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1.
A 2.4GHz CMOS Monolithic Transceiver Front-End for IEEE 802.11b Wireless LAN Applications 总被引:1,自引:3,他引:1
A 2.4GHz CMOS monolithic transceiver front-end for IEEE 802.11b wireless LAN applications is presented.The receiver and transmitter are both of superheterodyne structure for good system performance.The front-end consists of five blocks:low noise amplifier,down-converter,up-converter, pre-amplifier,and LO buffer.Their input/output impedance are all on-chip matched to 50Ω except the down-converter which has open-drain outputs.The transceiver RF front-end has been implemented in a 0.18μm CMOS process.When the LNA and the down-converter are directly connected,the measured noise figure is 5.2dB,the measured available power gain 12.5dB,the input 1dB compression point -18dBm,and the third-order input intercept point -7dBm.The receiver front-end draws 13.6mA currents from the 1.8V power supply.When the up-converter and pre-amplifier are directly connected,the measured noise figure is 12.4dB,the power gain is 23.8dB,the output 1dB compression point is 15dBm,and the third-order output intercept point is 16dBm.The transmitter consumes 276mA current from the 1.8V power supply. 相似文献
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60 GHz宽带无线通信射频芯片研究进展 总被引:1,自引:0,他引:1
60GHz无线通信技术由于其超高速的数据传输能力,将成为第4代无线通信技术的代表,引发了学术界和工业界研究热潮。近几年,随着半导体技术的发展,基于不同工艺的60GHz宽带无线通信射频芯片已经不断有报道。文中跟踪了近些年国外60GHz无线技术研究情况,分别从应用、技术特点、标准状况和芯片研究进展等方面介绍了60GHz宽带无线通信系统及其发展趋势。 相似文献
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Seok‐Bong Hyun Geum‐Young Tak Sun‐Hee Kim Byung‐Jo Kim Jinho Ko Seong‐Su Park 《ETRI Journal》2004,26(3):229-240
This paper reports on our development of a dual‐mode transceiver for a CMOS high‐rate Bluetooth system‐on‐chip solution. The transceiver includes most of the radio building blocks such as an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, a variable gain amplifier (VGA), a dc offset cancellation circuit, a quadrature local oscillator (LO) generator, and an RF front‐end. It is designed for both the normal‐rate Bluetooth with an instantaneous bit rate of 1 Mb/s and the high‐rate Bluetooth of up to 12 Mb/s. The receiver employs a dualconversion combined with a baseband dual‐path architecture for resolving many problems such as flicker noise, dc offset, and power consumption of the dual‐mode system. The transceiver requires none of the external image‐rejection and intermediate frequency (IF) channel filters by using an LO of 1.6 GHz and the fifth order on‐chip filters. The chip is fabricated on a 6.5‐mm2 die using a standard 0.25‐μm CMOS technology. Experimental results show an in‐band image‐rejection ratio of 40 dB, an IIP3 of ?5 dBm, and a sensitivity of ?77 dBm for the Bluetooth mode when the losses from the external components are compensated. It consumes 42 mA in receive π/4‐diffrential quadrature phase‐shift keying (π/4‐DQPSK) mode of 8 Mb/s, 35 mA in receive GFSK mode of 1 Mb/s, and 32 mA in transmit mode from a 2.5‐V supply. These results indicate that the architecture and circuits are adaptable to the implementation of a low‐cost, multi‐mode, high‐speed wireless personal area network. 相似文献
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采用0.18μm Si RFCMOS工艺设计了应用于s波段AESA的高集成度射频收发前端芯片。系统由发射与接收前端组成,包括低噪声放大器、混频器、可变增益放大器、驱动放大器和带隙基准电路。后仿真结果表明,在3.3V电源电压下,发射前端工作电流为85mA,输出ldB压缩点为5.0dBm,射频输出在2~3.5GHz频带内电压增益为6.3~9.2dB,噪声系数小于14.5dB;接收前端工作电流为50mA,输入1dB压缩点为-5.6dBm,射频输入在2~3.5GHz频带内电压增益为12—14.5dB,噪声系数小于11dB;所有端口电压驻波比均小于1.8:芯片面积1.8×2.6mm0。 相似文献
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The evolution of satellite communication systems for the design of both the satellite’s communication payload and the ground-station
are towards the implementation of such systems using the Software Radio (SR) technology. This paper focuses on a key element
of the SR, that is, the wideband front-end which still poses the greatest technological challenge for design and proliferation
of SR. In particular, we look at the front-end architecture of wideband receivers, outline the key aspects of the design of
such front-end systems, specify the performance metrics associated with their design, present an architecture of a promising
wideband analog to digital converter, and finally present the results of our design, implementation, and test campaign of
a prototype PC-based SR system.
This revised version was published online in July 2006 with corrections to the Cover Date. 相似文献
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C波段CMOS射频前端电路设计与实现 总被引:1,自引:0,他引:1
设计了一款工作在C波段(4.2 GHz)的CMOS射频前端电路,电路包括低噪声放大器和Gilbert型有源双平衡混频器.其中低噪声放大器采用共源和共栅放大器方式,实现了单端输入到差分输出的变换;而混频器的输出端采用电感负载形式.电路采用SMIC 0.18μmRF工艺实现,测试结果表明,混频器的输出频率约为700 MHz,电路的功率增益为24 dB,单边带噪声指数为8 dB,在1.8 V工作电压下,电路总功耗为36 mW. 相似文献
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ZHAO Wenhu WANG Zhigong 《电子学报:英文版》2008,(2):386-388
This paper describes a configurable transceiver which can realize multiple operation modes to meet various fiber communication standards. With this configurable architecture, the transceiver can operate in 2:1, 3:1, 4:1, 5:1, 6:1, 8:1, 10:1 multiplexing modes and 1:2, 1:3, 1:4, 1:5, 1:6, 1:8, 1:10 demultiplexing modes with internal synchronized clock signals. Comma detection and word alignment circuits are also included in the receiver to meet the standards using 8B/10B code. This configurable multi-mode transceiver has been implemented in a 0.25μm CMOS technology. 相似文献
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Kåre T. Christensen Thomas H. Lee Erik Bruun 《Analog Integrated Circuits and Signal Processing》2005,42(1):55-64
This paper presents a highly programmable front-end filter and amplifier intended to replace SAW filters and low noise amplifiers (LNA) in multi-mode direct conversion radio receivers. The filter has a 42 MHz bandwidth, is tunable from 1850 to 2400 MHz, achieves a 5.8 dB NF, –25 dBm in-band 1-dB input compression point (ICP) and 0 dBm out-of-band ICP while drawing 26 mA from a 2.5 V supply.Kâre T. Christensen received the M.Sc. and Ph.D. degrees in electrical engineering from the Technical University of Denmark in 1997 and 2002, respectively.In 1995-96 he was a visiting scholar working on switched current memory cells at the Spanish National Microelectronics Centre in Seville. In 1997 he worked on an asynchronous embedded MIPS16/MIPS32 microprocessor core for LSI Logic. In 1999-2000 he was a visiting researcher at Stanford University. During his stay he worked on fully integrated RF front-end filters in CMOS.From 1998 to 2002 he worked for Nokia Mobile Phones conducting research in the design of RF ICs for multi-band GSM terminals. He currently works for the Danish hearing aid manufacturer Oticon A/S designing micro-power RF circuits and systems in CMOS.He has lectured on several occasions at the Technical University of Denmark and other universities. He has authored or co-authored nine papers and holds three U.S. patents.Thomas H. Lee received the S.B., S.M. and Sc.D. degrees in electrical engineering, all from the Massachusetts Institute of Technology in 1983, 1985, and 1990, respectively.He joined Analog Devices in 1990 where he was primarily engaged in the design of high-speed clock recovery devices. In 1992, he joined Rambus Inc. in Mountain View, CA where he developed high-speed analog circuitry for 500 megabyte/s CMOS DRAMs.He has also contributed to the development of PLLs in the StrongARM, Alpha and AMD K6/K7/K8 microprocessors. Since 1994, he has been a Professor of Electrical Engineering at Stanford University where his research focus has been on gigahertz-speed wireline and wireless integrated circuits built in conventional silicon technologies, particularly CMOS.He has twice received the Best Paper award at the International Solid-State Circuits Conference, co-authored a Best Student Paper at ISSCC, was awarded the Best Paper prize at CICC, and is a Packard Foundation Fellowship recipient.He is an IEEE Distinguished Lecturer of both the Solid-State Circuits and Microwave Societies. He holds 35 U.S. patents and authored The Design of CMOS Radio-Frequency Integrated Circuits (now in its second edition), and Planar Microwave Engineering, both with Cambridge University Press. He is a co-author of four additional books on RF circuit design, and also cofounded Matrix Semiconductor.Erik Bruun received the M.Sc. and Ph.D. degrees in electrical engineering in 1974 and 1980, respectively, from the Technical University of Denmark. In 1980 he received the B.Com. degree from the Copenhagen Business School. In 2000 he also received the dr. techn. degree from the Technical University of Denmark.From January 1974 to September 1974 he was with Christian Rovsing A/S, working on the development of space electronics and test equipment for space electronics. From 1974 to 1980 he was with the Laboratory for Semiconductor Technology at the Technical University of Denmark, working in the fields of MNOS memory devices, IL devices, bipolar analog circuits, and custom integrated circuits. From 1980 to 1984 he was with Christian Rovsing A/S. From 1984 to 1989 he was the managing director of Danmos Microsystems ApS. Since 1989 he has been a Professor of analog electronics at the Technical University of Denmark where he has served as head of the Sector of Information Technology, Electronics, and Mathematics from 1995 to 2001. Since 2001 he has been head of ÿrstedïDTU.His current research interests are in the areas of RF integrated circuit design and integrated circuits for mobile phones. 相似文献
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设计了一款用于中国60 GHz标准频段的射频接收前端电路。该射频接收前端采用直接变频结构,将59~64 GHz的微波信号下变频至5~10 GHz的中频信号。射频前端包括一个四级低噪声放大器和电流注入式的吉尔伯特单平衡混频器。LNA设计中考虑了ESD的静电释放路径。后仿真表明,射频接收前端的转换增益为13.5~17.5 dB,双边带噪声因子为6.4~7.8 dB,输入1 dB压缩点为-23 dBm。电路在1.2 V电源电压下功耗仅为38.4 mW。该射频接收前端电路采用IBM 90 nm CMOS工艺设计,芯片面积为0.65 mm2。 相似文献
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利用PIC中档单片机优越特性,实现参数全部由软件设定的PPM信号调制;用软件同时完成PPM信号的编码和解码.以单片机最小系统实现一个简洁可靠、成本低廉的PPM调制全双工激光无线通信收发器,该收发器为两个数据终端之间提供一条透明的通用异步串行数据传输通道。 相似文献
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利用PIC中档单片机优越特性,实现参数全部由软件设定的PPM信号调制;用软件同时完成PPM 信号的编码和解码。以单片机最小系统实现一个简洁可靠、成本低廉的PPM调制全双工激光无线通信收发器,该收发器为两个数据终端之间提供一条透明的通用异步串行数据传输通道。 相似文献
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A fully integrated CMOS DCS-1800 frequency synthesizer 总被引:2,自引:0,他引:2
A prototype frequency synthesizer for the DCS-1800 system has been integrated in a standard 0.4 μm CMOS process without any external components. A completely monolithic design has been made feasible by using an optimized hollow-coil inductor low-phase-noise voltage-controlled oscillator (VCO). The frequency divider is an eight-modulus phase-switching prescaler that achieves the same speed as asynchronous dividers. The die area was minimized by using a dual-path active loop filter. An indirect linearization technique was implemented for the VCO gain. The resulting architecture is a fourth-order, type-2 charge-pump phase-locked loop. The measured settling time is 300 μs, and the phase noise is up to -123 dBc/Hz at 600 kHz and -138 dBc/Hz at 3 MHz offset 相似文献
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This paper presents a direct‐conversion CMOS transceiver for fully digital DS‐UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase‐locked loop (PLL), and a voltage controlled oscillator (VCO). A single‐ended‐to‐differential converter is implemented in the down‐conversion mixer and a differential‐to‐single‐ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 mm2 die using standard 0.18 µm CMOS technology and a 64‐pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low‐power, and high‐speed wireless personal area network. 相似文献
17.
Dirk K. Neumann Michael W. Hoffman Sina Balkır 《Circuits, Systems, and Signal Processing》2008,27(3):381-390
Many ultra-wideband (UWB) systems are challenged by strong jammers and narrowband interferers. Using two antennas, we demonstrate
a robust UWB radio frequency (RF) front-end design in a 0.25 μm mixed-signal complementary metal oxide semiconductor (CMOS)
technology. The proposed realization is capable of adaptively removing a high-power, narrowband interferer early in the receiver
chain avoiding front-end saturation and preserving UWB signal power. The early interferer removal resulting in interferer-free
demodulation is based on the least mean squares (LMS) algorithm and achieved through a novel combiner low-noise amplifier
and noise optimized filtering. Circuit level RF simulations of the proposed circuitry indicate a maximum improvement in signal-to-interference
ratio of 39.6 dB. 相似文献
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A Single-Chip CMOS Transceiver for UHF Mobile RFID Reader 总被引:4,自引:0,他引:4
Ickjin Kwon Yunseong Eo Heemun Bang Kyudon Choi Sangyoon Jeon Sungjae Jung Donghyun Lee Heungbae Lee 《Solid-State Circuits, IEEE Journal of》2008,43(3):729-738
This paper describes a single-antenna low-power single-chip radio frequency identification (RFID) reader for mobile phone applications. The reader integrates an RF transceiver, data converters, a digital baseband modem, an MPU, memory, and host interfaces. The direct conversion RF receiver architecture with the highly linear RF front-end circuit and DC offset cancellation circuit is used to give good immunity to the large transmitter leakage. It is suitable for a mobile phone reader with single-antenna architecture and low-power reader solution. The transmitter is implemented in the direct I/Q up-conversion architecture. The frequency synthesizer based on a fractional-N phase-locked-loop topology offering 900 MHz quadrature LO signals is also integrated with the RF transceiver. The reader is fabricated in a 0.18 mum CMOS technology, and its die size is 4.5 mm times 5.3 mm including electrostatic discharge I/O pads. The reader consumes a total current of 89 mA apart from the external power amplifier with 1.8 V supply voltage. It achieves an 8 dBm P1dB, an 18.5 dBm IIP3, and a maximum transmitter output power of 4 dBm. 相似文献