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1.
A 2.4GHz CMOS Monolithic Transceiver Front-End for IEEE 802.11b Wireless LAN Applications 总被引:1,自引:3,他引:1
A 2.4GHz CMOS monolithic transceiver front-end for IEEE 802.11b wireless LAN applications is presented.The receiver and transmitter are both of superheterodyne structure for good system performance.The front-end consists of five blocks:low noise amplifier,down-converter,up-converter, pre-amplifier,and LO buffer.Their input/output impedance are all on-chip matched to 50Ω except the down-converter which has open-drain outputs.The transceiver RF front-end has been implemented in a 0.18μm CMOS process.When the LNA and the down-converter are directly connected,the measured noise figure is 5.2dB,the measured available power gain 12.5dB,the input 1dB compression point -18dBm,and the third-order input intercept point -7dBm.The receiver front-end draws 13.6mA currents from the 1.8V power supply.When the up-converter and pre-amplifier are directly connected,the measured noise figure is 12.4dB,the power gain is 23.8dB,the output 1dB compression point is 15dBm,and the third-order output intercept point is 16dBm.The transmitter consumes 276mA current from the 1.8V power supply. 相似文献
2.
《半导体学报》2005,26(9)
实现了一个应用于IEEE 802.11b无线局域网系统的2.4GHz CMOS单片收发机射频前端,它的接收机和发射机都采用了性能优良的超外差结构.该射频前端由五个模块组成:低噪声放大器、下变频器、上变频器、末前级和LO缓冲器.除了下变频器的输出采用了开漏级输出外,各模块的输入、输出端都在片匹配到50Ω.该射频前端已经采用0.18μm CMOS工艺实现.当低噪声放大器和下变频器直接级联时,测量到的噪声系数约为5.2dB,功率增益为12.5dB,输入1dB压缩点约为-18dBm,输入三阶交调点约为-7dBm.当上变频器和末前级直接级联时,测量到的噪声系数约为12.4dB,功率增益约为23.8dB,输出1dB压缩点约为1.5dBm,输出三阶交调点约为16dBm.接收机射频前端和发射机射频前端都采用1.8V电源,消耗的电流分别为13.6和27.6mA. 相似文献
3.
A single-chip low-power transceiver IC operating in the 2.4 GHz ISM band is presented. Designed in 0.18μm CMOS, the transceiver system employs direct-conversion architecture for both the receiver and transmitter to realize a fully integrated wireless LAN product. A sigma-delta (∑△) fractional-N frequency synthesizer provides on-chip quadrature local oscillator frequency. Measurement results show that the receiver achieves a maximum gain of 81 dB and a noise figure of 8.2 dB, the transmitter has maximum output power of -3.4 dBm and RMS EVM of 6.8%. Power dissipation of the transceiver is 74 mW in the receiving mode and 81 mW in the transmitting mode under a supply voltage of 1.8 V, including 30 mW consumed by the frequency synthesizer. The total chip area with pads is 2.7 × 4.2 mm^2. 相似文献
4.
W波段(75~110 GHz)拥有大可用带宽、低大气损耗、短波长以及在多尘和多雾条件下工作的能力,因此具有巨大的应用潜力,涵盖从通信、传感、成像到短程高速数据通信的多个领域。因此,W波段收发机的研究和应用受到了越来越多的关注。本文提出了基于耦合线的收发开关、移相器和衰减器,旨在对应用于W波段的CMOS毫米波相控阵收发机芯片中重要模块和关键技术予以研究。其中,收发开关在复用为功率放大器的输出匹配网络和低噪声放大器的输入匹配网络的同时有效降低了插入损耗,移相器和衰减器实现了极高的分辨率。以上3个关键模块的实现原理和电路设计均在文中进行了详细的阐述,并通过了流片验证。仿真结果和测试结果说明了采用CMOS工艺制造W波段相控阵芯片的可实现性。 相似文献
5.
60 GHz宽带无线通信射频芯片研究进展 总被引:1,自引:0,他引:1
60GHz无线通信技术由于其超高速的数据传输能力,将成为第4代无线通信技术的代表,引发了学术界和工业界研究热潮。近几年,随着半导体技术的发展,基于不同工艺的60GHz宽带无线通信射频芯片已经不断有报道。文中跟踪了近些年国外60GHz无线技术研究情况,分别从应用、技术特点、标准状况和芯片研究进展等方面介绍了60GHz宽带无线通信系统及其发展趋势。 相似文献
6.
Seok‐Bong Hyun Geum‐Young Tak Sun‐Hee Kim Byung‐Jo Kim Jinho Ko Seong‐Su Park 《ETRI Journal》2004,26(3):229-240
This paper reports on our development of a dual‐mode transceiver for a CMOS high‐rate Bluetooth system‐on‐chip solution. The transceiver includes most of the radio building blocks such as an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, a variable gain amplifier (VGA), a dc offset cancellation circuit, a quadrature local oscillator (LO) generator, and an RF front‐end. It is designed for both the normal‐rate Bluetooth with an instantaneous bit rate of 1 Mb/s and the high‐rate Bluetooth of up to 12 Mb/s. The receiver employs a dualconversion combined with a baseband dual‐path architecture for resolving many problems such as flicker noise, dc offset, and power consumption of the dual‐mode system. The transceiver requires none of the external image‐rejection and intermediate frequency (IF) channel filters by using an LO of 1.6 GHz and the fifth order on‐chip filters. The chip is fabricated on a 6.5‐mm2 die using a standard 0.25‐μm CMOS technology. Experimental results show an in‐band image‐rejection ratio of 40 dB, an IIP3 of ?5 dBm, and a sensitivity of ?77 dBm for the Bluetooth mode when the losses from the external components are compensated. It consumes 42 mA in receive π/4‐diffrential quadrature phase‐shift keying (π/4‐DQPSK) mode of 8 Mb/s, 35 mA in receive GFSK mode of 1 Mb/s, and 32 mA in transmit mode from a 2.5‐V supply. These results indicate that the architecture and circuits are adaptable to the implementation of a low‐cost, multi‐mode, high‐speed wireless personal area network. 相似文献
7.
采用0.18μm Si RFCMOS工艺设计了应用于s波段AESA的高集成度射频收发前端芯片。系统由发射与接收前端组成,包括低噪声放大器、混频器、可变增益放大器、驱动放大器和带隙基准电路。后仿真结果表明,在3.3V电源电压下,发射前端工作电流为85mA,输出ldB压缩点为5.0dBm,射频输出在2~3.5GHz频带内电压增益为6.3~9.2dB,噪声系数小于14.5dB;接收前端工作电流为50mA,输入1dB压缩点为-5.6dBm,射频输入在2~3.5GHz频带内电压增益为12—14.5dB,噪声系数小于11dB;所有端口电压驻波比均小于1.8:芯片面积1.8×2.6mm0。 相似文献
8.
提出了一种使用品质因数增强型的有源电感的射频带通滤波器,描述了在宽射频频段上可调谐的品质因数增强型的有源电感设计技术,而且解释了与有源电感噪声和稳定性相关的问题.该滤波器采用0.18μm CMOS工艺制造,它所占用芯片的有效面积仅为150μm×200μm.测试结果表明:该射频滤波器中心频率为2.44GHz时,3dB带宽为60MHz,中心频率可在2.07~2.44GHz范围内调谐,1dB压缩点为-15dBm,而静态功耗为10.8mW;在中心频率为2.07GHz时,滤波器的品质因数可达到103. 相似文献
9.
基于0.18 μm CMOS工艺,设计了一种面向低速率低功耗应用的2.4 GHz射频前端电路,包含2个单刀双掷开关、1个功率放大器和1个低噪声放大器。采用栅衬浮动电压偏置技术对传统单刀双掷开关进行了改进,以提高其线性度;功率放大器采用两级放大结构,对全集成的低噪声放大器进行了噪声优化;集成了输入输出匹配网络,采用了到地电感,以提高输入输出端的ESD性能。在接收模式时,电路的静态电流为10.7 mA,增益为11.7 dB,IIP3为2.1 dBm,噪声系数为3.4 dB。在发射模式时,电路的静态电流为17.4 mA,功率增益为17.7 dB,输出P1dB为20 dBm,饱和功率为21.4 dBm,最大PAE为23.8%,在输出功率为20 dBm时的频谱满足802.15.4协议要求。 相似文献
10.
提出了一种使用品质因数增强型的有源电感的射频带通滤波器,描述了在宽射频频段上可调谐的品质因数增强型的有源电感设计技术,而且解释了与有源电感噪声和稳定性相关的问题.该滤波器采用0.18μm CMOS工艺制造,它所占用芯片的有效面积仅为150μm×200μm.测试结果表明:该射频滤波器中心频率为2.44GHz时,3dB带宽为60MHz,中心频率可在2.07~2.44GHz范围内调谐,1dB压缩点为-15dBm,而静态功耗为10.8mW;在中心频率为2.07GHz时,滤波器的品质因数可达到103. 相似文献
11.
The evolution of satellite communication systems for the design of both the satellite’s communication payload and the ground-station
are towards the implementation of such systems using the Software Radio (SR) technology. This paper focuses on a key element
of the SR, that is, the wideband front-end which still poses the greatest technological challenge for design and proliferation
of SR. In particular, we look at the front-end architecture of wideband receivers, outline the key aspects of the design of
such front-end systems, specify the performance metrics associated with their design, present an architecture of a promising
wideband analog to digital converter, and finally present the results of our design, implementation, and test campaign of
a prototype PC-based SR system.
This revised version was published online in July 2006 with corrections to the Cover Date. 相似文献
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C波段CMOS射频前端电路设计与实现 总被引:1,自引:0,他引:1
设计了一款工作在C波段(4.2 GHz)的CMOS射频前端电路,电路包括低噪声放大器和Gilbert型有源双平衡混频器.其中低噪声放大器采用共源和共栅放大器方式,实现了单端输入到差分输出的变换;而混频器的输出端采用电感负载形式.电路采用SMIC 0.18μmRF工艺实现,测试结果表明,混频器的输出频率约为700 MHz,电路的功率增益为24 dB,单边带噪声指数为8 dB,在1.8 V工作电压下,电路总功耗为36 mW. 相似文献
15.
针对未来智能驾驶和无人驾驶对毫米波传感器多模式、多场景感知需求,设计并实现了一种77GHz多模毫米波雷达收发机芯片。芯片采用65nm CMOS工艺,集成了3路雷达发射机和4路接收机、调频连续波(FMCW)波形发生器、模数转换器以及高速数据接口等电路。利用交叉耦合中和电容技术提升了CMOS工艺上毫米波低噪声放大器、毫米波片上功放等电路性能,采用两点调制锁相环技术提升了FMCW信号带宽和调制速率。收发机的发射功率、波形样式、接收增益和带宽等参数具有较好的可配置性,满足未来多模式、小型化和低成本汽车雷达传感器需求。芯片测试结果显示,在76~81GHz频率范围内,接收机实现50dB的增益控制,最小噪声系数11dB,FMCW信号调频带宽达4.2GHz,调制速率达233MHz/μs,线性度优于0.1%,-45~+125℃全温范围内发射机典型输出功率大于13dBm。 相似文献
16.
ZHAO Wenhu WANG Zhigong 《电子学报:英文版》2008,(2):386-388
This paper describes a configurable transceiver which can realize multiple operation modes to meet various fiber communication standards. With this configurable architecture, the transceiver can operate in 2:1, 3:1, 4:1, 5:1, 6:1, 8:1, 10:1 multiplexing modes and 1:2, 1:3, 1:4, 1:5, 1:6, 1:8, 1:10 demultiplexing modes with internal synchronized clock signals. Comma detection and word alignment circuits are also included in the receiver to meet the standards using 8B/10B code. This configurable multi-mode transceiver has been implemented in a 0.25μm CMOS technology. 相似文献
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18.
A single-chip low-power transceiver IC operating in the 2.4 GHz ISM band is presented. Designed in 0.18 μm CMOS, the transceiver system employs direct-conversion architecture for both the receiver and transmitter to realize a fully integrated wireless LAN product. A sigma-delta (∑△) fractional-N frequency synthesizer provides on-chip quadrature local oscillator frequency. Measurement results show that the receiver achieves a maximum gain of 81 dB and a noise figure of 8.2 dB, the transmitter has maximum output power of-3.4 dBm and RMS EVM of 6.8%. Power dissipation of the transceiver is 74 mW in the receiving mode and 81 mW in the transmitting mode under a supply voltage of 1.8 V, including 30 mW consumed by the frequency synthesizer. The total chip area with pads is 2.7×4.2 mm2. 相似文献
19.
Kåre T. Christensen Thomas H. Lee Erik Bruun 《Analog Integrated Circuits and Signal Processing》2005,42(1):55-64
This paper presents a highly programmable front-end filter and amplifier intended to replace SAW filters and low noise amplifiers (LNA) in multi-mode direct conversion radio receivers. The filter has a 42 MHz bandwidth, is tunable from 1850 to 2400 MHz, achieves a 5.8 dB NF, –25 dBm in-band 1-dB input compression point (ICP) and 0 dBm out-of-band ICP while drawing 26 mA from a 2.5 V supply.Kâre T. Christensen received the M.Sc. and Ph.D. degrees in electrical engineering from the Technical University of Denmark in 1997 and 2002, respectively.In 1995-96 he was a visiting scholar working on switched current memory cells at the Spanish National Microelectronics Centre in Seville. In 1997 he worked on an asynchronous embedded MIPS16/MIPS32 microprocessor core for LSI Logic. In 1999-2000 he was a visiting researcher at Stanford University. During his stay he worked on fully integrated RF front-end filters in CMOS.From 1998 to 2002 he worked for Nokia Mobile Phones conducting research in the design of RF ICs for multi-band GSM terminals. He currently works for the Danish hearing aid manufacturer Oticon A/S designing micro-power RF circuits and systems in CMOS.He has lectured on several occasions at the Technical University of Denmark and other universities. He has authored or co-authored nine papers and holds three U.S. patents.Thomas H. Lee received the S.B., S.M. and Sc.D. degrees in electrical engineering, all from the Massachusetts Institute of Technology in 1983, 1985, and 1990, respectively.He joined Analog Devices in 1990 where he was primarily engaged in the design of high-speed clock recovery devices. In 1992, he joined Rambus Inc. in Mountain View, CA where he developed high-speed analog circuitry for 500 megabyte/s CMOS DRAMs.He has also contributed to the development of PLLs in the StrongARM, Alpha and AMD K6/K7/K8 microprocessors. Since 1994, he has been a Professor of Electrical Engineering at Stanford University where his research focus has been on gigahertz-speed wireline and wireless integrated circuits built in conventional silicon technologies, particularly CMOS.He has twice received the Best Paper award at the International Solid-State Circuits Conference, co-authored a Best Student Paper at ISSCC, was awarded the Best Paper prize at CICC, and is a Packard Foundation Fellowship recipient.He is an IEEE Distinguished Lecturer of both the Solid-State Circuits and Microwave Societies. He holds 35 U.S. patents and authored The Design of CMOS Radio-Frequency Integrated Circuits (now in its second edition), and Planar Microwave Engineering, both with Cambridge University Press. He is a co-author of four additional books on RF circuit design, and also cofounded Matrix Semiconductor.Erik Bruun received the M.Sc. and Ph.D. degrees in electrical engineering in 1974 and 1980, respectively, from the Technical University of Denmark. In 1980 he received the B.Com. degree from the Copenhagen Business School. In 2000 he also received the dr. techn. degree from the Technical University of Denmark.From January 1974 to September 1974 he was with Christian Rovsing A/S, working on the development of space electronics and test equipment for space electronics. From 1974 to 1980 he was with the Laboratory for Semiconductor Technology at the Technical University of Denmark, working in the fields of MNOS memory devices, IL devices, bipolar analog circuits, and custom integrated circuits. From 1980 to 1984 he was with Christian Rovsing A/S. From 1984 to 1989 he was the managing director of Danmos Microsystems ApS. Since 1989 he has been a Professor of analog electronics at the Technical University of Denmark where he has served as head of the Sector of Information Technology, Electronics, and Mathematics from 1995 to 2001. Since 2001 he has been head of ÿrstedïDTU.His current research interests are in the areas of RF integrated circuit design and integrated circuits for mobile phones. 相似文献
20.
设计了一款用于中国60 GHz标准频段的射频接收前端电路。该射频接收前端采用直接变频结构,将59~64 GHz的微波信号下变频至5~10 GHz的中频信号。射频前端包括一个四级低噪声放大器和电流注入式的吉尔伯特单平衡混频器。LNA设计中考虑了ESD的静电释放路径。后仿真表明,射频接收前端的转换增益为13.5~17.5 dB,双边带噪声因子为6.4~7.8 dB,输入1 dB压缩点为-23 dBm。电路在1.2 V电源电压下功耗仅为38.4 mW。该射频接收前端电路采用IBM 90 nm CMOS工艺设计,芯片面积为0.65 mm2。 相似文献