A CMOS Quadrature Baseband Frequency Synthesizer/Modulator

A quadrature baseband frequency synthesizer/modulator IC has been designed and fabricated in a 0.5 m CMOS. This quadrature baseband frequency synthesizer/modulator is intended for use in a wide variety of indoor/outdoor portable wireless applications in the 2.4–2.4835 GHz ISM frequency band. This frequency synthesizer/modulator is a capable of frequency and phase modulation. The major components are: a quadrature direct digital synthesizer, digital-to-analog converters and lowpass filters. By programming the quadrature direct digital synthesizer, adaptive channel bandwidths, modulation formats, frequency hopping and data rates are easily achieved. The quadrature baseband direct digital synthesizer produces an 80 MHz frequency band. The quadrature baseband spectrum could be upconverted with off-chip mixers into the 2.4 GHz ISM frequency band. The chip has a complexity of 17,803 transistors with a die area of 24 mm² and a core area of 9 mm². The power dissipation is 496 mW at 3.3 V.     

A Dual‐Mode 2.4‐GHz CMOS Transceiver for High‐Rate Bluetooth Systems

This paper reports on our development of a dual‐mode transceiver for a CMOS high‐rate Bluetooth system‐on‐chip solution. The transceiver includes most of the radio building blocks such as an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, a variable gain amplifier (VGA), a dc offset cancellation circuit, a quadrature local oscillator (LO) generator, and an RF front‐end. It is designed for both the normal‐rate Bluetooth with an instantaneous bit rate of 1 Mb/s and the high‐rate Bluetooth of up to 12 Mb/s. The receiver employs a dualconversion combined with a baseband dual‐path architecture for resolving many problems such as flicker noise, dc offset, and power consumption of the dual‐mode system. The transceiver requires none of the external image‐rejection and intermediate frequency (IF) channel filters by using an LO of 1.6 GHz and the fifth order on‐chip filters. The chip is fabricated on a 6.5‐mm² die using a standard 0.25‐μm CMOS technology. Experimental results show an in‐band image‐rejection ratio of 40 dB, an IIP3 of ?5 dBm, and a sensitivity of ?77 dBm for the Bluetooth mode when the losses from the external components are compensated. It consumes 42 mA in receive π/4‐diffrential quadrature phase‐shift keying (π/4‐DQPSK) mode of 8 Mb/s, 35 mA in receive GFSK mode of 1 Mb/s, and 32 mA in transmit mode from a 2.5‐V supply. These results indicate that the architecture and circuits are adaptable to the implementation of a low‐cost, multi‐mode, high‐speed wireless personal area network.     

Low Noise Wide Tuning Range Quadrature Ring Oscillator for Multi-Standard Transceiver

This letter presents a low phase noise quadrature ring oscillator with new start-up circuit. The oscillator architecture is a two-stage differential ring with an additional pair of transition-assistance transistors. The circuit was implemented in 0.18 $mu{rm m}$ CMOS technology and the measured tuning range of the prototype device is from 1.7 GHz to 5.5 GHz and figure of merit (FOM) is ${- 162}~{rm dB}$. The proposed area of application is the core of the local oscillator in a multi-standard wireless transceiver.      

A 1.12 pJ/b Inductive Transceiver With a Fault-Tolerant Network Switch for Multi-Layer Wearable Body Area Network Applications

A near-field coupling transceiver integrated with a fault-tolerant network switch is implemented for inter-layer and intra-layer Wearable Body Area Network. The inductive coupling transceiver employs a Resonance Compensator (RC) with a digitally controlled on-chip capacitor bank and a variable hysteresis Schmitt Trigger to compensate dynamic and static variances of woven inductor, and it enables 10 Mbps wireless transaction with the reception energy of 1.12 pJ/b at 2.5 V supply. The network switch introduces new fault-tolerant protocol to eliminate the routing table and reduces power consumption by 70% compared with the conventional switch using torus topology. The transceiver with the switch and the RC are implemented in 0.25-$mu$m 1P5M CMOS process technology, occupying 2.0 mm$^{2}$ and 0.8 mm$^{2}$ area, respectively.      

Digital Modulator with Bandpass Delta-Sigma Modulator

A digital quadrature modulator with a bandpass -modulator is presented that interpolates orthogonal input carriers by 16 and performs a digital quadrature modulation at carrier frequencies f_s/4, –f_s/4 (f_s is the sampling frequency). After quadrature modulation, the signal is converted into an analogue IF signal using a bandpass modulator and a 1-bit D/A converter. The die area of the chip is 5.2 mm² (0.13 m CMOS technology). The total power consumption is 139 mW at 1.5 V with a clock frequency of 700 MHz (D/A converter full-scale output current 11.5 mA).     

BER Evaluation of IEEE 802.15.4 Compliant Wireless Sensor Networks Under Various Fading Channels

This paper presents bit error rate (BER) analysis of wireless sensor networks (WSNs) consisting of sensor nodes based on an IEEE 802.15.4 RF transceiver. Closed-form expressions for BER are obtained for WSNs operating over AWGN, Rayleigh and Nakagami-m fading channels. For the purpose of analysis, we consider an IEEE 802.15.4 RF transceiver using direct sequence spread spectrum-offset quadrature phase shift keying (DSSS-OQPSK) modulation under 2.4 GHz frequency band in a WSN. Analytical expressions for BER are derived for a wireless link between sensor nodes that act as a transmitter unit and a base station without considering the effect of interferers in the wireless environment. Numerical results for BER are obtained by varying the IEEE 802.15.4 standard specific physical layer parameters, such as number of bits used to represent a Zigbee symbol, number of modulation levels used in an OQPSK modulator, and various values of Rayleigh and Nakagami-m fading parameters, denoted as \(\alpha \) and \(m\) , respectively. Moreover, optimum values of physical layer parameters are identified for improved system performance. It is found that error performance analysis of WSN shows improvement when lower number of bits is used to represent a Zigbee symbol. Specifically, under a Rayleigh fading channel which reflects a real-time WSN environment, the network exhibits better performance only when it is operated at high SNR values, i.e., BER of order \(10^{-2}\) is achieved when SNR lies in the range 5–15 dB. Also, the effect of fading parameters on network performance shows that better results are obtained for higher values of \(\alpha \) and \(m\) for Rayleigh and Nakagami-m fading channels, respectively.     

Design and Implementation of a Low Complexity VLSI Turbo-Code Decoder Architecture for Low Energy Mobile Wireless Communications

Channel coding is commonly incorporated to obtain sufficient reception quality in wireless mobile communications transceiver to counter channel degradation due to intersymbol interference, multipath dispersion, and thermal noise induced by electronic circuit devices. For low energy mobile wireless communications, it is highly desirable to incorporate a decoder which has a very low power consumption while achieving a high coding gain. In this paper, a sub-optimal low-complexity multi-stage pipeline decoder architecture for a powerful channel coding technique known as turbo-code is presented. The presented architecture avoids complex operations such as exponent and logarithmic computations. The turbo-code decoding algorithm is reformulated for an efficient VLSI implementation. Furthermore, the communication channel statistic estimation process has been completely eliminated. The architecture has been designed and implemented with the 0.6 m CMOS standard cell technology using Epoch computer aided design tool. The performance and the circuit complexity of the turbo-code decoder are evaluated and compared with the other types of well-known decoders. The power consumption of the low-complexity turbo-code decoder is comparable to that of the conventional convolutional-code decoder. However, the low-complexity turbo-code decoder has a significant coding gain over the conventional convolutional-code decoders and it is well suited for very low power applications.     

A polyphase filter based on CMOS inverters

A new idea for generation of quadrature signals on chip is presented. The topology is based on a passive RC polyphase filter, where the resistive parts are made active by using inverters. The active filter combines quadrature generation, isolation, and gain without losing quadrature performance compared to a regular RC polyphase filter. The filter technique is demonstrated in a 10 GHz front-end application where a broadband VCO, having a tuning range of 1.44 GHz, drives an active polyphase filter to generate quadrature LO signals. According to simulations the quadrature phase error shows a typical tuned behavior and stays below 0.8° for the complete tuning range. Since the signal amplitude is high throughout the filter the noise is low, below 160 dBc/Hz at 10 MHz offset. The high amplitude also reduces the need for high gain tuned buffers, thereby enabling significant reductions in chip area.     

Analysis and design of a frequency-hopped spread-spectrumtransceiver for wireless personal communications

Personal communications services (PCS) require low-power radio technologies. One such transceiver architecture employing frequency-hopped spread-spectrum techniques is presented. System features such as antenna diversity with equal-gain combining and sequential hop combining are incorporated into the transceiver design to achieve robust wireless digital data transmission over fading channels. A direct-conversion architecture from radio frequency (RF) to baseband reduces the overall power consumption by eliminating intermediate frequency (IF) components. High-rate frequency hopping with frequency-shift keying (FSK) modulation is implemented using a direct digital frequency synthesis technique. A multiplierless correlation FSK detector, suitable for direct-conversion receivers, has been designed for quadrature noncoherent detection. Robust acquisition algorithms based on energy detection and pattern matching and tracking architectures using digital phase-locked loops are also described for system synchronization. The proposed transceiver is well-suited for low-power PCS applications and other portable wireless communications     

A 1 V Wireless Transceiver for an Ultra-Low-Power SoC for Biotelemetry Applications

This paper presents a 1 V RF transceiver for biotelemetry and wireless body sensor network (WBSN) applications, realized as part of an ultra low power system-on-chip (SoC), the Sensiumtrade. The transceiver utilizes FSK/GFSK modulation at a data rate of 50 kbit/s to provide wireless connectivity between target sensor nodes and a central base-station node in a single-hop star network topology operating in the 862-870 MHz European short-range-device (SRD) and the 902-928 MHz North American Industrial, Scientific & Medical (ISM) frequency bands. Controlled by a proprietary media access controller (MAC) which is hardware implemented on chip, the transceiver operates half-duplex, achieving -102 dBm receiver input sensitivity (for 1E-3 raw bit error rate) and up to -7 dBm transmitter output power through a single antenna port. It consumes 2.1 mA during receive and up to 2.6 mA during transmit from a 0.9 to 1.5 V supply. It is fabricated in a 0.13 mum CMOS technology and occupies 7 mm² in a SoC die size of 4 times 4 mm².     

Polyphase Filter Approach for High Performance, FPGA-Based Quadrature Demodulation

The polyphase filter approach to quadrature demodulation is shown to be well suited for the implementation of purpose-designed wide bandwidth digital quadrature demodulators. The duplicated polyphase filter approach is introduced, as a way to increase the maximum allowable input signal bandwidth for a given implementation technology. Other algorithmic and architectural considerations specifically applicable to the realization of digital filters in low-cost Field-Programmable Gate Array (FPGA) technology are discussed. A design example suitable for processing input signals centered on an intermediate frequency of 160 MHz with a bandwidth of 45 MHz is presented. This design occupies 83% of the Configurable Logic Blocks (CLBs) in a low-cost Xilinx X4010E-3 FPGA. Additional techniques for further performance optimization are presented.     

Low‐Power Direct Conversion Transceiver for 915 MHz Band IEEE 802.15.4b Standard Based on 0.18 μm CMOS Technology

This paper presents the experimental results of a low‐power low‐cost RF transceiver for the 915 MHz band IEEE 802.15.4b standard. Low power and low cost are achieved by optimizing the transceiver architecture and circuit design techniques. The proposed transceiver shares the analog baseband section for both receive and transmit modes to reduce the silicon area. The RF transceiver consumes 11.2 mA in receive mode and 22.5 mA in transmit mode under a supply voltage of 1.8 V, in which 5 mA of quadrature voltage controlled oscillator is included. The proposed transceiver is implemented in a 0.18 μm CMOS process and occupies 10 mm² of silicon area.     

A 22–29-GHz UWB Pulse-Radar Receiver Front-End in 0.18-$mu{hbox{m}}$ CMOS

The design of a CMOS 22–29-GHz pulse-radar receiver (RX) front-end for ultra-wideband automotive radar sensors is presented. The chip includes a low-noise amplifier, in-phase/quadrature mixers, a quadrature voltage-controlled oscillator (QVCO), pulse formers, and baseband variable-gain amplifiers. Fabricated in a 0.18-$mu{hbox{m}}$ CMOS process, the RX front-end chip occupies a die area of 3 ${hbox{mm}}^{2}$. On-wafer measurements show a conversion gain of 35–38.1 dB, a noise figure of 5.5–7.4 dB, and an input return loss less than $-$14.5 dB in the 22–29-GHz automotive radar band. The phase noise of the constituent QVCO is $-$107 dBc/Hz at 1-MHz offset from a center frequency of 26.5 GHz. The total dc power dissipation of the RX including output buffers is 131 mW.      

A low power,low bandwidth protocol for remote wireless terminals

We present a low bandwidth protocol for wireless multimedia terminals targeted towards low power consumption on the terminal side. With the widespread use of portable computing devices, low power has become a major design criterion. One way of minimizing power consumption is to perform all tasks, other than managing hardware for the display and input, on a stationary workstation and exchange information between that workstation and the portable terminal via a wireless link. A protocol for such a system that emphasizes low bandwidth and low power requirements is presented herein. Such a protocol should address the issue of noisy wireless channels. We describe error correction and retransmission methods capable of dealing with burst error noise up to BERs of 10^-3. The final average bandwidth required is 140 Kbits/sec for 8bit color applications.     

Design of high-speed data transfer turbo code for body channel communication transceivers

In this work, a digital differential transmitter based on low-power wireless compensation transceiver for body channel communication (BCC) is proposed. Further, the proposed transceiver is composed of Touch Status Detection Unit (TSDU), Wireless Status Compensation Unit (WSCU), and a reconfigurable preamplifier. Initially, the human body channel environment for wireless communication is investigated based on properties from 1 to 100 MHz. Further, the turbo code-based encoding scheme is used to encode the data before transferring the data on the transmitter side. Also, the proposed error-correcting parallel turbo decoder using a modified step-by-step algorithm is presented. The turbo code-based decoding scheme is used to recover the error-free transmitted data at the receiver side. Results demonstrate that the proposed BCC transceiver is designed using 90 nm CMOS technology and it is observed that the proposed BCC transceiver has utilized an area of 600mm². Also, the maximum data rate achieved by a proposed BCC transceiver was 100 Mbps, and the overall transceiver power consumption is 0.42 mW, and energy for communication is 0.02 nj/b.     

A Zero-IF 60 GHz 65 nm CMOS Transceiver With Direct BPSK Modulation Demonstrating up to 6 Gb/s Data Rates Over a 2 m Wireless Link

This paper presents a directly modulated, 60 GHz zero-IF transceiver architecture suitable for single-carrier, low-power, multi-gigabit wireless links in nanoscale CMOS technologies. This mm-wave front end architecture requires no upconversion of the baseband signals in the transmitter and no analog-to-digital conversion in the receiver, thus minimizing system complexity and power consumption. All circuit blocks are realized using sub-1.0 V topologies, that feature only a single high-frequency transistor between the supply and ground, and which are scalable to future 45 nm, 32 nm, and 22 nm CMOS nodes. The transceiver is fabricated in a 65 nm CMOS process with a digital back-end. It includes a receiver with 14.7 dB gain and 5.6 dB noise figure, a 60 GHz LO distribution tree, a 69 GHz static frequency divider, and a direct BPSK modulator operating over the 55–65 GHz band at data rates exceeding 6 Gb/s. With both the transmitter and the receiver turned on, the chip consumes 374 mW from 1.2 V which reduces to 232 mW for a 1.0 V supply. It occupies 1.28$,times,$0.81 mm$^{2}$. The transceiver and its building blocks were characterized over temperature up to 85$^{circ}$ C and for power supplies down to 1 V. A manufacturability study of 60 GHz radio circuits is presented with measurements of transistors, the low-noise amplifier, and the receiver on slow, typical, and fast process splits. The transceiver architecture and performance were validated in a 1–6 Gb/s 2-meter wireless transmit-receive link over the 55–64 GHz range.      

A K-Band CMOS Quadrature Frequency Tripler Using Sub-Harmonic Mixer

A low-power frequency tripler is designed by using the sub-harmonic mixer configuration for K-band applications. The proposed circuit features quadrature signal generation, applicable to LO signal synthesis in millimeter-wave wireless transceivers. It achieves conversion gain of $-$5.7 dB at the output frequency of 21 GHz. Implemented in a 0.18 $mu{rm m}$ CMOS technology, the circuit consumes power of 7.5 mW with 1.5 V supply voltage. The entire die occupies an area of $1000times 1050 mu{rm m}^{2}$.      

Topology control in constant rate mobile ad hoc networks

Topology control is the problem of assigning power levels to the nodes of an ad hoc network so as to create a specified network topology while minimizing the energy consumed by the network nodes. While considerable theoretical attention has been given to the issue of topology control in wireless ad hoc networks, all of that prior work has concerned stationary networks. When the nodes are mobile, there is no algorithm that can guarantee a graph property (such as network connectivity) throughout the node movement. In this paper we study topology control in mobile wireless ad hoc networks (MANETs). We define a mobility model, namely the constant rate mobile network (CRMN) model, in which we assume that the speed and direction of each moving node are known. The goal of topology control under this model is to minimize the maximum power used by any network node in maintaining a specified monotone graph property. Network connectivity is one of the most fundamental monotone properties. Under the CRMN model, we develop general frameworks for solving both the decision version (i.e. for a given value p > 0, will a specified monotone property hold for the network induced by assigning the power value p to every node?) and the optimization version (i.e. find the minimum value p such that the specified monotone property holds for the network induced by assigning the power value p to every node) of the topology control problems. Efficient algorithms for specific monotone properties can be derived from these frameworks. For example, when the monotone property is network connectivity, our algorithms for the decision and optimization versions have running times of O(n ² log² n) and O(n ⁴ log² n), respectively. Our results represent a step towards the development of efficient and provably good distributed algorithms for topology control problems for MANETs.     

A Single-Chip CMOS Transceiver for UHF Mobile RFID Reader

This paper describes a single-antenna low-power single-chip radio frequency identification (RFID) reader for mobile phone applications. The reader integrates an RF transceiver, data converters, a digital baseband modem, an MPU, memory, and host interfaces. The direct conversion RF receiver architecture with the highly linear RF front-end circuit and DC offset cancellation circuit is used to give good immunity to the large transmitter leakage. It is suitable for a mobile phone reader with single-antenna architecture and low-power reader solution. The transmitter is implemented in the direct I/Q up-conversion architecture. The frequency synthesizer based on a fractional-N phase-locked-loop topology offering 900 MHz quadrature LO signals is also integrated with the RF transceiver. The reader is fabricated in a 0.18 mum CMOS technology, and its die size is 4.5 mm times 5.3 mm including electrostatic discharge I/O pads. The reader consumes a total current of 89 mA apart from the external power amplifier with 1.8 V supply voltage. It achieves an 8 dBm P1dB, an 18.5 dBm IIP3, and a maximum transmitter output power of 4 dBm.     

A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme

A 5-Gb/s/pin transceiver for DDR memory interface is proposed with a crosstalk suppression scheme. The proposed transceiver implements a staggered memory bus topology and a glitch canceller to suppress crosstalk-induced distortions in a memory channel. The transceiver is implemented using 0.18 $mu$m CMOS process and operates at 5 Gb/s. The results demonstrate widened eye diagram and lower bit error rate. The eye width and height of the proposed scheme increases 28.3% and 11.1% compared to the conventional memory transceiver, respectively. The peak-to-peak jitter of output data is 52.82 ps.