二氧化硅膜的减压淀积

我们在一个减压CVD反应器中,于700～750℃下用四乙氧基硅烷(TEOS)分解法,在硅衬底上淀积出了二氧化硅膜。淀积速率为200～300埃/分。在能装载100片的淀积区,淀积膜厚的均匀性优于1％。台阶覆盖性良好,缺陷密度很低,膜的应力是压应力而且很小。膜的折射率,红外质谱和密度与常压淀积的二氧化硅膜相同。系统中添加磷化物使淀积速率增加,膜厚的均匀性变坏。因此,这种反应并不能适用于淀积集成电路所用的掺磷二氧化硅膜;然而,对非掺杂的二氧化硅膜淀积工艺来说,这种反应似乎是一个很好的工艺过程。     

光化学汽相淀积技术在薄膜备制中的应用

介绍了光化学汽相淀积法的原理以及ＰＶＤ－１０００设备淀积薄膜的规律，特点等，并且给出了所淀积的ＳｉＯ２膜，Ｓｉ３Ｎ４膜和ＺｎＳ膜的基本特性。     

紫外光能量辅助CVD的反应机制

以二氧化硅，氮化硅薄膜为例论述了紫外光能量辅助化学汽相淀积的反应机制。二氧化硅薄膜的组成为纯ＳｉＯ２；氮化硅薄膜中含有氧元素，组成氮氧化硅。     

氧对化学汽相淀积氮化硅的影响

一、引言 不少文章已介绍了氮化硅膜有它的独特之处,许多性能优于二氧化硅膜,因而已在集成电路工艺中得到广泛的应用,而目前制备氮化硅膜有种种方法,较常用的有高温(850℃左右)下的化学汽相淀积(简称CVD)及低温(500℃以下)等离子化学汽相淀积(简称PCVD),前者又分“常压法”和“减压法”。本文主要讨论前者两种方法生长的氮化硅膜。     

半导体器件制造技术(八)

在半导体器件和集成电路中,需要应用多种金属薄膜和介质薄膜,金属膜用作器件内部电极的欧姆接触和延伸引出,集成电路各组元件之间的低电阻连接等。介质膜用作集成电路中多层布线的介质绝缘等。这些薄膜一般都采用真空淀积的方法制作。因为此淀积过程在真空中进行,可以得到器件所需要的高纯膜,也可避免器件表面被沾污。同时,淀积可以在低温下实现,因此,淀积过程不至引起器件内部结构的变化。一般地说,真空淀积可分成蒸发和溅射两种不同的方法。     

一种克服断铝的方法 磷硅玻璃回流

引言 硅栅MOS大规模集成电路中,采用了多晶硅铝的多层结构,其间常用低渴淀积SiO_2膜作绝缘层。但在多晶硅条和铝连线的交叉处及开孔处,由于铝条要爬越二氧化硅膜在多晶硅条“肩”部所形成的陡峭的台阶(图1),断铝常常会发生。为了克服“肩”部断铝问题,人们进行了广泛的研究。通常采用的方法有:进一步提高铝膜厚度的均匀性。对铝膜的腐蚀由原来的湿法改为干法,以及提高低温淀积二氧化硅膜的淀积温度和增加其厚度以降低台阶高度等方法。第一种方法和第三种方法的综合使用,在4K以下的MOS RAM电路中获得了较好的效果。铝膜的干法腐蚀由于条件的限制,尚未广泛使用。然而,     

LPCVD工艺—用20%、50%浓度的硅烷淀积多晶硅的工艺报告

很多年来,半导体工业上生产多晶硅、二氧化硅、氮化硅和无定型硅都是采用标准的常压冷壁化学汽相淀积技术.而在半导体器件工艺中,随着大规模集成电路的发展和超大规模集成电路的出现,对用常压CVD制备的半导体膜和绝缘膜的要求越来越高,原来的常压CVD技术淀积方法已经不能满足这种要求,人们开始研究新的技术来满足电路对工艺的要求.     

低温PECVD法制备半导体的复合钝化膜

本文主要是以ＳｉＨ４、Ｎ２Ｏ和Ｓｉ３Ｈ４、ＮＨ３、Ｎ２作为气体源，在平行板电容耦合式淀积设备上，采用等离子增强化学气相淀积（ＰＥＣＶＤ）法制备ＳｉＯ２－Ｓｉ３Ｎ４复合钝化膜。     

PCVD技术在InSb CID焦平面阵列的应用

本文系统描述了用ＰＣＶＤ（光化学汽相淀积）技术在ＩｎＳｂ衬底上沉积ＳｉＯｘＮｙ介质膜的工艺过程。对ＳｉＯｘＮｙ膜进行测试分析，并用它作介质膜，钝化膜，作出了性能较好的ＩｎＳｂ ＣＩＤ焦平面器件。     

DLTS技术研究富氮SiOxNy薄介质膜的电学特性

采用深能级瞬态谱技术（ＤＬＴＳ）,测试了等离子体增强化学汽相淀积（ＰＥＣＶＤ）法低温制备的富氮的ＳｉＯｘＮｙ栅介质膜的电学特性（界面态密度、俘获截面随禁带中能量的变化关系）,结果表明,采用合适的ＰＥＣＶＤ低温工艺淀积ＳｉＯｘＮｙ膜可以制备性质优良的栅介质膜。     

HDP介质淀积引起的等离子充电损伤机制研究

高密度等离子体化学气相淀积(HDP CVD),具有卓越的填孔能力和可靠的电学特性等诸多优点,因此它被广泛应用于超大规模集成电路制造工艺中.本文研究了金属层间介质(IMD)的HDP CVD过程对栅氧化膜的等离子充电损伤.研究表明在HDP淀积结束时的光电导效应使得IMD层(包括FSG和USG)在较短的时间内处于导电状态,较大电流由IMD层流经栅氧化膜,在栅氧化膜中产生缺陷,从而降低了栅氧化膜可靠性.通过对HDP CVD结束后反应腔内气体组分的调节,IMD层的光电导现象得到了一定程度的抑制,等离子充电损伤得到了改善.     

液态源化学气相淀积制备SiO_2薄膜的设备研制

采用液态有机硅源的等离子体增强化学气相淀积设备是通向深亚微米时代的桥梁。介绍研制的液态源化学气相淀积设备的工作原理、结构特点和工艺结果,制备的SiO2薄膜膜厚均匀性±2%,折射率1.452±0.014,生长速率40nm?min。     

Fabrication of submicron junctions-proximity rapid thermaldiffusion of phosphorus, boron, and arsenic

Various techniques used in fabrication of deep submicron junctions are reviewed with respect to their advantages and disadvantages in silicon very large scale integration (VLSI) circuits technology. Proximity rapid thermal diffusion is then presented as an alternative process which results in very shallow junctions with high dopant concentrations at the surface. The feasibility of Si doping with B, P, and As for both planar and 3-D structures such as trench capacitors used in high density DRAM memories is shown based on sheet resistance measurements, secondary ion mass spectroscopy and scanning electron micrographs. Retardation effect of arsenic diffusion similar to the well known inhibition of silicon or SiO₂ deposition in chemical vapor deposition (CVD) processes is identified and discussed     

VLSI互连线系统中的低介电常数材料与工艺研究

阐述了超大规模集成电路 ( VLSI)特征尺寸的减小及互连线层数增加引起的互连线电容增加的问题。具体总结了为提高 VLSI的速度而采用的低介电常数材料及其制备工艺 ,对在连线间形成空气间隙来降低线间电容的方法也进行了介绍。最后 ,展望了低介电常数材料在 VL SI互连线系统中的应用前景。     

Electrical properties for MOS LSI's fabricated using stacked Oxide SWAMI technology

The stacked oxide SWAMI (STOMI) process, in which the SWAMI process is improved by employing CVD oxide deposition on the first nitride film, has been developed. The stacked oxide plays an important role in process stability and controllability in fabricating VLSI devices. A large punchthrough voltage between diffused layers, a small sidewall capacitance for the n⁺-p junction, and a small narrow-channel effect for silicon gate n-channel MOSFET's have been achieved by the STOMI process. A 256-kbit dynamic RAM with high performance has also been fabricated successfully. The STOMI process is particularly advantageous as an isolation technique applicable to advanced devices with small (< 1 µm) geometries.     

Characterization and reliability of dual high-k gate dielectric stack (poly-Si-HfO/sub 2/-SiO/sub 2/) prepared by in situ RTCVD process for system-on-chip applications

We investigate for the first time the possibility of integrating chemical vapor deposition (CVD) HfO/sub 2/ into the multiple gate dielectric system-on-a-chip (SoC) process in the range of 6-7 nm, which supports higher voltage (2.5-5 V operation/tolerance). Results show that CVD HfO/sub 2/-SiO/sub 2/ stacked gate dielectric (EOT =6.2 nm) exhibits lower leakage current than that of SiO/sub 2/ (EOT =5.7 nm) by a factor of /spl sim/10/sup 2/, with comparable interface quality (D/sub it//spl sim/1/spl times/10/sup 10/ cm/sup -2/eV/sup -1/). The presence of negative fixed charge is observed in the HfO/sub 2/-SiO/sub 2/ gate stack. In addition, the addition of HfO/sub 2/ on SiO/sub 2/ does not alter the dominant conduction mechanism of Fowler-Nordheim tunneling in the HfO/sub 2/-SiO/sub 2/ gate stack. Furthermore, the HfO/sub 2/-SiO/sub 2/ gate stack shows longer time to breakdown T/sub BD/ than SiO/sub 2/ under constant voltage stress. These results suggest that it may be feasible to use such a gate stack for higher voltage operation in SoC, provided other key requirements such as V/sub t/ stability (charge trapping under stress) can be met and the negative fixed charge eliminated.     

Theoretical and experimental investigation of Si nanocrystal memory device with HfO/sub 2/ high-k tunneling dielectric

In this paper, silicon (Si) nanocrystal memory using chemical vapor deposition (CVD) HfO/sub 2/ high-k dielectrics to replace the traditional SiO/sub 2/ tunneling/control dielectrics has been fabricated and characterized for the first time. The advantages of this approach for improved nanocrystal memory operation have also been studied theoretically. Results show that due to its unique band asymmetry in programming and retention mode, the use of high-k dielectric on Si offers lower electron barrier height at dielectric/Si interface and larger physical thickness, resulting in a much higher J/sub g,programming//J/sub g,retention/ ratio than that in SiO/sub 2/ and therefore faster programming and longer retention. The fabricated device with CVD HfO/sub 2/ shows excellent programming efficiency and data-retention characteristics, thanks to the combination of a lower electron barrier height and a larger physical thickness of HfO/sub 2/ as compared with SiO/sub 2/ of the same electrical oxide thickness (EOT). It also shows clear single-electron charging effect at room temperature and superior data endurance up to 10/sup 6/ write/erase cycles.     

利用ISSG退火技术实现沉积二氧化硅薄膜平坦化

利用现场水汽生成(in-situ steam generation,ISSG)退火这种新型的低压快速氧化热退火技术,在对沉积二氧化硅薄膜热退火的同时进行补偿氧化生长,最终实现了沉积二氧化硅薄膜的平坦化.实验数据表明,ISSG退火补偿生长后整个晶圆表面的薄膜厚度波动(最大值与最小值之差)从0.76nm降到了0.16nm,49点厚度值的标准偏差从0.25nm降到了0.04nm.同时,薄膜的隧穿场强增加到4.3MV/cm,硅氧界面与传统的氧气快速退火工艺相比更为良好.实验结果为二氧化硅薄膜平坦化提供了新的思路,对实际生产具有重要意义.     

Advantages of Thermal Nitride and Nitroxide Gate Films in VLSI Process

Thin gate SiO/sub 2/ films thinner than 200 /spl Aring/ often deteriorate throughout developmentaf VLSI processes, including refractory metal or silicide gates and ion- or plasma-assisted processes. Thermal nitridation of such SiO/sub 2/ films improves the MOS characteristics by producing surface protective layers against impurity penetration and by producing good interfacial characteristics. This fact indicates that a thermally grown silicon nitride film on a silicon substrate is the most promising candidate for a very-thin gate insulator. Experimental data show significant benefits from the nitride film for future VLSI devices.     

PECVD SiO2 薄膜内应力研究

研究了等离子体增强化学气相淀积(PWCVD)法生长SiO2薄膜的内应力.借助XP-2型台阶仪和椭偏仪测量计算了SiO2薄膜的内应力,通过改变薄膜淀积时的工艺条件,如淀积温度、气体流量、反应功率、腔体压力等,分析了这些参数对SiO2薄膜内应力的影响.同时讨论了内应力产生的原因以及随工艺条件变化的机理,对工艺条件的优化有一定参考价值.