Improving low-temperature APCVD SiO2 passivation byrapid thermal annealing for Si devices

The quality of low-temperature (≈400°C) atmospheric pressure chemical vapor deposited (APCVD) silicon dioxide (SiO₂ ) films has been improved by a short time rapid thermal annealing (RTA) step. The RTA step followed by a low temperature (400°C) forming gas anneal (FGA) results in a well-passivated Si-SiO₂ interface, comparable to thermally grown conventional oxides. Efficient and stable surface passivation is obtained by this technique on virgin silicon as well as on photovoltaic devices with diffused (n⁺p) emitter surface while maintaining a very low thermal budget. Device parameters are improved by this APCVD/RTA/FGA passivation process     

Formation of 0.05-μm p+-n and n+-pjunctions by very low (<500 eV) ion implantation

The current-voltage (I-V) characteristics of ultrashallow p⁺ -n and n⁺-p diodes, obtained using very-low-energy (<500-eV) implantation of B and As, are presented. the p⁺-n junctions were formed by implanting B⁺ ions into n-type Si (100) at 200 eV and at a dose of 6×10¹⁴ cm^-2, and n⁺-p junctions were obtained by implanting As⁺ ions into p-type (100) Si at 500 eV and at a dose 4×10¹² cm^-2. A rapid thermal annealing (RTA) of 800°C/10 s was performed before I-V measurements. Using secondary ion mass spectrometry (SIMS) on samples in-situ capped with a 20-nm ²⁸Si isotopic layer grown by a low-energy (40 eV) ion-beam deposition (IBD) technique, the depth profiles of these junctions were estimated to be 40 and 20 nm for p⁺-n and n⁺-p junctions, respectively. These are the shallowest junctions reported in the literature. The results show that these diodes exhibit excellent I-V characteristics, with ideality factor of 1.1 and a reverse bias leakage current at -6 V of 8×10^-12 and 2×10^-11 A for p⁺-n and n⁺-p diodes, respectively, using a junction area of 1.96×10^-3 cm²     

Electrical characterization of ultra-shallow junctions formed bydiffusion from a CoSi2 layer

Ultra-shallow p⁺/n and n⁺/p junctions were fabricated using a Silicide-As-Diffusion-Source (SADS) process and a low thermal budget (800-900°C). A thin layer (50 nm) of CoSi₂ was implanted with As or with BF₂ and subsequently annealed at different temperatures and times to form two ultra-shallow junctions with a distance between the silicide/silicon interface and the junction of 14 and 20 nm, respectively. These diodes were investigated by I-V and C-V measurements in the range of temperature between 80 and 500 K. The reverse leakage currents for the SADS diodes were as low as 9×10 ^-10 A/cm² for p⁺/n and 2.7×10^-9 A/cm² for n⁺/p, respectively. The temperature dependence of the reverse current in the p ⁺/n diode is characterized by a unique activation energy (1.1 eV) over all the investigated range, while in the n⁺/p diode an activation energy of about 0.42 eV is obtained at 330 K. The analysis of the forward characteristic of the diodes indicate that the p⁺ /n junctions have an ideal behavior, while the n⁺/p junctions have an ideality factor greater than one for all the temperature range of the measurements. TEM delineation results confirm that, in the case of As diffusion from CoSi₂, the junction depth is not uniform and in some regions a Schottky diode is observed in parallel to the n⁺/p junction. Finally, from the C-V measurements, an increase of the diodes area of about a factor two is measured, and it is associated with the silicide/silicon interface roughness     

Low-resistance bandgap-engineeredW/Si1-xGex/Si contacts

Bandgap-engineered W/Si_1-xGe_x/Si junctions (p⁺ and n⁺) with ultra-low contact resistivity and low leakage have been fabricated and characterized. The junctions are formed via outdiffusion from a selectively deposited Si_0.7Ge _0.3 layer which is implanted and annealed using RTA. The Si _1-xGe_x layer can then be selectively thinned using NH₄OH/H₂O₂/H₂O at 75°C with little change in characteristics or left as-deposited. Leakage currents were better than 1.6×10^-9 A/cm² (areal), 7.45×10^-12 A/cm (peripheral) for p⁺/n and 3.5×10^-10 A/cm² (peripheral) for n⁺/p. W contacts were formed using selective LPCVD on Si_1-xGe_x. A specific contact resistivity of better than 3.2×10^-8 Ω cm² for p ⁺/n and 2.2×10^-8 Ω cm² for n⁺/p is demonstrated-an order of magnitude n⁺ better than current TiSi₂ technology. W/Si_1-xGe _x/Si junctions show great potential for ULSI applications     

Comments on "The saturated photovoltage of a p-n junction"

In a recent paper, Gray has shown that the open-circuit photovoltage ratio of p⁺n to n⁺p junctions is given by the mobility ratio. We show here that this is an overestimation, the ratio being much smaller if an exact analysis is used.     

Shallow p+n junctions formed by using a two-stepannealing scheme with low thermal budget

Shallow p⁺n junctions have been formed by directly implanting BF₂ dopant into the Si substrate and then treating the samples by an annealing scheme with low thermal budget. A junction leakage smaller than 10 nA/cm² can be achieved by an annealing scheme that employs low-temperature long-time furnace annealing (FA) at 600°C for 3 h followed by medium-temperature rapid thermal annealing (RTA) at 800°C for 30 s. No considerable dopant diffusion is observed by using this low-thermal-budget annealing process. In addition, a moderate low-temperature annealing time of about 2-3 h should be employed to optimize the shallow p⁺n junction formed by this scheme. However, the annealing process that employs medium-temperature RTA followed by low-temperature FA treatment produces worse junctions than the annealing scheme that employs long-time FA at 600°C followed by RTA at 800°C     

Ultra-shallow junction formation using silicide as a diffusionsource and low thermal budget

Ultra-shallow p⁺/n and n⁺/p junctions were fabricated using SADS (silicide-as-diffusion-source) and ITS (ion-implantation-through-silicide processing) of 45-nm CoSi₂ films (3.5 Ω/□) using a low thermal budget. The best junctions of either type were made by moderate 10-s RTA (rapid thermal annealing) at 800°C, where the total junction depth, counting the silicide thickness, is believed to be under 60 nm. Diffusion-limited current predominated down to 50°C in junctions made under these conditions. The initial implantation energy had only a minor effect on the junction leakage, where shallower implants required slightly higher temperatures to form low leakage diodes, resulting in diodes which were somewhat more susceptible to shorting during silicide agglomeration at high temperatures. The ITS scheme, where dopant is implanted slightly beyond the silicide, gives an equally low leakage current. Nevertheless, the ITS scheme gives deeper junctions than the SADS process, and it is difficult to control the position of the ITS junction due to silicide/silicon interface fluctuations     

Optimization of the germanium preamorphization conditions forshallow-junction formation

Shallow p⁺-n and n⁺-p junctions were formed in germanium preamorphized Si substrates. Germanium implantation was carried out over the energy range of 50-125 keV and at doses from 3×10¹⁴ to 1×10¹⁵ cm^-2. p ⁺-n junctions were formed by 10-keV boron implantation at a dose of 1×10¹⁵ cm^-2. Arsenic was implanted at 50 keV at a dose of 5×10¹⁵ cm^-2 to form the n⁺-p junctions. Rapid thermal annealing was used for dopant activation and damage removal. Ge, B, and As distribution profiles were measured by secondary ion mass spectroscopy. Rutherford backscattering spectrometry was used to study the dependence of the amorphous layer formation on the energy and dose of germanium ion implantation. Cross-sectional transmission electron microscopy was used to study the residual defects formed due to preamorphization. Complete elimination of the residual end-of-range damage was achieved in samples preamorphized by 50-keV/1×10¹⁵ cm^-2 germanium implantation. Areal and peripheral leakage current densities of the junctions were studied as a function of germanium implantation parameters. The results show that high-quality p⁺-n and n⁺-p junctions can be formed in germanium preamorphized substrates if the preamorphization conditions are optimized     

Mo- and Ti-silicided low-resistance shallow junctions formed using the ion implantation through metal technique

Mo-and Ti-silicided junctions were formed using the ITM technique, which consists of ion implantation through metal (ITM) to induce metal-Si interface mixing and subsequent thermal annealing. Double ion implantation, using nondopant ions (Si or Ar) implantation for the metal-Si interface mixing and dopant ion (As or B) implantation for doping, has resulted in ultrashallow ( ≤ 0.1-µm) p⁺-n or n⁺-p junctions with ∼30-Ω sheet resistance for Mo-silicided junctions and ∼5.5-Ω sheet resistance for Ti-silicided junctions. The leakage current levels for the Mo-silicided n⁺-p junctions (0.1-µm junction depth) and the Mo-silicided p⁺-n junction (0.16-µm junction depth) are comparable to that for unsilicided n⁺-p junction with greater junction depth ( ∼0.25 µm).     

Formation of cobalt silicided shallow junction using implantinto/through silicide technology and low temperature furnace annealing

This work investigates the shallow CoSi₂ contacted junctions formed by BF₂⁺ and As⁺ implantation, respectively, into/through cobalt silicide followed by low temperature furnace annealing. For p⁺n junctions fabricated by 20 keV BF₂⁺ implantation to a dose of 5×10¹⁵ cm^-2, diodes with a leakage current density less than 2 nA/cm² at 5 V reverse bias can be achieved by a 700°C/60 min annealing. This diode has a junction depth less than 0.08 μm measured from the original silicon surface. For n⁺p junctions fabricated by 40 keV As⁺ implantation to a dose of 5×10¹⁵ cm^-2, diodes with a leakage current density less than 5 nA/cm² at 5 V reverse bias can be achieved by a 700°C/90 min annealing; the junction depth is about 0.1 μm measured from the original silicon surface. Since the As⁺ implanted silicide film exhibited degraded characteristics, an additional fluorine implantation was conducted to improve the stability of the thin silicide film. The fluorine implantation can improve the silicide/silicon interface morphology, but it also introduces extra defects. Thus, one should determine a tradeoff between junction characteristics, silicide film resistivity, and annealing temperature     

Subquarter-micrometer gate-length p-channel and n-channel MOSFETswith extremely shallow source-drain junctions

The fabrication of p-channel and n-channel MOSFETs with sub-quarter-micrometer n⁺ polysilicon gates, have been fabricated using extremely shallow source-drain (S-D) junctions, is reported p⁺-n junctions as shallow as 80 nm have been fabricated using preamorphization low-energy BF₂ ion implantation and rapid thermal annealing, and 80-nm n⁺-p junctions have been fabricated using low-energy arsenic ion implantation and rapid thermal annealing. n-channel MOSFETs with 80-mm S-D junctions and 0.16-μm gate lengths have been fabricated, and a maximum transconductance of 400 mS/mm has been obtained. 51-stage n-channel enhancement-mode/enhancement-mode (E/E) ring oscillators and p-channel E/E ring oscillators with extremely shallow S-D junctions have also been obtained     

Shallow-junction diode formation by implantation of arsenic andboron through titanium-silicide films and rapid thermal annealing

The performance of diodes fabricated on n-type and p-type Si substrates by implanting As or B through a low-resistivity titanium-silicide layer is discussed. The effects of varying the implant dose, energy, and postimplant thermal treatment were investigated. After implantation, a rapid thermal anneal was found to remove most of the implant damage and activate the dopants, which resulted in n⁺-p and p⁺-n junctions under a low-resistivity silicide layer. The n⁺-p junctions were as shallow as 1000 Å with reverse leakage currents as low as 5.5 μA/cm². A conventional furnace anneal resulted in a further reduction of this leakage. Shallow p⁺-n junctions could not be formed with boron implantation because of the large projected range of boron ions at the lowest available energy. Ti silicide films thinner than 600 Å exhibited a sharp rise in sheet resistivity after a furnace anneal, whereas thicker films exhibited more stable behavior. This is attributed to coalescence of the films. High-temperature furnace annealing diffused some of the dopants into the silicide film, reducing the surface concentrations at the TiSi₂ -Si interface     

Nonalloyed ohmic contacts to n-type GaAs by pulsed ruby laser diffused tin from tin-silica film

Nonalloyed ohmic contacts were formed on n⁺diffused layers on GaAs. The n⁺layers were formed on semi-insulating substrates by depositing a layer of tin-silica film and irradiating by ruby laser alone without thermal diffusion. Vacuum-evaporated AuGe-Ni contacts display low specific contact resistance ≃1.8 × 10^-6Ω.cm², without alloying.     

Shallow-junction formation on silicon by rapid thermal diffusion ofimpurities from a spin-on source

Rapid thermal diffusion (RTD) of P and/or B into silicon wafer from spin-on sources using tungsten halogen lamps was successfully used to fabricate very shallow n⁺-p and/or p⁺-n junctions. RTD was performed in the temperature range of 600-1080°C for 5-60 s, and the heating rates were varied in the range 10-83°C/s. Effects of the two-step RTD, high temperature for several seconds, and subsequent low temperature for 60 s, were also examined. The RTD of P was carried out from P-doped oxide films and that of B was carried out from polymeric boron-doped films. Using RTD one can obtain a very shallow junction, thinner than 20 nm in depth. The impurity diffusion by RTD is similar to conventional furnace processing. However, the RTD of P and/for B was enhanced with the heating rate, especially at 83°C/s. This was assumed to be caused by the stress field induced in the heating stage. The junction depth, I-V characteristics, spectral response, and cell parameters of fabricated photodiodes are presented     

Effect of ion energy on hydrogen diffusion in n- and p-GaAs

The ion energy during electron cyclotron resonance (ECR) plasma hydrogenation is found to have a strong effect on both the effective diffusivity and solubility of hydrogen in n⁺ and p⁺ GaAs. For fixed plasma exposure conditions (30 min, 250°C) the diffusion depths for -150 V acceleration voltage are ~50 and ~100% larger, respectively, in p⁺- and n⁺-GaAs compared to 0 V acceleration voltage. The smaller incorporation depths at lower ion energy coincide with much larger peak hydrogen concentrations and higher apparent thermal stability of passivated dopants     

Impurity profile determination and DC modeling of the JIGFET

The junction and insulated gate FET (JIGFET) is a novel type of JFET which is formed by implantation of a deep channel between source and drain through a MOST gate. For high voltages on the gate an inversion layer is created underneath the oxide. This inversion layer is laterally connected to the substrate. In this way a new channel control mechanism for FET's is achieved in which the inversion layer is used as a substitute for a p⁺-n- or an n⁺-p-junction. This results in a very high bulk transconductance, which is of considerable importance in many applications. In this paper the n-channel JIGFET's with implanted channels of 2.4 × 10¹²p⁺ions/cm²at 100 keV and 3.4 × 10¹²p+ ions/cm²at 160 keV are investigated. The implantation profiles are calculated from pulsedC-Vmeasurements. From these data the dc characteristics are calculated with the abrupt space charge layer edge (ASCE) approximation and compared with the experiments for both high and low drain voltages.     

Junction depth versus sheet resistivity in BF2+-implanted rapid-thermal-annealed silicon

Conditions to achieve shallow p+-junctions with low sheet resistance by using ion implantation and rapid thermal annealing (RTA), are presented. This work shows that (junction depth) × (sheet resistivity)rho_{s}X_{j}has a smaller value with increasing implant dose and anneal temperature (boron solubility), and decreasing implant energy. However, the value is saturated for higher doses than 10¹⁶Xjcm², where Xjis junction depth in micrometers, and anneal temperature should be lower than 1100°C, because of considerable boron diffusion even in 10-s RTA.rho_{s}X_{j} = 18Ω.µm is achieved by BF2+ implantation with 5 × 10¹⁵-cm^-2dose at 30 keV and 1000°C RTA. The possibility of further improvement inrho_{s}X_{j}value is discussed.     

Rapid thermal annealing effects on Si p+-n junctionsfabricated by low-energy FIB Ga+ implantation

Effects of rapid thermal annealing (RTA) on sub-100 nm p⁺ -n Si junctions fabricated using 10 kV FIB Ga⁺ implantation at doses ranging from 10¹³ to 10¹⁵ cm ^-2 are reported. Annealing temperature and time were varied from 550 to 700°C and 30 to 120 s. It was observed that a maximum in the active carrier concentration is achieved at the critical annealing temperature of 600°C. Temperatures above and below the critical temperature were followed by a decrease in the active concentration, leading to a `reverse' annealing effect     

0.2-μm p+-n junction characteristics dependent onimplantation and annealing processes

Junction depth, sheet resistance, dopant activation, and diode leakage current characteristics were measured to find out the optimal processing conditions for the formation of 0.2-μm p⁺-n junctions. Among the 2×10¹⁵ cm^-2 BF₂ implanted crystalline, As or Ge preamorphized silicon, the crystalline and Ge preamorphized samples exhibit excellent characteristics. The thermal cycle of furnace anneal (FA) followed by rapid thermal anneal (RTA) shows better characteristics than furnace anneal, rapid thermal anneal, or rapid thermal anneal prior to furnace anneal     

Process limitation and device design tradeoffs of self-aligned TiSi2 junction formation in submicrometer CMOS devices

Submicrometer CMOS transistors require shallow junctions to minimize punchthrough and short-channel effects. Salicide technology is a very attractive metallization scheme to solve many CMOS scaling problems. However, to achieve a shallow junction with a salicide structure requires careful optimization for device design tradeoffs. Several proposed techniques to form shallow titanium silicide junctions are critically examined. Boron, BF₂, arsenic, and phosphorus dopants were used to study the process parameters for low-leakage TiSi ₂ p⁺/n and n⁺/p junctions in submicrometer CMOS applications. It is concluded that the dopant drive-out (DDO) from the TiSi₂ layer to form a shallow junction scheme is not an efficient method for titanium salicide structure; poor device performance and unacceptably leaky junctions are obtained by this scheme. The conventional post junction salicide (PJS) scheme can produce shallow n⁺/p and p⁺/n junctions with junction depths of 0.12 to 0.20 μm below the TiSi₂. Deep submicrometer CMOS devices with channel length of 0.40 to 0.45 μm can be fabricated with such junctions