Statistical extraction and modeling of inductance considering spatial correlation

In this paper, we present a novel method for statistical inductance extraction and modeling for interconnects considering process variations. The new method, called statHenry, is based on the collocation-based spectral stochastic method where orthogonal polynomials are used to represent the statistical processes. The coefficients of the partial inductance orthogonal polynomial are computed via the collocation method where a fast multi-dimensional Gaussian quadrature method is applied with sparse grids. To further improve the efficiency of the proposed method, a random variable reduction scheme is used. Given the interconnect wire variation parameters, the resulting method can derive the parameterized closed form of the inductance value. We show that both partial and loop inductance variations can be significant given the width and height variations. This new approach can work with any existing inductance extraction tool to extract the variational partial and loop inductance or impedance. Experimental results show that our method is orders of magnitude faster than the Monte Carlo method for several practical interconnect structures.     

非并网自备电源电压跌落检测与评估的研究

采用非序贯蒙特卡罗法计算和评估非并网自备电源故障工作状态下的电压跌落。通过建立概率模型、样本随机抽样,样本统计量数据评估来计算和评估自备电源系统中的电压跌落。触发信号与故障信号的下降沿时刻差值Δt值集中于(1.675±0.1)ms范围内,节点1和节点3发生故障时电流通过时间较短,电压跌落幅值大概率在0.6 p.u之上。非序贯蒙特卡罗法仿真分析的幅值、电压跌落概率与实测统计法相近,具有良好的稳定性和准确性。     

Statistical simulation methodology for sub- 100nm memory design

A new statistical simulation methodology under process variations in deep sub-micron technology is described. By dividing the overall memory system into sub-blocks and running Monte Carlo simulations locally, significant reduction in the statistical simulation time is achieved. A novel methodology to combine the simulation results and accurately predict the read access failure of the overall system is also presented. This allows allocation of design margins and setting of design guidelines for each sub-block in the early design stage.     

Numerical Estimation of Yield in Sub-100-nm SRAM Design Using Monte Carlo Simulation

This paper describes a method to numerically calculate the design margin and to estimate the yield associated with the read access failure for sub-100-nm SRAM. Process variations at sub-100 nm not only affect SRAM cells but also periphery circuits, such as the sense amplifier (SA) and the tracking scheme. Simulation that incorporates both SRAM cells and surrounding circuits is either accurate but computationally expensive (comprehensive Monte Carlo simulation), or overly simple (fixed corner design) and unable to capture crucial statistical variation concern, dominant in sub-100-nm designs. By mathematically combining the separate Monte Carlo simulation results of SRAM cells and each peripheral block, we show that the distribution of the SA input voltage can be estimated accurately in a case where fixed corner simulation underestimates by 19%. We also present the yield equation by combining the SA input voltage and the SA offset distribution, which can be used to choose the design point. In addition, yield sensitivities are derived from the yield data to make sure that the yield has good dependence to design variables.      

Stochastic logical effort as a variation aware delay model to estimate timing yield

Considerable effort has been expended in the EDA community during the past decade in trying to cope with the so-called statistical timing problem. In this paper, we not only present a fast and approximate gate delay model called stochastic logical effort (SLE) to capture the effect of statistical parameter variations on the delay but also combine this model with a previously proposed transistor level smart Monte Carlo method to construct ISLE timing yield estimator. The results demonstrate that our approximate SLE model can capture the delay variations and ISLE achieves the same accuracy as the standard Monte Carlo estimator with a cost reduction of about 180× on the average for ISCAS’85 benchmark circuits and in the existence of both inter- and intra-die variations.     

Fast and accurate statistical characterization of standard cell libraries

With devices entering the nanometer scale process-induced variations, intrinsic variations and reliability issues impose new challenges for the electronic design automation industry. Design automation tools must keep the pace of technology and keep predicting accurately and efficiently the high-level design metrics such as delay and power. Although it is the most time consuming, Monte Carlo is still the simplest and most employed technique for simulating the impact of process variability at circuit level. This work addresses the problem of efficient alternatives for Monte Carlo for modeling circuit characteristics under statistical variability. This work employs the error propagation technique and Response Surface Methodology for substituting Monte Carlo simulations for library characterization.The techniques are validated and compared using a production level cell library using a state-of-the-art 32 nm technology node and statistical device compact model. They require electrical simulation effort linear to the number of devices, thus from one to two orders of magnitude speed-up is obtained compared to Monte Carlo analysis with the error on standard deviation and mean being smaller than 2% for the Response Surface Methodology, as compared to errors of 7% when using linear sensitivity analysis.     

An Efficient Simulation Environment and Simulation Techniques for Bluetooth Device Design

Validation of an System-on-Chip (SoC) design with networking capability needs global simulation of the whole system including the network as well as the SoC design itself. Especially, it is needed to validate the interoperability of SoCs from different vendors. In this paper, we propose a simulation environment and simulation techniques for efficient validation of such SoC designs and apply them to networked Bluetooth SoC designs. The environment enables two types of simulation. One is modular enough to include the simulation of other vendors' Bluetooth devices and the other is optimized to achieve fast simulation in developing in-house Bluetooth devices. Especially, the former is scalable in that it keeps the constant simulation runtime despite the increase of the number of Bluetooth devices. Since multiple simulators are involved, the global simulation is still slow. Thus, the simulation efforts need to be minimized to shorten the design cycle. We present two simulation techniques, a concept called grouped message for reduction in simulation runtime and a system debug scenario called fix–modify–restart for reduction in the number of simulation runs. The former is to reduce inter-process communication overhead between simulators in the global simulation. The latter is to reduce repeated simulation runs in the conventional design cycle. Experimental results show the scalability of the presented simulation environment, reduction in simulation efforts by two simulation techniques.     

Efficient parametric yield optimization of VLSI circuit by uniform design sampling method

A novel yield estimation and optimization method is proposed based on uniform design sampling (UDS) method, which is one kind of quasi-Monte Carlo method. Compared with primitive statistical methods based on Monte Carlo sampling method, this new method needs only few circuit simulations to have a valuable estimation and is immune to the number of statistical variables. Furthermore, owing to simple algorithm to generate samples, the UDS method adds no computational complexity. A comparison of UDS method with the popular Monte Carlo based method–Latin hypercube sampling method is made in this paper to show the efficiency of the new method. Finally, several examples are presented to demonstrate the advantages of the proposed method over those available.     

Analytical modeling of CMOS circuit delay distribution due to concurrent variations in multiple processes

A technique for modeling the effect of variations in multiple process parameters on circuit delay performance is proposed. The variation in saturation current I_on at the device level, and the variation in rising/falling edge stage delay for the NAND gate at the circuit level, are taken as performance metrics. The delay of a two-input NAND gate with 65 nm gate length transistors is extensively characterized by mixed-mode simulations, which is then used as a library element. Appropriate templates for the NAND gate library are incorporated in a general purpose circuit simulator SEQUEL. A 4-bit × 4-bit Wallace tree multiplier circuit, consisting of two-input NAND gates is used to demonstrate the proposed methodology. The variation in the multiplier delay is characterized, by generating delay distributions, using an extensive Monte Carlo analysis. The use of linear interpolation and linear superposition is evaluated to study simultaneous variations in two and more process parameters. An analytical model for gate delays, in terms of device drive current I_on, is proposed, which can be used to extend this methodology for a generic technology library with a variety of library elements. The model is validated against Monte Carlo simulations and is shown to have a typical error of less than 0.1% for simultaneous variations in multiple process parameters. The proposed methodology can be used for statistical timing analysis and circuit simulation at the gate level.     

Yield analysis for self-repairable MEMS devices

In this paper, yield analysis for a self-repairable MEMS (SRMEMS) accelerometer design is proposed. The accelerometer consists of (n  +  m) identical modules: n of them serve as the main device, while the remaining m modules act as the redundancy. The yield model for MEMS redundancy repair is developed by statistical analysis. Based upon the yield model, the yield increase after redundancy repair for different m and n numbers is analyzed. ANSYS Monte Carlo simulation is used to estimate the yield of BISR/non-BISR MEMS devices with random point-stiction defects. The simulation results are in good agreement with the theoretical prediction based on our yield model. The simulation results also show that the SRMEMS leads to effective yield increase compared to non-BISRS design, especially for a moderate initial yield.     

Performance of M-MRC receivers over TWDP fading channels

An expression of characteristic function of signal-to-noise ratio (SNR) for two waves with diffused power (TWDP) fading channel is derived. Using this expression, the expression for the probability density function (PDF) of the output SNR of maximal ratio combining (MRC) receiver is obtained. Expressions for the performance matrix of MRC receiver over TWDP fading channels are also deduced. PDF based approach is followed to derive expressions of outage probability and average symbol error rate for coherent and non-coherent m-ary modulation schemes. Effects of the number of branches M and the fading parameters K and Δ on the system performance are studied. The results obtained are verified by Monte Carlo simulation.     

A recursive variance-reduction algorithm for estimatingcommunication-network reliability

In evaluating the capacity of a communication network architecture to resist possible faults of some of its components, several reliability metrics are used. This paper considers the 𝒦-terminal unreliability measure. The exact evaluation of this parameter is, in general, very costly since it is in the NP-hard family. An alternative to exact evaluation is to estimate it using Monte Carlo simulation. For highly reliable networks, the crude Monte Carlo technique is prohibitively expensive; thus variance reduction techniques must be used. We propose a recursive variance-reduction Monte-Carlo scheme (RVR-MC) specifically designed for this problem, RVR-MC is recursive, changing the original problem into the unreliability evaluation problem for smaller networks. When all resulting systems are either up or down independently of components state, the process terminates. Simulation results are given for a well-known test topology. The speedups obtained by RVR-MC with respect to crude Monte Carlo are calculated for various values of component unreliability. These results are compared to previously published results for five other methods (bounds, sequential construction, dagger sampling, failure sets, and merge process) showing the value of RVR-MC     

Modified Latin Hypercube Sampling Monte Carlo (MLHSMC) Estimation for Average Quality Index

The Monte Carlo (MC) method exhibits generality and insensitivity to the number of stochastic variables, but it is expensive for accurate Average Quality Index (AQI) or Parametric Yield estimation of MOS VLSI circuits or discrete component circuits. In this paper a variant of the Latin Hypercube Sampling MC method is presented which is an efficient variance reduction technique in MC estimation. Theoretical and practical aspects of its statistical properties are also given. Finally, a numerical and a CMOS clock driver circuit examples are given. Encouraging results and good agreement between theory and simulation results have thus far been obtained.     

Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random On-Chip Data Traffic

This paper presents a statistical approach to synthesize an energy conscious the optimal bus width and the number of buses. The slack is exploited to maximize bus sharing and to reduce energy consumption by simultaneously scaling the voltage during the synthesis of on-chip communication bus. An assumption for bus synthesis is that a system has been partitioned and mapped onto the appropriate modules of a system-on-chip (SoC). Because of the diversity of applications to be run on a single SoC, there exists a variability of data size to be transferred among the on-chip communicating modules. This variability of data size is modeled as a random variable with a known distribution function. The resulting synthesis problem is relaxed to a convex quadratic optimization problem and solved efficiently using a convex optimization tool. The effectiveness of our approach is demonstrated by applying optimization to an automatically generated benchmark and a real-life application. By scaling voltage of a bus, a tradeoff between communication bus cost (bus width and the number of buses) and energy reduction is explored. The experimental results show the significant reduction in communication energy with scaling voltage. However, it offers a limitation to minimize the communication bus cost, if the voltage is scaled beyond its minimum limit. Furthermore, we also estimate the distribution of voltage under a random data size using an analytical method and the Monte Carlo simulation. The results show that the analytically estimated statistical parameters of voltage are close to the simulated results.     

Performance Evaluation of Underlay Cognitive Multi-hop Networks Over Nakagami-m Fading Channels

We derive a closed-form bit error rate (BER) formula for underlay cognitive N-hop networks operated over Nakagami-m fading channels where N is the arbitrary integer. This formula is corroborated by Monte Carlo simulations and useful for evaluating the network performance under different parameters such as modulation level, path-loss, maximum transmit power, tolerable interference power level, fading model, and the number of hops. Numerical results illustrate that underlay cognitive multi-hop networks suffer a high error floor and the BER performance not only depends on the number of hops but also the network topology. For the linear network model, the higher the number of hops, the better the network performance.     

Symbolic Statistical Analysis of SNR Variation for Delta–Sigma Modulators

Traditional methods for statistical analysis of delta-sigma modulators are based on Monte Carlo analysis to iteratively change the design parameters and evaluate the histogram of signal-to-noise ratio (SNR). But Monte Carlo analysis is time-consuming, especially when a number of candidate designs need to be considered. In this brief, a systematic symbolic formulation of statistical SNR variation is made so that variations of capacitors are directly translated to SNR variation. In addition, the symbolic formulation is derived from a generic modulator topology, so that the derived symbolic formulation is applicable to any topology that is covered by the generic topology. Experiments have shown the symbolic formulation can provide fast and reasonably accurate estimation of statistical SNR variation, especially for high-order modulators.     

Energy efficient collaborative communications in AWGN and Rayleigh fading channel in wireless sensor networks

Collaborative communication produces high power gain and significantly reduces bit error rate (BER) if both frequency and phase synchronization are achieved. In this paper, a novel collaborative communication system with imperfect phase and frequency synchronization that includes the influence of noise and fading is proposed, modeled, theoretically analyzed, and simulated. Mathematical expressions are derived for the received power as a function of number of collaborative nodes and BER as a function of signal to noise ratio (E_b ∕ N₀). To analyze the energy efficiency of our proposed collaborative communication system, energy consumption of the system is modeled, simulated, and analyzed by considering the parameters of the off‐the‐shelf products. Analytical and simulation results showed that the proposed system produces significant power gain and reduction in BER in the presence of phase errors, frequency errors, additive white Gaussian noise, and Rayleigh fading. A detailed theoretical analysis and Monte Carlo simulation revealed that the proposed collaborative communication system is an energy efficient communication system that can be implemented in sensor networks, as approximately N (number of collaborative nodes) times less total transmitted power is required than for the single input single output communication for a specifies transmission range. Copyright © 2012 John Wiley & Sons, Ltd.     

Process variation-aware performance analysis of asynchronous circuits

Current technology trends have led to the growing impact of process variations on performance of asynchronous circuits. As it is imperative to model process parameter variations for sub-100nm technologies to produce a more real performance metric, it is equally important to consider the correlation of these variations to increase the accuracy of the performance computation. In this paper, we present an efficient method for performance evaluation of asynchronous circuits considering inter- and intra-die process variation. The proposed method includes both statistical static timing analysis (SSTA) and statistical Timed Petri-Net based simulation. Template-based asynchronous circuit has been modeled using Variant-Timed Petri-Net. Based on this model, the proposed SSTA calculates the probability density function of the delay of global critical cycle. The efficiency for the proposed SSTA is obtained from a technique that is derived from the principal component analysis (PCA) method. This technique simplifies the computation of mean, variance and covariance values of a set of correlated random variables. In order to consider spatial correlation in the Petri-Net based simulation, we also include a correlation coefficient to the proposed Variant-Timed Petri-Net which is obtained from partitioning the circuit. We also present a simulation tool of Variant-Timed Petri-Net and the results of the experiments are compared with Monte Carlo simulation-based method.     

Statistical Model for the Circuit Bandwidth Dependence of Low-Frequency Noise in Deep-Submicrometer MOSFETs

This paper covers measurement, analytical analysis, and Monte Carlo simulation of the frequency and bandwidth dependence of MOSFET low-frequency (LF) noise behavior. The model is based on microscopic device physics parameters, which cause statistical variation in the LF noise behavior of individual devices. Analytical equations for the statistical parameters are provided. The analytical model is compared to experimental data and Monte Carlo simulation results