On contact resistance measurement using four-terminal Kelvinstructures in advanced double-polysilicon bipolar transistor processes

The contact between a polycrystalline silicon (polysilicon) layer and a silicon substrate is investigated for an advanced double-polysilicon bipolar transistor process. Contact resistances are measured using four-terminal cross bridge Kelvin structures. The specific contact resistivity of the interface and the sheet resistance of the doped substrate region directly underneath the contact are extracted using a two-dimensional simulation model originally developed for metal-semiconductor contacts. The extracted sheet resistance values are found to be larger than those measured using van der Pauw structures combined with anodic oxidation and oxide removal. During the fabrication of the contacts, epitaxial realignment of the polysilicon in accordance to the substrate orientation and severe interdiffusion of dopants across the interface take place, which complicate the characterization. The validity of the two-dimensional simulation model applied to the poly-mono silicon contact is discussed     

Roughness improvement of the CoSi2/Si-interface for an application as buried silicide

The material CoSi₂ is preferred for the fabrication of buried silicide films between silicon device layer and buried oxide of SOI substrates for BICMOS integrations. Such an application needs excellent quality of the interface between the silicide and the silicon device layer. Using the conventional cobalt salicide process the roughness and waviness of the interface is too large for a device application. In this presentation three technologies to improve the CoSi₂/Si-interface quality were characterized. Using the first technology a very thin single crystalline CoSi₂ film was fabricated on a silicon substrate. This film acts as initial layer to produce thicker single crystalline silicide films. By the second technology an interlayer between cobalt and the silicon substrate was used to mediate an epitaxial CoSi₂ growth. Different types and materials were tested. Using the third technique a sacrificial layer of polycrystalline silicon between cobalt and the silicon substrate was consumed during the silicidation reaction. This method gives the best results with interface roughness values of less than 1 nm. The interface roughness was measured after CoSi₂ removal using AFM. A possible epitaxial growth of the silicide films was investigated with XRD analysis. Cross sectional SEM images were prepared to analyze the interface waviness and the CoSi₂ structure.     

Theory and application of a two-layer Hall technique

The electrical characterization of epitaxial layers on substrates of the opposite conductivity type presents serious problems if the p-n junction at the interface has significant leakage current such that it cannot be used to effectively electrically isolate the two regions. In order to meet the need for nondestructively characterizing such structures, a modification of the conventional Hall technique was developed in which the Hall measurements are made simultaneously on both the epitaxial layer and its substrate, the interface impedance is measured, and the interaction between the two regions is modeled and taken into account. This technique can be used to verify those cases in which the perturbing effects of a high-resistivity substrate are negligible, thus justifying conventional measurements on the epitaxial layer. In principle, it can be used to measure the resistivity and Hall coefficient of each layer separately if the assumptions of the model are realized in practice. The use of this technique is discussed and applied to the case of a thin n-type silicon epitaxial layer on: 1) a conducting substrate of indium-doped silicon that had a significant amount of leakage at the interface p-n junction and 2) a high-resistivity silicon substrate that had negligible influence on the measurement of the Hall coefficient of the epitaxial layer.     

Reduced leakage current of nickel induced crystallization poly-Si TFTs by a simple chemical oxide layer

Ni-metal-induced crystallization (MIC) of amorphous Si (α-Si) has been used to fabricate low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs). However, the leakage current of MIC-TFT is high. In this study, a chemical oxide layer was used to avoid excess of Ni atoms into α-Si layer during MIC process, which was simple and without extra expensive instrument. The minimum leakage current and on/off current ratio were significantly improved.     

Substrate orientation and processing effects on GaAs/Si misorientation in GaAs-on-Si grown by MBE

The angular misorientation of GaAs epitaxial layers grown on silicon substrates by molecular beam epitaxy has been measured using x-ray diffraction. A significant misorientation, or tilt, between the epitaxial layer and the substrate has been observed. The magnitude of the tilt depends on the initial substrate orientation, the silicon substrate type (float zone or Czochralski), postgrowth annealing, and epitaxial layer thickness. In almost all cases, the sense of the tilt is such that the GaAs 〈001〉 lies between the surface normal and the silicon 〈001〉. While the presence of interfacial dislocations with Burgers vectors that are approximately parallel to the heterointerface does predict a tilt between the substrate and the epitaxial layer, the sense of the tilt that arises from these dislocations is opposite to that observed experimentally. A model, based on the relief of misfit by dislocations inclined approximately 45 degrees to the interface, is proposed that correctly describes the observed tilt.     

Evaluation of the influence of an embedded porous silicon layer on the bulk lifetime of epitaxial layers and the interface recombination at the epitaxial layer/porous silicon interface

Porous silicon plays an important role in the concept of wafer‐equivalent epitaxial thin‐film solar cells. Although porous silicon is beneficial in terms of long‐wavelength optical confinement and gettering of metals, it could adversely affect the quality of the epitaxial silicon layer grown on top of it by introducing additional crystal defects such as stacking faults and dislocations. Furthermore, the epitaxial layer/porous silicon interface is highly recombinative because it has a large internal surface area that is not accessible for passivation. In this work, photoluminescence is used to extract the bulk lifetime of boron‐doped (10¹⁶/cm³) epitaxial layers grown on reorganised porous silicon as well as on pristine mono‐crystalline, Czochralski, p⁺ silicon. Surprisingly, the bulk lifetime of epitaxial layers on top of reorganised porous silicon is found to be higher (~100–115 µs) than that of layers on top of bare p⁺ substrate (32–50 µs). It is believed that proper surface closure prior to epitaxial growth and metal gettering effects of porous silicon play a role in ensuring a higher lifetime. Furthermore, the epitaxial layer/porous silicon interface was found to be ~250 times more recombinative than an epitaxial layer/p⁺ substrate interface (S ≅ 10³ cm/s). However, the inclusion of an epitaxially grown back surface field on top of the porous silicon effectively shields minority carriers from this highly recombinative interface. Copyright © 2013 John Wiley & Sons, Ltd.     

Hot carrier effects in polycrystalline silicon thin-film transistors: analysis of electrical characteristics and noise performance modifications

Hot-carrier effects on both the electrical characteristics and the noise performance in polycrystalline silicon thin film transistors are analysed. The devices were fabricated by using a combined solid phase crystallization (SPC) and excimer laser annealing (ELA) process, combining the beneficial aspects of the two techniques. Hot-carrier degradation results in the formation of both interface states, which have been evaluated through the analysis of the sheet conductance and of oxide traps near the insulator/semiconductor interface, as evidenced by the 1/f noise measurements. Oxide traps are calculated evaluating the flat band voltage spectral density associated with interface charge fluctuations in the damaged part of the interface. A strong correlation between interface state and oxide trap densities has been found, suggesting a common origin for the generation mechanism of the two types of defects.     

Large‐area epitaxial silicon solar cells based on industrial screen‐printing processes

Thin‐film epitaxial silicon solar cells are an attractive future alternative for bulk silicon solar cells incorporating many of the process advantages of the latter, but on a potentially cheap substrate. Several challenges have to be tackled before this potential can be successfully exploited on a large scale. This paper describes the points of interest and how IMEC aims to solve them. It presents a new step forward towards our final objective: the development of an industrial cell process based on screen‐printing for > 15% efficient epitaxial silicon solar cells on a low‐cost substrate. Included in the discussion are the substrates onto which the epitaxial deposition is done and how work is progressing in several research institutes and universities on the topic of a high‐throughput epitaxial reactor. The industrial screen‐printing process sequence developed at IMEC for these epitaxial silicon solar cells is presented, with emphasis on plasma texturing and improvement of the quality of the epitaxial layer. Efficiencies between 12 and 13% are presented for large‐area (98 cm²) epitaxial layers on highly doped UMG‐Si, off‐spec and reclaim material. Finally, the need for an internal reflection scheme is explained. A realistically achievable internal reflection at the epi/substrate interface of 70% will result in a calculated increase of 3 mA/cm² in short‐circuit current. An interfacial stack of porous silicon layers (Bragg reflectors) is chosen as a promising candidate and the challenges facing its incorporation between the epitaxial layer and the substrate are presented. Experimental work on this topic is reported and concentrates on the extraction of the internal reflection at the epi/substrate interface from reflectance measurements. Initial results show an internal reflectance between 30 and 60% with a four‐layer porous silicon stack. Resistance measurements for majority carrier flow through these porous silicon stacks are also included and show that no resistance increase is measurable for stacks up to four layers. Copyright © 2005 John Wiley & Sons, Ltd.     

耗尽区调制对氢化MILC Poly-Si TFT热产生漏电的影响

研究了热载流子应力下耗尽区调制效应对氢化金属诱导横向结晶多晶硅薄膜晶体管热产生漏电的影响.从理论上论证了热载流子应力下氢化金属诱导横向结晶多晶硅薄膜晶体管热产生漏电中的耗尽区调制效应的存在.并利用正、反向测量模式,从实验上进一步确认这种效应对氢化金属诱导横向结晶多晶硅薄膜晶体管热产生漏电的影响.发现在热载流子应力下,正、反向测量模式时,氢化金属诱导横向结晶多晶硅薄膜晶体管热产生漏电均随应力时间的增加而减小.但由于漏极和源极附近沟道区的表面势受热空穴注入影响的程度不同,热载流子应力下,正、反向测量模式的热产生漏电减小程度不同.理解热载流子应力下耗尽区调制效应对氢化金属诱导横向结晶多晶硅薄膜晶体管热产生漏电的影响,有助于成功设计电路.     

Domain epitaxial growth of TiN/Si(001), TiN/GaAs(001), and Si/TiN/Si(001) heterostructures by laser physical vapor deposition: Theory and experiment

We have successfully deposited epitaxial titanium nitride films on (001) silicon and (001) gallium arsenide substrates and multilayer Si/TiN/Si(001) epitaxial heterostructures using pulsed laser (KrF: λ = 248 nm, τ = 25 ns) physical vapor deposition. The deposition of TiN was carried out at a substrate temperature of 600°C on Si(001) and 400°C on GaAs(00l). The interfaces were sharp without any indication of interfacial reaction. The epitaxial relationships were found to be <001> TiN ‖<001> Si on the silicon substrate, <001> Si ‖<001> TiN |<001> Si on the heterostructure, and [1-10] TiN‖[110] GaAs and [001] TiN ‖[110] GaAs on the GaAs substrate. The growth in these large-mismatch systems is modeled and the various energy terms contributing to the growth of these films are determined. The domain matching epitaxy provides a mechanism of epitaxial growth in systems with large lattice mismatch.The epitaxial growth is characterized by domain epitaxial orientation relationships with m lattice constants of epilayer matching with n of the substrate and with a small residual domain mismatch present in the epilayer. This residual mismatch is responsible for a coherent strain energy. The magnitude of compression of Ti-N bond in the first atomic layer, contributing to the chemical free energy of the interface during the initial stages of growth, is found to be a very important factor in determining the orientation relationship. This result was used to explain the differences in the orientaion relationships between TiN/Si and TiN/GaAs systems. The various energy terms associated with the domain epitaxial growth are evaluated to illustrate that the domain epitaxial growth is energetically favorable compared to the lattice mismatched epitaxial growth. The results of this analysis illustrate that the observed variations in the epitaxial growth are consistent with the minimum energy configurations associated with the domain epitaxial growth.     

Structural characterization of low temperature Epi-silicon grown on {100} and {111} Si substrates using ultrahigh resolution cross-sectional TEM

Low defect-density epitaxial silicon was grown at 550°C, but it became polysilicon or amorphous silicon when the substrate was submitted to bombardment of ECR argon plasma prior to growth. Through carefully characterizing the interface and structure of low temperature epitaxial silicon films using ultrahigh resolution cross-sectional transmission electron microscopy (UHRXTEM), defects were found to have different features in silicon epitaxial layers grown on {100} and {111} silicon substrates. Twinning was more likely to generate in the epitaxial layer grown on the {111} silicon substrate while stacking faults had priority in forming in the epitaxial layer grown on the {100} substrate. The probable causes of different defect formation mechanisms were analyzed and discussed with the help of UHRXTEM lattice images. The atom model of the twin boundary in the epitaxial silicon film was analyzed in detail.     

Electrical characterization of the Si substrate in magneticallyenhanced or conventional reactive-ion-etch-exposed SiO2/p-Sistructures

The authors explore the silicon substrate damage produced by Cl ₂- and HBr-based reactive ion polycrystalline silicon overetches used in the definition of polycrystalline-Si/SiO₂/single-crystal-Si structures. The damage-caused traps, examined by means of deep-level transient spectroscopy, in the p-type Si are found to have concentrations that can exceed one tenth that of the boron dopant, and are detectable as far as ~10 μm from the SiO₂/Si interface. The concentration and depth of these traps are shown to depend on the polycrystalline Si overetch selectivity, on the initial oxide thickness, and on the magnetic field strength, as well as on the presence of hydrogen     

Influence of interfaces on electrical characteristics formation in monocrystalline silicon–noncrystalline ultrathin oxide – polycrystalline silicon structures

In this article, the electrically active centres (EAC) in a noncrystalline ultrathin oxide layer and at its interfaces with a monocrystalline silicon substrate and a polycrystalline silicon gate were investigated. These centres are (1) the fixed oxide charge centres in the ultrathin oxide layer and (2) the traps at its interfaces and in the polysilicon gate layer. In order to study these centres and to estimate their space and energy distributions, the modified C–V technique was applied. Among the results obtained, the significant role of the outer interface (polysilicon–ultrathin oxide) in the formation of electrical characterisitics and its sensitivity to the technological operations which possibly has an effect on the degree of its hydrogenation ought to be emphasised.     

Determination of the minority carrier lifetime in crystalline silicon thin‐film material

The effective minority carrier lifetimes on epitaxial silicon thin‐film material have been measured successfully using two independent microwave‐detected photoconductivity decay setups. Both measurement setups are found to be equally suited to determine the minority carrier lifetime of crystalline silicon thin‐film (cSiTF) material. The different measurement conditions to which the sample under investigation is exposed are critically analyzed by both simulations and measurements on a large number of lifetime samples. No systematic deviation between the lifetime results from different measurement setups could be observed, underlining the accuracy of the determined lifetime value. Subsequently, a method to separate the epitaxial bulk lifetime and the total recombination velocity, consisting of front surface and interface recombination between the epitaxial layer and the substrate, is presented. The method, based on different thicknesses of the epitaxial layer, is applied to all batches of this investigation. Each batch consists of samples with the same material quality but different epitaxial layer thicknesses whereas different batches differ in their material quality. In addition, the same method is also successfully applied on individual cSiTF samples. From the results, it can be concluded that the limiting factor of the effective minority carrier lifetime for the investigated solar‐grade cSiTF material is the elevated recombination velocity at the interface between epitaxial layer and the substrate compared with microelectronic‐grade material. In contrast, the samples cannot be classified into different material qualities by their epitaxial bulk lifetimes. Even on multicrystalline substrate, solar‐grade material can exhibit high epitaxial bulk lifetimes comparable to microelectronic‐grade material. Copyright © 2012 John Wiley & Sons, Ltd.     

Thermally generated leakage current mechanisms of metal-induced laterally crystallized n-type poly-Si TFTs under hot-carrier stress

Mechanisms of thermally generated leakage current have been systematically studied for metal-induced laterally crystallized n-type polycrystalline silicon thin film transistors under the hot-carrier stress. Various mechanisms of thermally generated leakage current are identified by both forward and reverse modes. The decrease of thermally generated leakage current is attributed to the depletion region modulation effect, which results from its shrinkage. While the increase of thermally generated leakage current is caused by the increase of the donor trap density, its increment relative to the initial one follows the Schottky model in the forward mode. Overall, the depletion region modulation effect dominates and the thermally generated leakage current decreases.     

Three dimensional devices fabricated by silicon epitaxial lateral overgrowth

Selective epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO) of silicon over oxide are used for novel device technologies in CMOS and bipolar with a large potential for BICMOS. A stacked inverted P-MOS device in crystalline Si on top of an oxidized poly-gate was fabricated with the critical “as-grown” interface state densities, between the ELO silicon grown over the existing poly-oxide, measured to be less than 2 × 10¹¹/ (cm²-eV) near midgap. A SiH₂Cl₂-HCl-H₂ in a LPCVD epitaxial system was employed at 150 Torr and at 900° C to produce the ELO/SEG material. The initial stacked-inverted 3D P-MOS devices typically show hole mobilities of greater than 160 cm²/V-s with adequate subthreshold characteristics for 3-dimensional CMOS implementation. A new form of SEG was used to grow single crystal silicon horizontally between dielectric walls to form SOI material in thin slabs, called confined lateral selective epitaxial growth (CLSEG). BJT-SOI device structures with β_dc > 150 were fabricated in CLSEG silicon to demonstrate the device quality material and to show the 3D-SOI capability.     

外延碳化硅纳米线的合成和显微结构研究

本文以硅为衬底,用热蒸发SiO粉末的方法合成了外延碳化硅(SiC)纳米线。利用扫描电子显微镜(SEM)、透射电子显微镜(TEM)等对SiC纳米线进行了电子显微学分析。实验发现,在SiC纳米线生长前,衬底上首先自发形成了一层SiC多晶膜,纳米线在这层多晶膜的某些晶粒上外延生长。在显微结构分析的基础上,本文探讨了外延生长一维纳米结构的有利条件是高的生长温度和低的生长速率。     

外延碳化硅纳米线的合成和显微结构研究

本文以硅为衬底,用热蒸发SiO粉末的方法合成了外延碳化硅(SiC)纳米线.利用扫描电子显微镜(SEM)、透射电子显微镜(TEM)等对SiC纳米线进行了电子显微学分析.实验发现,在SiC纳米线生长前,衬底上首先自发形成了一层SiC多晶膜,纳米线在这层多晶膜的某些晶粒上外延生长.在显微结构分析的基础上,本文探讨了外延生长一...     

Investigation on the interface of the polycrystalline silicon contacted diode formed with a stacked amorphous silicon film

The structural morphology of the poly-single crystalline silicon interface of a diode formed with a stacked-amorphous-silicon (SAS) film has been investigated. Secondary ion mass spectroscopy analyses showed the existence of multi-dopant segregation peaks at each layer boundary and at the poly-single crystalline silicon interface. The break-up at the poly-single silicon interface and the epitaxial regrowth of the polysilicon realigned to the silicon substrate were found to depend not only on the polysilicon deposition and the post annealing conditions, but also on the number and the thickness of the stacked amorphous silicon layers. For the diode formed with a six-layer stacked amorphous silicon, break-up of the interface was found to occur even at an annealing temperature as low as 900°C. After an additional annealing at 1000°C for 20 min, the interface was fully broken-up and the epitaxial regrowth layer of the polysilicon could be as thick as 760Å.     

CMOS device isolation using the selective-etch-and-refill-with-EPI (SEREPI) process

A technique has been developed for forming wells in a silicon substrate for CMOS IC's with an oxide layer providing lateral isolation between adjacent devices. The silicon in the wells is etched; oxide is formed on the sidewalls of the wells; and the wells are refilled with selectively deposited epitaxial silicon. Ring oscillators and submicrometer n- and p-channel MOS transistors have been fabricated using this isolation technique, and special latch-up test structures have been investigated.