DC voltage sensorless single-phase PFC converter

We propose a simple DC voltage sensorless single phase PFC converter by detecting an AC line voltage waveform. Both DC voltage and AC current sensors used in the conventional PFC converter are not required to construct the control system. The conventional converter circuit with a boost chopper circuit in the DC side from a rectifier circuit is used as the main PFC converter circuit. In the control system, the circuit parameters such as a series inductance L and equivalent load resistance value R/sub d/ are used to generate the sinusoidal current waveform. The DC voltage is directly controlled by the command input signal k/sub d/(=E/sub d//E/sub a/) for the boost chopper circuit. The DC voltage regulation is small because of the feed forward control for the AC line voltage E/sub a/ and no dependence of the circuit parameters. The sinusoidal current waveform in phase with the AC line voltage can be obtained. The feasibility of the proposed control system is verified by some simulation and experimental results.     

Novel broad-band bit-synchronization circuit module for optical interconnections

A novel broad-band and ultrafast bit-synchronization circuit module is proposed and fabricated for optical interconnections. In optical packet switch fabric or optical interconnection between electric circuit boards, instantaneous bit synchronization is crucial to properly retime incoming packets with a random phase and reduce the number of preamble overhead bits. The developed bit-synchronization circuit module has a new clock selection circuit, which is configured with a phase comparator and an amplitude comparator. Since device-dependent delay circuits, such as buffer amplifiers or RC phasors, are not adopted, the newly developed clock selection circuit can operate under broad-band frequencies. The bit-synchronization circuit module was fabricated with a Si-bipolar gate array and it can operate at broad-band bit rates of up to 10.5 Gb/s. It also exhibits a power sensitivity penalty as low as 3 dB for 10-Gb/s input signals. The synchronization acquisition time of less than 9 b over the entire 360/spl deg/ phase range was confirmed by experiment.     

A 1.5 Gbit/s GaAs four-channel selector LSI with monolithicallyintegrated newly structured GaAs ohmic contact MSM photodetector andlaser driver

A monolithic integrated 1.5 Gb/s high-speed four-channel optoelectronic integrated circuit (OEIC) selector GaAs LSI circuit is discussed. This LSI circuit incorporates photodetectors, preamplifiers, a selector, a decision circuit, and a high-speed laser driver. To achieve high efficiency, a AuGe/Ni-GaAs structured ohmic contact metal-semiconductor-metal (OC-MSM) is used for the interdigitated structural photodetector. With this OC-MSM structure, photocurrent is approximately twice as effective as with the conventional Schottky contact MSM structure. The new LSI has a maximum operating speed of 1.5 Gb/s and exhibits low power dissipation of 927 mW     

A Spectrum-Shaping Output Stage for IR-UWB Transmitters

This paper presents a novel on-chip wideband balanced-to-unbalanced (balun) transition circuit based on a complementary current inversion method. The proposed circuit features an easily controllable wide bandpass characteristic and is intended to be used as an output stage to filter ill-defined spectra of time-domain ultra-wideband pulses to fit regulation masks. We investigated the circuit in an active topology driven by differential pairs. A mathematical analysis is presented, as well as the implementation of an integrated circuit realized with IBM BiCMOS 0.18-$mu{hbox{m}}$ technology.      

5-Gbit/s Si integrated regenerative demultiplexer and decision circuit

A silicon bipolar circuit is presented which may be used as either a 1:2 demultiplexer or a decision circuit up to the bit rate of 5 Gb/s. The circuit was fabricated with a standard bipolar technology with oxide-wall isolation, 2-/spl mu/m emitter stripe widths, and a transit frequency of about 9 GHz at V/SUB CE/=1 V. The high-speed performance of the circuit was achieved by applying a double sampling scheme. Clock phase margin (CPM) and decision ambiguity are 120/spl deg/ and 150 mV at 4 Gb/s, respectively. CPM at 5 Gbit/s is about 90%. Decision feedback equalization may be included in the circuit scheme for optional use.     

APD前置放大模块电路建模与仿真分析

采用SACM—APD电路模型以及对前置放大电路的分析，建立了APD前置放大模块电路模型，并对模型进行瞬态特性和交流特性仿真分析。模拟得到响应度约为400kV／W；信号沿上升下降时间为6ns，-3dB带宽约为73MHz，与研制的APD前置放大模块实际试验测试值相吻合。     

酞菁铜缓冲层对有机太阳能电池开路电压的影响

用p型有机半导体材料酞菁铜作为阴极缓冲层制作了器件结构为氧化铟锡/酞菁锌/碳六十/酞菁铜/铝的有机小分子太阳能电池, 对器件进行电学测量发现酞菁铜缓冲层的厚度对器件的开路电压有明显影响.基于半导体器件物理分析了光照下测量得到的电流-电压曲线, 由拟合结果得到的器件参数表明高理想因子导致了器件开路电压升高, 其原因为器件的输运特性不只受酞菁锌与碳六十形成的p-n结影响, 还与酞菁铜缓冲层与铝电极形成的肖特基接触有关.研究表明在有机太阳能电池器件中引入一个合适的缓冲层/阴极肖特基结可以提高器件的开路电压.     

一种智能检测系统电路设计

简述了一种智能检测系统电路的设计，具体分析其中超高部分、轨距部分电路、里程部分测量电路、温度部分测量电路的设计，中央处理与A／D转换电路，电源变换电路。     

A Simple Schmitt Trigger Circuit with Grounded Passive Elements and Its Application to Square/Triangular Wave Generator

This paper introduces a new simple Schmitt trigger circuit using a plus-type differential voltage-current conveyor (DVCC+) and only two grounded resistors. The proposed circuit is very simple and enjoys adjustable lower and higher threshold voltages as well as the output saturation levels. The application of the proposed Schmitt trigger circuit to the square/triangular wave generator is also given. Moreover, a current feedback operational amplifier (CFOA)-based square/triangular wave generator is derived from the proposed DVCC+-based circuit. Simulation and experimental results are presented to exhibit the performance of the proposed circuits.     

DVB-T接收前端下变频电路设计

介绍了DVB-T接收系统前端下变频的基本原理,设计了DVB-TRF信号到基带信号的下变频电路。电路基本原理为,调谐器将RF信号混频到中频,A/D转换器带通采样,将中频信号搬移到基带部分,得到数字基带信号。电路的控制部分由MCU和D/A转换器组成。本电路实现了对DVB-TRF信号的转换,得到了DVB-T数字基带信号。     

基于忆阻的全功能巴甫洛夫联想记忆电路的设计、实现与分析

联想记忆是一种描述生物学习和遗忘过程的重要机制,对构建神经形态计算系统和模拟类脑功能有重要的意义,设计并实现联想记忆电路成为人工神经网络领域内的研究热点。巴甫洛夫条件反射实验作为联想记忆的经典案例之一,其硬件电路的实现方案仍然存在电路设计复杂、功能不完善以及过程描述不清晰等问题。基于此,该文融合经典的条件反射理论和纳米科学技术,提出一种基于忆阻的全功能巴甫洛夫联想记忆电路。首先,基于水热合成法和磁控溅射法制备了Ag/TiO_x nanobelt/Ti结构的忆阻器,通过电化学工作站、四探针测试台和透射电子显微镜联合完成相应的性能测试;接着,利用测试得到的电化学数据,构建了Ag/TiO_x nanobelt/Ti忆阻器的数学模型和SPICE电路模型,并通过客观评价验证模型的精确度;进一步,基于提出的Ag/TiO_x nanobelt/Ti忆阻器模型,设计了一种全功能巴甫洛夫联想记忆电路,通过电路描述和功能分析,论述了该电路能够正确模拟巴甫洛夫实验中2类学习过程和3类遗忘过程;最后,通过一系列计算机仿真和分析,验证了所提方案的正确性和有效性。     

Voice/Data Integration Using Circuit Switched Networks

This paper assesses the impact of integrating voice and data over circuit switched networks. Three main types of circuit switching are considered: 1) traditional circuit switching, 2)fast circuit switchingemploying advanced switching speeds, and 3) enhanced circuit switchingemploying time assigned speech interpolation (TASI) and adaptive data multiplexing (ADM) techniques. The circuit switching networks are evaluated in terms of two main network performance parameters: transmission efficiency and delay. In addition, an evaluation is made of such things as protocol and error control, precedence and preemption, routing and flow control, synchronization, voice continuity, probability of error or loss, and classmarking flexibility. One of the main conclusions of this paper is that circuit switching technologies have several deficiencies associated with providing integrated voice/data service and that the future lies in the effective use of packet and hybrid (circuit/packet) switching technologies.     

Single transistor MOS RAM using a short-channel MOS transistor

The relationship between sensitivity and other factors in the sense circuit of a single transistor MOS RAM has been investigated by computer simulation. An expression for sensitivity of the sense circuit has been derived. It suggests key points to increase the sensitivity of the sense circuit. A new sense circuit that defects a signal less than /spl plusmn/30 mV and has low power capability 50 /spl mu/W/circuit is realized by following the suggestions. The high performance of the proposed sense circuit has been verified through the fabrication of a 1K MOS RAM. Fine pattern technology, such as 2-/spl mu/m minimum pattern width and spacing and 500-/spl Aring/ gate oxide thickness, has been adopted. The threshold voltage of the MOS transistor is 0.8 V and dc supplies are 7 V and /spl plusmn/2 V. This 1K RAM has characteristics of 80-ns access time, 150-ns cycle time, and 30-mW power dissipation.     

A General Spectral Analysis of Time Jitter Produced in a Regenerative Repeater

A general theory is presented for evaluating the spectral density of time jitter produced in a self-timed regenerative repeater. The timing circuit consists of a general memoryless nonlinear device followed by a narrow-band tank circuit tuned as close as possible to the symbol rate; the signal (timing wave) at the output of the circuit has both amplitude and phase modulations that cause the timing error (jitter). The theory includes the cases of arbitrary pattern statistics, pulse waveform, and nonlinear processing, in contrast to previous work which is strongly limited to the assumptions of pattern symbol independence and particular nonlinearities. The time jitter is treated as a discrete-parameter random process and its spectral density is finally related to the input message statistics, pulse waveform, and timing circuit parameters. In most cases the spectral density turns out to be a rational function of exp (j2pifT),fbeing the frequency andTthe symbol period. Hence, a spectral factorization can be obtained that leads to a useful linear equivalent circuit of the timing (nonlinear) circuit (NLC). This last feature is illustrated by three examples.     

实时光栅衍射效率测量的光功率采集器设计

针对常用光功率计通道单一、测量过程复杂以及自动化程度较低等缺陷,设计了一种基于实时光栅衍射效率测量的双路光功率自动采集器。基于普通光功率计的理论和实际设计方法,提出设计方案。设计硬件方面包括前置放大电路、电源升压电路、A/D转换电路、单片机控制电路以及串口通信电路的设计。在软件方面完成了A/D转换控制程序以及数据传输、计算与存储程序的设计。设计采用633 nm作为测量的标准激光波长,测量功率范围在0.01~10 mW,设计完成后,光栅衍射效率测量精度保证在±4.5%。     

Dealing with hot-carrier aging in nMOS and DMOS, models, simulations and characterizations

Circuit aging simulation is seen as a true enhancement to device and circuit simulation. To predict aging of circuit performance, tested models for device parameters are needed in which the change in device behavior as function of time, given the biasing and temperature condition of the device in the circuit, is correctly modeled. The time scale here is the lifetime of the product. A circuit simulator in the transient mode can predict circuit aging using a transformation of the dc/ac biasing situation with an appropriate scaling mechanism. Device aging models that can be implemented in such a circuit simulator are presented here for nMOS and DMOS (double diffused MOS) based on measurements and empirical modeling.     

Current-mode divide-by-two circuit

A current-mode divide-by-two circuit is presented which does not rely on well matched components and a high gain opamp. The circuit can be employee as a reference-generating circuit of an algorithmic current-mode A/D convertor.<>     

InP DHBT-Based Monolithically Integrated CDR/DEMUX IC Operating at 80 Gbit/s

In this paper, a monolithically integrated clock and data recovery (CDR) circuit with 1:2 demultiplexer (DEMUX), which is intended for use in 80 Gbit/s optical fiber links, is presented. The integrated circuit (IC) is manufactured using an in-house InP double heterostructure bipolar transistor (DHBT) technology, exhibiting cut-off frequency values of more than 220 GHz for both$f_T$and$f_max $. The CDR circuit in the topology of a phase-locked loop (PLL) is mainly composed of a half-rate linear phase detector including a 1:2 demultiplexer (DEMUX), a loop filter, and a voltage-controlled oscillator (VCO). Hence, the corresponding architecture of each of these components as well as the applied circuit design technique are extensively addressed. Concerning the performance achieved by the CDR/DEMUX IC, the recovered and demultiplexed 40 Gbit/s data from an 80 Gbit/s input signal feature clear eye opening with a signal swing as high as 600$hboxmV_ pp$. The extracted 40 GHz clock signal shows a phase noise as low as$- hbox98~dBc/hboxHz$at 100 kHz offset frequency. The corresponding rms jitter amounts to 0.37 ps while the peak-to-peak jitter is as low as 1.66 ps. At a single supply voltage of$-hbox4.8~V$, the power consumption of the full CDR/DEMUX IC amounts to 1.65 W. To the authors' best knowledge, this work demonstrates the first CDR circuit at the achieved data rate, regardless of all the competing semiconductor technologies.     

Femto Joule logic circuit with enhancement-type Schottky barrier gate FET

As an approach to an advanced LSI logic, a high-speed and low-power femto-joule logic circuit has been developed by using an enhancement-type Schottky barrier gate FET (ESBT) with³¹P implanted channel layer. A direct coupled transistor logic (DCTL) was designed using ESBT and resistor as a basic logic circuit. To evaluate the dynamic performance of the logic circuit, a 15-stage ring oscillator with an output buffer was integrated on a chip. A power-delay product was found in the femto-joule range. The logic swing is about 0.4 V and typical noise margin is 30 percent of the logic swing. A high-speed (40 ns) and low-power (10 mW) 4 bit ALU has been developed by using DCTL, NOR gates. Furthermore, improving ESBT channel layer carrier profile to the higher carrier concentration and abruptly changing shallower carrier profile by³¹P and¹¹B double implantation resulted in advanced characteristics of ESBT and logic circuit using it as follows. ESBT transconductance was increased by a factor of two. Power-delay product reduced to 80 percent of that of logic circuit, using ESBT with³¹P single implanted channel layer, was satisfactorily confirmed, together with a circuit density as large as 300 gates/ mm².     

一种模拟惯性组合输出电路的设计与实现

为完成对某型弹载计算机的自动测试,设计一种模拟惯性组合输出电路。该电路硬件主要以基于PCI总线的数字量输入输出卡PCI144DI／O及可编程定时计数器82C54为核心,电路硬件结构简单,使用灵活方便。控制软件基于Labwindows／CVI软件平台开发设计。实验证明,该电路完全能够模拟惯性组合输出脉冲宽度、脉冲周期及脉冲个数可调的脉冲信号,并且成本低、开发周期短。