通用CPU性能基准测试研究综述

CPU性能基准测试旨在给出可对比、定量的指标数据，为产品选型提供依据，它已成为引领计算产业发展的风向标之一. CPU技术发展迅速，性能基准测试也在不断演进.本文对包含SPEC CPU在内的主流基准测试进行了研究，从测试目标、测试方法等角度，综述主流CPU基准测试的演进过程、最新研究成果，以及通用CPU性能指标和基准测试需求，分析了通用CPU性能基准测试所面临的挑战，并对今后可能的研究趋势进行了展望.     

我国CPU发展战略探讨

CPU是电子信息产品的核心,是半导体产业技术最密集、最具战略价值的产品,也是一个国家技术实力的象征。基于安全与市场利益的考虑,欧美、日、韩等集成电路强国一直致力于本国CPU的设计与研制。中国作为一个大国,发展具有自主知识产权的国产CPU是提高信息产业自主创新能力、转变经济增长方式的重要举措和着力点。本文首先分析了我国发展CPU的国际形势,接下来重点介绍了我国CPU发展现状及存在的主要问题。在此基础上深入论证了国际主流CPU厂商的发展战略及对我国CPU产业的影响。最后提出了我国发展CPU产业的技术路线与战略取向。     

基于可配置处理器的H.264解码芯片的选型

首先分析了可配置CPU的技术特点,然后介绍了市场上的两种可配置CPU的特性.通过对H.264标准的深入分析,最终选择了一种利用多个可配置CPU来实现H.264解码器芯片的设计方案.     

专业后期工作站的国产替代畅想

在Windows7安全补丁服务停止提供的背景下,总台技术局对国产CPU和操作系统的国产终端产品进行了替换Windows7终端的技术可行性测试.本文主要介绍了当前背景下国产CPU和操作系统的国产终端产品在专业制作领域中的测试简况,专业化工作站的国产替代发展趋势和进展,并对国产化替代的进一步发展提出畅想.     

结构网格CFD应用程序在天河超级计算机上的高效并行与优化

对多区结构网格大规模CFD流场模拟的高效并行方法进行了研究,以天河超级计算机平台的CPU同构计算环境和CPU+MIC异构计算环境为例,重点讨论了CFD应用特点与超级计算机运行环境相适应的性能优化与改进策略,发展了一系列多层次并行与性能优化方法.通过在天河2高性能计算平台上进行了多个算例的数值模拟,验证了这些优化方法的并行效果;在CPU+MIC异构平台上模拟的最大CFD问题规模达到6800亿个网格单元,共使用137.6万CPU+MIC处理器核,测试结果表明在CPU+MIC异构平台上移植优化后的程序性能提高2.6倍左右,且具有良好的可扩展性.     

基于I2C的CPU温度监控功能设计与实现

随着CPU处理性能的不断提高,CPU功耗也不断增加.高功耗产生的热量如果无法及时散热,将引起CPU温度持续升高,不但影响CPU性能,甚至可能造成硬件损坏,CPU温度监控功能显得尤为重要.针对以上问题,提出了一种基于I2C的CPU温度监控功能实现方法.通过I2C总线获取ADT7461温度芯片采集的CPU温度值,根据采集到...     

芯片厂商引领广电的人工智能化

本文从芯片厂商的角度分析人工智能(AI)得以迅速发展的三大关键要素.并以当前AI中最核心的深度学习技术为例,分析其训练和执行两个阶段分别对硬件的需求,得出GPU和CPU性能在AI应用的重要性.随后介绍了兆芯在GPU和CPU方面的技术优势,以及在广电领域,兆芯凭借自身平台优势引领AI产业发展及推进AI应用落地的实际案例.     

一种任意时间片长度对CPU上下文切换代价影响消除的新方法

分析并量化了操作系统任务调度时上下文切换对CPU性能影响,得出了任务上下文切换代价对CPU效率影响关系.在此影响关系的基础上,提出了一种可行的Hyper-Scheduling方法.此方法通过在CPU内部设置一条特殊的任务切换专用流水线数据通路,并在通用寄存器堆上寄生一个相同的寄存器堆(影子寄存器堆)和监视访存状态的寄生逻辑,来监视各硬件资源运行情况,实现在CPU硬件资源闲置状态时进行预先数据准备或任务保存.当任务切换时将这条特殊数据通路与CPU主数据通路流水线进行交换,使上下文切换时间可趋近于零,任务切换代价被消除,上下文频繁切换或时间片长度缩短至近于零的情况下,CPU效率仍能够保持性能最大化.     

一种基于动态调频的有源RFID低功耗标签设计

针对2.4GHz有源RFID标签的功耗问题,提出了一种动态调频(DFM)的低功耗设计方法.标签采用NXP的LPC1758MCU和TI的CC2520射频芯片,通过改变CPU时钟源、配置PLL值、CPU时钟分频器值来控制CPU频率.根据代码片段运行的特征,自适应地调整CPU时钟频率.实验表明,对比标签CPU动态倍频前后,实现了标签待机功耗减半.     

虚拟CPU负载预测算法性能评估

准确的虚拟CPU负载预测是提高虚拟机CPU调度性能的重要前提,然而,虚拟机操作系统环境下,虚拟CPU负载预测方法需要尽可能简单、有效.针对虚拟机CPU调度应用场景,以实际CPU负载为研究对象,选取五种简单的时间序列预测算法,详细评估其虚拟CPU负载预测性能,为虚拟机CPU调度的实现提供了研究基础.结果表明,平均移动法、...     

以CPU为核心的数字系统的VHDL建模研究

本文介绍了ＶＨＤＬ在以ＣＰＵ为核心的数字系统中建模的方法，在算法级上给出ＣＰＵ的功能描述，对ＭＥＭＯＲＹ建立简化模型，对接口电路给出信号的定时描述。     

Scheduling techniques for reducing processor energy use in MacOS

The CPU is one of the major power consumers in a portable computer, and considerable power can be saved by turning off the CPU when it is not doing useful work. In Apple's MacOS, however, idle time is often converted to busy waiting, and generally it is very hard to tell when no useful computation is occurring. In this paper, we suggest several heuristic techniques for identifying this condition, and for temporarily putting the CPU in a low‐power state. These techniques include turning off the processor when all processes are blocked, turning off the processor when processes appear to be busy waiting, and extending real time process sleep periods. We use trace‐driven simulation, using processor run interval traces, to evaluate the potential energy savings and performance impact. We find that these techniques save considerable amounts of processor energy (as much as 66%), while having very little performance impact (less than 2% increase in run time). Implementing the proposed strategies should increase battery lifetime by approximately 20% relative to Apple's current CPU power management strategy, since the CPU and associated logic are responsible for about 32% of power use; similar techniques should be applicable to operating systems with similar behavior. This revised version was published online in June 2006 with corrections to the Cover Date.     

Network subsystem design

It is argued that the bandwidth of the CPU/memory data path on workstations will remain within the same order of magnitude as the network bandwidth delivered to the workstation. This makes it essential that the number of times network data traverses the CPU/memory data path be minimized. Evidence which suggests that the cache cannot be expected to significantly reduce the number of data movements over this path is reviewed. Hardware and software techniques for avoiding the CPU/memory bottleneck are discussed. It is concluded that naively applying these techniques is not sufficient for achieving good application-to-application throughput; they must also be carefully integrated. Various techniques that can be integrated to provide a high bandwidth data path between I/O devices and application programs are outlined     

Application of Error-Correcting Codes in Computer Reliability Studies

The use of error-correcting codes as one of the important techniques to increase computer system reliability is introduced. The different codes used in the central processing unit (CPU) are described. Since the CPU usually contains the data path, logic, and arithmetic units, the codes used in this area are error-detecting codes, such as parity check codes and residue codes. The codes used or suggested for the memory system are discussed, emphasis being placed on parity check codes, two-dimensional codes, Hamming codes and other recently developed codes. The various codes used in the input/output system are presented. The input/output area of the computer system is relatively unreliable as compared with CPU or memory; therefore, error-correcting codes used in this area usually are much more powerful than single parity check codes. These include codes for the magnetic tape, disk, and drum units. The error coding techniques are compared with other techniques for increasing computer system reliability. The future trend of using error-correcting codes in a computer system is also discussed.     

应用空域分解法研究复杂物体的散射特性

本文给出了三种空域分解法迭代格式.在入射波非对称而结构对称时.给出了一种处理方法.从而减少计算量和存储量.以园柱体和平板复合体为目标,对TM波正入射时三种迭代格式下的结果及存储量计算量作了比较,然后分别计算了TM波和TE波入射时的散射待性.对入射方向和耦合的影响进行了讨论.     

Convergence properties of Newton's method for the solution of the semiconductor transport equations and hybrid solution techniques for multidimensional simulation of VLSI devices

In this paper the Kantorovich theorem has been modified to evaluate the simple sufficient conditions for the quadratic convergence of Newton's method. By the modified Kantorovich theorem, convergence properties of Poisson's equation and more generally total transport equations have been investigated. It is shown that sufficient condition of quadratic convergence of Newton's method can be satisfied when the maximum magnitude norm of the correction vectors becomes less than 0.5 kT/q for the Poisson's equation, while for the total carrier transport equations this criterion becomes 0.25 kT/q. Under the light of these convergence criteria, a hybrid solution algorithm is defined which employs both the coupled and decoupled solution techniques. This method and a variable mesh concept are combined to achieve dramatic reduction in CPU time for the simulation of VLSI devices. It is demonstrated that overall CPU time is reduced by a factor of two to eight by employing these techniques.     

基于AT P G的可测性设计在RSICCPU的应用

介绍了自动测试模式生成的测试故障模型和设计流程,以及自动测试模生成结合可测性设计技术在测试RSIC CPU制造缺陷中的应用。     

Full-wave analysis and modeling of multiconductor transmissionlines via 2-D-FDTD and signal-processing techniques

The full-wave analysis of multiconductor transmission lines on an inhomogeneous medium is performed by using the two-dimensional finite-difference time-domain (FDTD) method. The FDTD data are analyzed by using signal-processing techniques. The use of high-resolution signal-processing techniques allows one to extract the dispersive characteristics and normal-mode parameters, which include decoupled modal impedances and current and voltage eigenvector matrices. A new algorithm for extracting frequency-dependent equivalent-circuit parameters is presented in this paper. Smaller CPU time and memory are required as compared to the three-dimensional FDTD case. Numerical results are presented to demonstrate the accuracy and efficiency of this method     

Minimizing Average Schedule Length under Memory Constraints by Optimal Partitioning and Prefetching

Over the last 20 years, the performance gap between CPU and memory has been steadily increasing. As a result, a variety of techniques has been devised to hide that performance gap, from intermediate fast memories (caches) to various prefetching and memory management techniques for manipulating the data present in these caches. In this paper we propose a new memory management technique that takes advantage of access pattern information that is available at compile time by prefetching certain data elements before explicitly being requested by the CPU, as well as maintaining certain data in the local memory over a number of iterations. In order to better take advantage of the locality of reference present in loop structures, our technique also uses a new approach to memory by partitioning it and reducing execution to each partition, so that information is reused at much smaller time intervals than if execution followed the usual pattern. These combined approaches—using a new set of memory instructions as well as partitioning the memory—lead to improvements in total execution time of approximately 25% over existing methods.