Low temperature short channel polycrystalline silicon thin film transistors with high reliability for flat panel display

We have investigated a short channel (L ≤ 1 μm) effect on the electrical reliability of the low temperature poly-Si thin film transistors (TFT) on a glass substrate. The threshold voltage of the p-type poly-Si TFT was observed to be decreased due to the drain induced barrier lowering as the channel length decreased. In the n-type poly-Si TFT with a lightly-doped-drain (LDD), the threshold voltage was slightly decreased when a high drain voltage was applied, while the field effect mobility decreased due to the series resistance of the LDD region in the short channel poly-Si TFT. As the temperature increased, the field effect mobility increased about 80% due to the increase of the thermal activated carrier concentration. We have also investigated the degradation of a short channel poly-Si TFT under hot carrier and self-heating stress. After hot carrier stress (V_GS = 2V, V_DS = 15V), the field effect mobility was considerably decreased up to 20% due to the trap state generation induced by the hot carrier. The subthreshold slope and threshold voltage were scarcely degraded. After the self-heating stress (V_GS = V_DS = 15V), the subthreshold slope, mobility, and threshold voltage were degraded. Transfer characteristics measured at the high drain voltage (V_DS = 10V) were shifted to a negative direction because of hole trapping at the backside interface between the polysilicon film and buffer oxide on the glass substrate.     

Formation of polycrystalline-Si thin-film transistors with tunneling field-effect-transistor structure

The formation of a poly-Si thin-film transistor (TFT) device with a tunneling field-effect-transistor (TFET) structure has been studied. With scaling the gate length down to 1 μm, the poly-Si TFT device with a conventional metal-oxide-semiconductor-field-effect-transistor structure would be considerably degraded, which exhibits an off-state leakage of about 10 nA/μm at a drain bias of 6 V. The short channel effect would tend to cause the source/drain punch-through and also increase the lateral electric field within the channel region, thus enhancing the carried field emission via trap states. The TFET structure can be employed to alleviate the short channel effect in the poly-Si TFT device. As a result, even for a gate length of 1 μm, the poly-Si TFT device with the TFET structure can exhibit an off-state leakage smaller than 1 pA/μm and an on/off current ratio of about eight orders at a drain bias of 7 V. Furthermore, even for a gate length of only 0.2 μm, the resultant poly-Si TFT device with the TFET structure can exhibit good electrical characteristics with an off-state leakage smaller than 10 pA/µm and an on/off current ratio of about six orders at a drain bias of 3.2 V. As a result, this scheme is promising for implementing a high packing density of poly-Si TFT devices.     

Comparison of a-Si TFTs fabricated by Cat-CVD and PECVD methods

We investigate the characteristics of amorphous silicon thin film transistors (a-Si TFTs) fabricated by plasma-enhanced chemical vapor deposition (PECVD) and catalytic CVD (Cat-CVD), and their stability under bias and temperature (BT) accelerated stress. The Cat-CVD a-Si TFTs have off-leak current as small as 10^− 14 A, and a smaller threshold voltage shift under the BT stress. The superiority in off-leak current and stability is observed in the Cat-CVD a-Si TFTs fabricated at both 320 °C and 180 °C. The high performance and stability of the Cat-CVD a-Si TFTs will enable to use low-cost glass substrates and result in a cost reduction of TFT fabrication.     

Device degradation behavior and polysilicon film morphology of thin film transistors fabricated using advanced excimer laser lateral solidification techniques

The degradation of polysilicon thin film transistors fabricated in films obtained using variations of advanced through-mask excimer laser anneal sequential lateral solidification (SLS) schemes was investigated. The morphology and grain structure of these 50 nm thick polysilicon films was studied using SEM and AFM. Very elongated or square-like polycrystalline silicon grains were observed, as shaped by each crystallization technique. Hot carrier stressing measurements, under gate and drain DC biases, were performed and the TFT device parameters and characteristics were extracted for various stressing times. The threshold voltage V_th, subthreshold slope S and transconductance G_m were observed to exhibit shifts with stressing time, indicating some active layer and interface degradation ascribed to hot carrier injection and trap generation. These shifts depended both on stress conditions and on the fabrication technique used. The hot carrier stressing results thus indicate that the material structure affects the degradation rates of the TFT parameters and trap densities. Furthermore, the device structure and the crystallization conditions, with the resulting film morphology, affect not only the TFT degradation behavior but also other aspects of device performance; the susceptibility to drain current avalanche effects was found to be lower for TFTs in 2^N-shot polysilicon compared to ones in very elongated grain (directional) material.     

Comprehensive studies on the stabilities of a-In-Ga-Zn-O based thin film transistor by constant current stress

Stability under constant current stress, along with hysteresis characteristics, was studied for a-In-Ga-Zn-O thin-film transistors (TFTs) in several atmospheres and at several temperatures. Unannealed TFTs showed rather large instability; i.e., large hysteresis in transfer curves (ΔV_G > 0.8 V) and large positive threshold voltage shift (ΔV_th > 10 V for 50 h tests at 5 µA) with deterioration of subthreshold voltage swing was observed. The instability for the unannealed TFT had a strong dependence on the stress atmosphere and the stress temperature, which suggests that trap states generated by the stress test is related to oxygen vacancy formed by breaking weak chemical bonds. Wet annealing improved stability; the hysteresis disappeared and the ΔV_th was reduced to < 2 V. The improvement is considered to be related to the reduction of weak chemical bonds by wet annealing with the strong oxidation power of water molecules.     

High-performance metal-induced lateral-crystallization polysilicon thin-film transistors with multiple nanowire channels and multiple gates

In this study, pattern-dependent nickel (Ni) metal-induced lateral-crystallization (Ni-MILC) polysilicon thin-film transistors (poly-Si TFTs) with ten nanowire channels and multigate structure were fabricated and characterized. Experimental results reveal that applying ten nanowire channels improves the performance of an Ni-MILC poly-Si TFT, which thus has a higher ON current, a lower leakage current, and a lower threshold voltage (V/sub th/) than single-channel TFTs. Furthermore, the experimental results reveal that combining the multigate structure and ten nanowire channels further enhances the entire performance of Ni-MILC TFTs, which thus have a low leakage current, a high ON/OFF ratio, a low V/sub th/, a steep subthreshold swing, and kink-free output characteristics. The multigate structure with ten-nanowire-channel Ni-MILC TFTs has a few poly-Si grain boundary defects, a low lateral electrical field, and a gate-channel shortening effect, all of which are associated with such high-performance characteristics.     

High-performance bottom-gate poly-Si polysilicon-oxide-nitride-oxide-silicon thin film transistors crystallized by excimer laser irradiation for two-bit nonvolatile memory applications

High-performance bottom-gate (BG) poly-Si polysilicon-oxide-nitride-oxide-silicon (SONOS) TFTs with single grain boundary perpendicular to the channel direction have been demonstrated via simple excimer-laser-crystallization (ELC) method. Under an appropriate laser irradiation energy density, the silicon grain growth started from the thicker sidewalls intrinsically caused by the bottom-gate structure and impinged in the center of the channel. Therefore, the proposed ELC BG SONOS TFTs exhibited superior transistor characteristics than the conventional solid-phase-crystallized ones, such as higher field effect mobility of 393 cm2/V-s and steeper subthreshold swing of 0.296 V/dec. Due to the high field effect mobility, the electron velocity, impact ionization, and conduction current density could be enhanced effectively, thus improving the memory performance. Based on this mobility-enhanced scheme, the proposed ELC BG SONOS TFTs exhibited better performance in terms of relatively large memory window, high program/erase speed, long retention time, and 2-bit operation. Such an ELC BG SONOS TFT with single-grain boundary in the channel is compatible with the conventional a-Si TFT process and therefore very promising for the embedded memory in the system-on-panel applications.     

Interface diffusion characteristics of Al-2 at.%Nd/n + a-Si:H and Al-2 at.%Nd/n + poly-Si bilayers

In order to use Al-2 at.%Nd as the source-drain electrode of hydrogenated amorphous silicon thin film transistors (a-Si:H TFTs) without diffusion barrier, the diffusion characteristics of Al-2 at.%Nd into phosphorus-doped (n+) a-Si:H were studied, and diffusion between Al-2 at.%Nd and phosphorous-doped poly-Si (n + poly-Si) was also investigated for comparison. The electric resistance variation of Al-2 at.%Nd, n + a-Si:H, and n + poly-Si was measured by four-point probe method at every annealing step, and each surface was inspected by optical microscope. Auger Electron Spectroscopy and X-ray Photoelectron Spectroscopy were used to analyze atomic diffusion progress with the variation of annealing temperature. Through these analyses, we ascertain that the Nd element of Al-2 at.%Nd hinders the diffusion between Al and Si, and n + a-Si:H is stable up to 300 °C and n + poly-Si is stable up to 400 °C against the diffusion of Al-2 at.%Nd. Thus Al-2 at.%Nd can be utilized as the source-drain electrode of a-Si:H TFTs below 300 °C and poly-Si TFTs below 400 °C without diffusion barrier.     

Influence of process steps on the performance of microcrystalline silicon thin film transistors

Bottom gate microcrystalline silicon thin film transistors (μc-Si TFT) have been realized with two types of films: μc-Si(1) and μc-Si(2) with crystalline fraction of 80% and close to 100% respectively. On these TFTs we applied two types of passivation (SiN_x and resist). μc-Si TFTs with resist as a passivation layer present a low leakage current of about 2.10^− 12 A for V_G = − 10 and V_D = 0.1V an ON to OFF current ratio of 10⁶, a threshold voltage of 7 V, a linear mobility of 0.1 cm²/V s, and a sub-threshold voltage of 0.9 V/dec. Microcrystalline silicon TFTs with SiN_x as a passivation present a new phenomenon: a parasitic current for negative gate voltage (− 15 V) causes a bump and changes the shape of the sub-threshold region. This excess current can be explained by and oxygen contamination at the back interface.     

Stability analysis and robust design of polysilicon TFT load 4M SRAM cell by statistical method

Advances in high-density static RAM (SRAM) technology have been focused primarily on the application of p-channel polysilicon (poly-Si) thin film transistors (TFTs) as memory cell loads. The penalty, however, is that the electrical characteristics of poly-Si TFTs, such as on-current (I_on), off-current (I_off), subthreshold slope (s) and threshold voltage (V_th), have large variations, a problem which becomes much more serious as the device size is reduced. In this paper we model the relation between SRAM stability and variations in poly-Si TFT characteristics by a statistical method. From our model it is found that grain boundary traps play a more important role than any other parameter. The trap density should be uniform and this requirement becomes severe as the operating voltage is scaled down. It is, however, very difficult to control the grain boundary characteristics of poly-Si TFTs. We propose a robust design method as an indirect but cost-effective solution to parameter fluctuation, based on the Taguchi method of off-line quality control, and assure that the output performance is enhanced without varying the fabrication conditions. © 1998 John Wiley & Sons, Ltd.     

Formation of polycrystalline thin-film transistors with stacked poly-SiGe/poly-Si channel layer for low-voltage applications

A thin-film transistor (TFT) with polycrystalline SiGe/Si stacked channel layer has been proposed for low-voltage applications. For the stacked poly-SiGe/poly-Si channel layer, the resultant 1-μm TFT device can achieve an on/off current ratio above 7 orders and a relatively large on-state current at a low operating voltage, and also cause better transfer characteristics than both the conventional poly-Si and poly-SiGe channel layers. As compared to the poly-Si channel layer, the poly-SiGe channel layer may cause a larger on-state current at a small gate bias of 3 V, due to smaller difference between conduction band and intrinsic level. However, even at a small drain bias of 3 V, the poly-SiGe channel layer leads to an off-state leakage current of about 2 order larger than the poly-Si channel layer, since a smaller energy bandgap may cause more carrier field emission via trap states. As a result, when a poly-SiGe/poly-Si stacked channel layer is employed, the leakage current may be suppressed to a low level as that for the poly-Si channel layer, and the resultant on-state current at a low gate bias voltage can be close to a relatively high level as that for the poly-SiGe channel layer.     

Investigation on indium concentration dependence of solution processed indium tin oxide thin film transistors

The effect of the indium content in indium tin oxide (ITO) films fabricated using a solution-based process and ITO channel thin film transistors (TFTs) was examined as a function of the indium mole ratio. The carrier concentration and resistivity of the ITO films could be controlled by the appropriate treatments. The TFTs showed an increase in the off-current due to the enhanced conductivity of the ITO channel layer with increasing indium mole ratios, producing an increase in the field effect mobility. The characteristics of the a-ITO channel TFT showed the best performance (μ_FE of 3.0 cm² V^− 1 s^− 1, V_th of 2.0 V, and S value of 0.4 V/decade) at In:Sn = 5:1.     

Thin film transistors by solution-based indium gallium zinc oxide/carbon nanotubes blend

Solution-based indium gallium zinc oxide (IGZO)/single-walled carbon nanotubes (SWNTs) blend have been used to fabricate the channel of thin film transistors (TFTs). The electrical characteristics of the fabricated devices were examined. We found a low leakage current and a higher on/off currents ratio for TFT with SWNTs compared to solution-based TFTs made without SWNTs. The saturation field effect mobility (μ_sat) of about 0.22 cm²/Vs, the current on/off ratio is ~ 10⁵, the subthreshod swing is ~ 2.58 V/decade and the threshold voltage (V_th) is less than − 2.3 V. We demonstrated that the solution-based blend active layer provides the possibility of producing higher performance TFTs for low-cost large area electronic and flexible devices.     

High-Performance and Reliable Lead-Free Layered-Perovskite Transistors

Perovskites have been intensively investigated for their use in solar cells and light-emitting diodes. However, research on their applications in thin-film transistors (TFTs) has drawn less attention despite their high intrinsic charge carrier mobility. In this study, the universal approaches for high-performance and reliable p-channel lead-free phenethylammonium tin iodide TFTs are reported. These include self-passivation for grain boundary by excess phenethylammonium iodide, grain crystallization control by adduct, and iodide vacancy passivation through oxygen treatment. It is found that the grain boundary passivation can increase TFT reproducibility and reliability, and the grain size enlargement can hike the TFT performance, thus, enabling the first perovskite-based complementary inverter demonstration with n-channel indium gallium zinc oxide TFTs. The inverter exhibits a high gain over 30 with an excellent noise margin. This work aims to provide widely applicable and repeatable methods to make the gate more open for intensive efforts toward high-performance printed perovskite TFTs.     

Stability and high-frequency operation of amorphous In-Ga-Zn-O thin-film transistors with various passivation layers

The stability of amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) was investigated focusing on the effects of passivation layer materials (Y₂O₃, Al₂O₃, HfO₂, and SiO₂) and thermal annealing. Positive bias constant current stress (CCS), negative bias stress without light illumination (NBS), and negative bias light illumination stress (NBLS) were examined. It was found that Y₂O₃ was the best passivation layer material in this study in terms of all the stability tests if the channel was annealed prior to the passivation formation (post-deposition annealing) and the passivation layer was annealed at ≥ 250 °C (post-fabrication annealing). Post-fabrication thermal annealing of the Y₂O₃ passivation layer produced very stable TFTs against the CCS and NBS stresses and eliminated subgap photoresponse up to the photon energy of 2.9 eV. Even for NBLS with 2.7 eV photons, the threshold voltage shift is suppressed well to − 4.4 V after 3 h of test. These results provide the following information; (i) passivation removes the surface deep subgap defects in a-IGZO and eliminates the subgap photoresponse, but (ii) the bulk defects in a-IGZO should be removed prior to the passivation process. The Y₂O₃-passivated TFT is not only stable for these stress conditions, but is also compatible with high-frequency operation with the current gain cut-off frequency of 91 kHz, which is consistent with the static characteristics.     

The role of structural defects and texture variability in the performance of poly-Si thin film transistors

High-performance poly-Si Thin Film Transistors (TFTs) with champion mobility and threshold voltage characteristics have been reported by several groups in the literature. Performance improvements have been especially spectacular after the wide acceptance of laser-based, lateral crystallization technology and its numerous variants. Despite the noted improvements in average transistor performance, variation in TFT characteristics still presents substantial difficulties to control. Speculation on the cause of the variation has been provided by various sources but, so far, no systematic study has been performed to that effect. In this work we have conducted an extensive study of characteristics of poly-Si TFTs, fabricated by laser crystallization, and their relationship to the microstructural details of the active layer. Our study clarifies the effect of a single grain boundary inclusion in the device channel and pinpoints the key causes of variation in performance even in the absence of “hard” boundaries. The existence of structural defects, as well as texture variation, is found to correlate well with the observed variability in TFT mobility and threshold voltage. These findings have also been confirmed by a simple quantitative model. Our work points to the importance in achieving consistent microstructure and the difficulty in doing so by employing blanket crystallization technologies. To that end, crystallization technology emphasizing location control appears to be preferable.     

Zinc cadmium oxide thin film transistors fabricated at room temperature

Zinc cadmium oxide (ZnCdO) transparent thin film transistors (TFTs) have been fabricated with a back-gate structure using highly p-type Si (001) substrate. For the active channel, 30 nm, 50 nm, and 100 nm thick ZnCdO thin films were grown by pulsed laser deposition. The ZnCdO thin films were wurtzite hexagonal structure with preferred growth along the (002) direction. All the samples were found to be highly transparent with an average transmission of about 80%~ in the visible range. We have investigated the change of the performance of ZnCdO TFTs as the thickness of the active layer is increased. The carrier concentration of ZnCdO thin films has been confirmed to be increased from 10¹⁶ to 10¹⁹ cm⁻³ as the film thickness increased from 30 to 100 nm. Base on this result, the ZnCdO TFTs show a thickness-dependent performance which is ascribed to the carrier concentration in the active layer. The ZnCdO TFT with 30 nm active layer showed good off-current characteristic of below ~ 10¹¹, threshold voltage of 4.69 V, a subthreshold swing of 4.2 V/decade, mobility of 0.17 cm²/V s, and on-to-off current ratios of 3.37 × 10⁴.     

Analysis of carrier modulation in channel of ferroelectric-gate transistors having polar semiconductor

We have been fabricated and characterized a ferroelectric-gate thin-film transistors (TFTs) using ZnO as a channel polar semiconductor and YMnO₃ as a ferroelectric gate. A typical n-channel transistor property showing clear drain current saturation in I_D-V_D (drain current - drain voltage) characteristics was recognized. When the 3 V of the gate voltage is applied under the 4 V of drain voltage, the large drain current of about 1.1 mA is obtained. These controlled-polarization-type ferroelectric-gate TFTs using ZnO-channel TFTs operate in the accumulation-depletion mode and the ON/OFF state of the ferroelectric-gate TFTs strongly depends on the polarization switching of P_SFe. In this paper, therefore, the polarization switching of P_SFe in the TFT is carefully examined and the relationship between the polarization switching and the carrier accumulation (depletion) state is discussed using impedance spectroscopy and Capacitance-Voltage (C-V) measurements at applied the gate voltage.     

Amorphous structure and electrical performance of low-temperature annealed amorphous indium zinc oxide transparent thin film transistors

The effect of low-temperature (200 °C) annealing on the threshold voltage, carrier density, and interface defect density of amorphous indium zinc oxide (a-IZO) thin film transistors (TFTs) is reported. Transmission electron microscopy and x-ray diffraction analysis show that the amorphous structure is retained after 1 h at 200 °C. The TFTs fabricated from as-deposited IZO operate in the depletion mode with on-off ratio of > 10⁶, sub-threshold slope (S) of ~ 1.5 V/decade, field effect mobility (μ_FE) of 18 ± 1.6 cm²/Vs, and threshold voltage (V_Th) of − 3 ± 0.7 V. Low-temperature annealing at 200 °C in air improves the on-current, decreases the sub-threshold slope (1.56 vs. 1.18 V/decade), and increases the field effect mobility (μ_FE) from 18.2 to 23.3 cm²/Vs but also results in a V_Th shift of − 15 ± 1.1 V. The carrier density in the channel of the as-deposited (4.3 × 10¹⁶ /cm³) and annealed at 200 °C (8.1 × 10¹⁷ /cm³) devices were estimated from test-TFT structures using the transmission line measurement methods to find channel resistivity at zero gate voltage and the TFT structures to estimate carrier mobility.     

Improvement in the negative bias temperature stability of ZnO based thin film transistors by Hf and Sn doping

We assessed the performance of ZnO TFTs using Si₃N₄ gate dielectrics after various treatments. A remarkable improvement in the transfer characteristics was obtained for the O₂ plasma treated ZnO TFT and SiO₂ interlayer deposited ZnO TFT. Also, we developed amorphous hafnium-zinc-tin oxide (HZTO) thin film transistors (TFTs) and investigated the influence of hafnium (Hf) doping on the electrical characteristics of the hafnium-zinc oxide (HZO) thin film transistors. Doping with Hf can decrease the carrier concentration, which may result from a decrease of the field effect mobility, and reduce oxygen vacancy related defects in the interfacial layer. Adding tin (Sn) can suppress the growth of a crystalline phase in the HZTO films. The HZTO TFTs exhibited good electrical properties with a field effect mobility of 14.33 cm²/Vs, a subthreshold swing of 0.97 V/decade, and a high I_ON/OFF ratio of over 10⁹.