一种集成运放输入级用高性能PJFET设计

通过使用肖克莱沟道近似理论和TCAD工具设计了一种可以应用于集成运放输入级的高压超浅结PJFET结构。采用Bi-FET兼容工艺,制作出了顶栅结深约0.1µm,栅漏电小于5pA,击穿电压大于80V,夹断电压在0.8～2.0V范围可调的PJFET。将该类器件及其兼容工艺用于某型号高输入阻抗JFET集成运放的设计与制造,获得了小于50PA的偏置电流,电压噪声小于50nV/Hz1/2,电流噪声小于0.05pA/Hz1/2。     

高性能结型场效应对管及其在ASIC中的应用

采用结型场效应管作为输入级的专用集成电路,一般都具有高速宽带以及高输入阻抗的特点。场效应管与双极型器件相结合,已成为新型专用型集成运算放大器的主要发展方向之一。国内在这些专用集成电路的研制工作中所面临的主要困难,是高耐压高频结型场效应对管的工艺制作。本文在介绍高性能结型场效应对管在ASIC中的应用及其工艺试验情况。     

亚微米栅长的高速大功率GaInAsP/InP结型场效应晶体管

<正> 由于激光二极管与驱动电路的单片集成能除去不希望有的谐振或限制带宽的寄生元件,所以人们对此工艺很感兴趣。在高比特率的系统中,GaInAsP/InP激光二极管被广泛用作高速光源,因此,值得研究一下用与InP晶格匹配的材料制作晶体管的可行性。最近广泛地研究了InP衬底上制作的结型场效应晶体管(JFET),并采用如GaInAs那样的高电子迁移率材料以及采用短栅长(1μm)结构来改进晶体管的性能。日本富士通实验室采用液相外延生长法成功地制作出大功率、高速GaInAsP/InP JFET,在这种器件中由于采用了短栅制作工艺,所以得到的跨导较高(160mS/mm),电流截止     

实现高压双极器件与I~2L器件单片兼容的最简单技术

本文讨论3.2×3.4mm~2的CVSD芯片内双极高压模拟器件与I~2L逻辑器件单片兼容的技术。该工艺采用在常规p-n结隔离双极IC基础上只增加一步深N~+扩散实现兼容,它是目前最简单的工艺方案。芯片采用5μ技术,集成286个元器件。除高压双极器件(BV_(ceo)≥25伏,β≥120)及I~2L注主逻辑单元器件外,还集成特殊结构二极管、扩散电阻、硼注入电阻及MOS电容等。本文侧重讨论高压双极器件晶体管与I~2L注入逻辑晶体管的参数匹配及工艺兼容,分析了p-n-p晶体管的小电流工作状态及器件结构、工艺的最佳化设计。同时对大阻值高精度的硼离子注入电阻的制作和修正技术也进行了讨论。还对影响电路参数的双层介质MOS电容的容量控制进行了分析。最后提出元器件的单片兼容结构及工艺方案,     

增益连续可调宽带前置放大电路设计与实现

针对数字示波表等仪器对前置通道的高性能要求,文中采用程控增益运算放大器作为核心器件,设计并实现了一种宽带前置放大电路。采用单片J-FET型宽带运放作为电路的输入级,与传统设计方法相比,在提高输入阻抗同时简化了电路结构。采用高精度数模转换器控制程控增益运算放大器灵活地实现了信号的放大功能。实验结果表明,所设计的放大电路工作稳定可靠,其-3dB带宽在各个量程下均高于120MHz,增益在-50dB到40dB范围内连续可调。     

高速单片集成运算放大器

本文列出了最新高速单片运算放大器典型样品的电性能参数。利用新型的工艺和电流反馈的设计方法,制造出了低成本和高性能的单片集成运算放大器。描述了低压工艺、高压工艺和互补工艺等对单片集成运算放大器性能的影响。对电流反馈设计技术的优点和缺点进行了比较,并指出了在集成运放应用中应注意的问题。     

一种高性能InP基谐振隧穿二极管的研制

设计并用分子束外延技术生长了InP基InGaAs/AlAs体系RTD材料,采用传统湿法腐蚀、光学接触式光刻、金属剥离、台面隔离和空气桥互连工艺,研制出了具有优良负阻特性和较高阻性截止频率的InP基RTD单管，器件正向PVCR为17.5,反向PVCR为28,峰值电流密度为56kA/cm^2,采用RNC电路模型进行数据拟合后得到阻性截止频率为82.8GHz，实验为今后更高性能RTD单管的研制,以及RTD与其他高速高频三端器件单片集成电路的设计与研制奠定了基础。     

不用p-n-p管的IC电压调节器的设计技术

本文将讨论不用p-n-p晶体管的IC电压调节器的新设计技术。包括的内容有,简要地讨论在电压调节器中常用作分流器件的p-n-p管的有关问题以及去掉这种p-n-p分流器件的两种方法。第一种方法适用于非温度补偿的电压调节器,这是一种降低调节器对电源变化的灵敏度的方法,它利用“φ对消”技术代替p-n-p分流器件,这种方法将极大地改进调节器的电压跟踪。讨论的第二种方法是具有温度补偿的带隙基准电压调节器,也不用p-n-p管,它采用差分放大器来维持跟踪晶体管中的电流相等。结果表明,去掉p-n-p器件使设计的自由度更大,并减少了设计对工艺变化的敏感性。     

微波单片集成电路进展

一、单片集成电路的优势和应用预测半导体集成电路开创了电子技术的新时代.1975年以来,GaAs单片集成电路开始振兴.它的振兴得力于几个重要因素,首先是得力于GaAs材料和器件工艺的进展,GaAs场效应晶体管的平面结构和电路多用性,以及GaAs单片电阻率可达10~8Ω.cm的半绝缘衬底特性,为单片上的有源与无源单元兼容提供了有利条件.单片集成打破了有源与无源元件的工艺界限,器件或电路均按预定计划作为整个工艺流程的某     

SiGe层中载流子迁移率研究简况

近些年来的研究结果认为,用Si_(1-x)Ge_x伪晶作成的异质结晶体管是采用硅工艺制作的高速高频器件的最大竞争对手。它的发展速度很快,在很短的时间内就从实验室内的珍品发展成为以硅工艺为基础的速度最快的双极晶体管,不仅设计制成了n-p-n和p-n-p管,而且制成了Si_(1-x)Ge_x伪晶异质结晶体管(PHBT)的集成电路,并获得满意的结果。采用二维漂移扩散(DD)模拟和一维流体学模拟(HD)来分析这类晶体管的高频性能,证明它们的f_r为70GHz左右。     

Vertical p-n-p for complementary bipolar technology

A process to fabricate high-performance vertical p-n-p devices has been developed. The use of a high-dose boron-implanted poly-Si layer to form the emitter is essential to obtain shallow emitters with high emitter gradient. The devices exhibit very high current gain (>200) and a calculated cutoff frequency of 3.6 GHz. The process as developed is compatible with the n-p-n process and, thus, suitable for fabrication of complementary bipolar devices.     

Vertical p-n-p for Complementary Bipolar Technology

A process to fabricate high-performance vertical p-n-p devices has been developed. The use of a high-dose bolon-implanted poly-Si layer to form the emitter is essential to obtain shallow emitters with high emitter gradient. The devices exhibit very high current gain (>200) and a calculated cutoff frequency of 3.6 GHz. The process as developed is compatible with the n-p-n process and, thus, suitable for fabrication of complementary bipolar devices.     

IC storage and access circuitry for an injection electroluminescent diode display

The design of a monolithic IC that is packaged in a hybrid assembly with a linear array of 32 light-emitting diodes to form a basic building block for LED panel display is discussed. The functions of the IC are buffering, inverting, decoding, driving, controlling, LED current regulation, storage, power gating, and lead reduction. Storage is provided by a two- transistor latch that is fabricated in monolithic form using a lateral p-n-p and vertical n-p-n. The random access time between elements in the array is 180 ns for turn-on and 100 ns for turn-off. The IC inputs are compatible with DTL and T/SUP 2/L input levels and the LED output brightness is adequate for viewing in room light.     

High-gain lateral p-n-p bipolar action in a p-MOSFET structure

Lateral p-n-p bipolar junction transistors (BJTs) fabricated using a bulk 0.25 μm CMOS technology are presented. The devices are structurally the same as p-MOSFETs in which the gate and the n-well are internally connected to form the base. The p-n-p BJT has an adjustable current gain which can be higher than 1000 and its peak cutoff frequency is 3.7 GHz. Since the lateral p-n-p BJT is fully process compatible with submicrometer CMOS and/or BiCMOS technologies, extension to a BiCMOS and/or complementary BiCMOS process is readily achieved     

The design and optimization of high-performance, double-polyself-aligned p-n-p technology

The device design and performance of double-poly self-aligned p-n-p technology, featuring a low-resistivity p⁺ subcollector, thin p-epi, and boron-doped poly-emitter are described. Device isolation is provided by deep and shallow trenches which reduce the collector-to-substrate capacitance while maintaining a high breakdown voltage (⩾40 V). By utilizing a shallow emitter process in conjunction with an optimized arsenic-base implant, devices with emitter-base junction depths as shallow as 20 nm and base widths of less than 100 nm were obtained. Cutoff frequencies of up to 27 GHz were obtained, and the AC performance was demonstrated by an NTL-gate delay of 36 ps and an active-pull-down (APD) ECL-gate delay of 20 ps. This high-performance p-n-p technology was developed to be compatible with existing double-poly n-p-n technologies. The matching speed of p-n-p devices opens up new opportunities for high-performance complementary bipolar circuits     

Comparison of input offset voltage of differential amplifiers using bipolar transistors and field-effect transistors

A field-effect transistor (whether junction type or MOS type) has very high input impedance. For those who desire to achieve a higher input impedance, it is often asked `Why aren't FET pairs used as input stages and bipolar transistors used as output stages, since compatible FET and bipolar transistor monolithic structures have been developed?' This correspondence is a study of this question.     

AC coupled three op-amp biopotential amplifier with active DC suppression

A three op-amps instrumentation amplifier (I.A) with active dc suppression is presented. dc suppression is achieved by means of a controlled floating source at the input stage, to compensate electrode and op-amps offset voltages. This isolated floating source is built around an optical-isolated device using a general-purpose optocoupler, working as a photovoltaic generator. The proposed circuit has many interesting characteristics regarding simplicity and cost, while preserving common mode rejection ratio (CMRR) and high input impedance characteristics of the classic three op-amps I.A. As an example, a biopotential amplifier with a gain of 80 dB, a lower cutoff frequency of 0.1 Hz, and a dc input range of +/- 8 mV was built and tested. Using general-purpose op-amps, a CMRR of 105 was achieved without trimmings.     

高性能纵向pnp晶体管的研制

pnp晶体管中由于空穴的迁移率较电子的迁移率低得多,再加上纵向pnp管有比npn管严重得多的基区宽度调变效应,一般情况下,难以使纵向pnp管的性能与npn管的性能相媲美。我们从理论上分析了提高纵向pnp管性能的途径,并设计了一套新的工艺流程。在p型外延材料上研制出了BV_(ceo)≥90V、V_(be)≤0.8V、f_T=900MHz、V_(ces)=0.2V、β=60～150、厄利电压大于150V的纵向pnp晶体管。在P型单晶材料上研制出了BV_(ceo)≥65V、f_T≥560MHz、β=60～150的纵向pnp晶体管。具有这种性能的纵向pnp管目前在国内外还很少见。     

A BiCMOS technology with 660-MHz vertical p-n-p transistor foranalog/digital ASICs

A fully complementary BiCMOS technology based on a 2-μm process designed for 12-V analog/digital applications is described. In this technology, a triple diffused vertical p-n-p transistor and n-p-n bipolar and CMOS devices are integrated in a single chip. A transition frequency of 660 MHz and a collector-to-emitter breakdown voltage of over 15 V have been obtained for the collector-isolated p-n-p transistor by adding only one extra mask to a conventional 2-μm BiCMOS process. The total number of masks is 20 with double-layer metallization. A unity gain frequency of 52 MHz and a DC gain of 85 dB have been obtained for a single-supply operational amplifier with a vertical p-n-p first stage. The propagation delay time for a CMOS two-NAND gate was 1.27 ns driving three loads and 3 mm of metal     

Integrated direct-coupled gyrator

An integrated gyrator is described. The device uses 1 diode, 12 resistors and 9 transistors, two of which are lateral p-n-p. Experimental results on gyration resistance, input impedance and resonant-circuit Q factor show excellent agreement with theory.