一种获得四管CMOS图像传感器像素夹断电压的方法

提出了一种测试四管CMOS图像传感器像素夹断电压的方法。该方法是基于像素中势阱结构的变化能够对图像信号散粒噪声产生影响的假设。实验结果测得的夹断电压与理论预测相一致。该技术提供的实验方法不仅能够帮助设计四管CMOS图像传感器光电二极管的结构,而且也能优化像素生产工艺。     

Two-dimensional pixel image lag simulation and optimization in a 4-T CMOS image sensor

Pixel image lag in a 4-T CMOS image sensor is analyzed and simulated in a two-dimensional model.Strategies of reducing image lag are discussed from transfer gate channel threshold voltage doping adjustment,PPD N-type doping dose/implant tilt adjustment and transfer gate operation voltage adjustment for signal electron transfer.With the computer analysis tool ISE-TCAD,simulation results show that minimum image lag can be obtained at a pinned photodiode n-type doping dose of 7.0×10~(12) cm~(-2),an implant ...     

Sensitivity Controllable CMOS Image Sensor Pixel Using Control Gate Overlaid on Photodiode

A new sensitivity controllable pixel structure is proposed for CMOS active-pixel image sensor. The proposed pixel structure has a sensitivity control gate overlaid on the photodiode. The sensitivity of the pixel is controlled by the bias voltage of the control gate that forms a variable accumulation-mode MOS capacitor. The prototype sensor is fabricated with a 0.35-mum CMOS process and consists of 60 times 240 pixels with 5.6-mum pixel pitch. Measurement results show that the sensitivity of the photodiode can be controlled by a factor of 4.     

基于4T像素结构的CMOS图像传感器设计

传统的CMOS图像传感器采用3T像素结构,但由于自身结构的关系,整体性能难以满足较高的要求,4T像素结构应运而生,它比3T像素有更小的噪声,更好的性能;同时要求控制部分更加复杂。文中介绍了基于一种4T像素结构的图像传感器的设计。     

垂直多结PPD像素势阱容量与电荷转移研究

研究了一种具有垂直多结结构的CMOS图像传感器四管像素结构,通过引入垂直多结结构可扩展感光区的势阱容量,增大耗尽区,提高信号电荷收集效率,特别对于长波长光波的吸收大幅增加。并为减小垂直多结结构的图像拖影现象,在N区水平方向上进行梯度掺杂,消除了电位障,使得信号电荷更易向外传输,从而减小图像拖影现象,并通过SILVACO TCAD软件对该结构进行数值仿真。     

A charge pump for driving CMOS active pixel reset

To overcome the limitation of low image signal swing range and long reset time in four Iransistor CMOS active pixel image sensor, a charge pump circuit is presented to improve the pixel reset performance. The charge pump circuit consists of two stage switch capacitor serial voltage doubler. Cross-coupled MOSFET switch structure with well close and open performance is used in the second stage of the charge pump. The pixel reset transistor with gate voltage driven by output of the pump works in linear region, which can accelerate reset process and complete reset is achieved. The simulation results show that output of the charge pump is enhanced from 1.2 to 4.2 V with voltage ripple lower than 6 inV. The pixel reset time is reduced to 1.14 ns in dark. Image smear due to non-completely reset is elIminated and the image signal swing range is enlarged. The charge pump is successfully embedded in a CMOS image sensor chip with 0.3 × 10^6 pixels.     

A logarithmic response CMOS image sensor with on-chip calibration

CMOS image sensors with logarithmic response are attractive devices for applications where a high dynamic range is required. Their strong point is the high dynamic range. Their weak point is the sensitivity to pixel parameter variations introduced during fabrication. This gives rise to a considerable fixed pattern noise (FPN) that deteriorates the image quality unless pixel calibration is used. In the present work a technique to remove the FPN by employing on-chip calibration is introduced, where the effect of threshold voltage variations in pixels is cancelled. An image sensor based on an active pixel structure with five transistors has been designed, fabricated, and tested. The sensor consists of 525×525 pixels measuring 7.5 μm×10 μm, and is fabricated in a 0.5-μm CMOS process. The measured dynamic range is 120 dB while the FPN is 2.5% of the output signal range     

A novel monolithic ultraviolet image sensor based on a standard CMOS process

We present a monolithic ultraviolet(UV) image sensor based on a standard CMOS process.A compact UV sensitive device structure is designed as a pixel for the image sensor.This UV image sensor consists of a CMOS pixel array,high-voltage switches,a readout circuit and a digital control circuit.A 16×16 image sensor prototype chip is implemented in a 0.18μm standard CMOS logic process.The pixel and image sensor were measured. Experimental results demonstrate that the image sensor has a high sensitivity of 0.072 V/(mJ/cm~2) and can capture a UV image.It is suitable for large-scale monolithic bio-medical and space applications.     

一种新型大动态范围CMOS图像传感器

提出了一种具有新型像素结构的大动态范围CMOS图像传感器,通过调整单个像素的积分时间来自适应不同的局部光照情况,从而有效提高动态范围。设计了一种低延时、低功耗、结构简单的新型pixel级电压比较器及基于可逆计数器的时间-电压编码电路。采用0.6μm DPDM标准数字CMOS工艺参数对大动态范围像素单元电路进行仿真,积分电容电压Vcint与光电流呈良好的线性关系,其动态范围可达126dB。在3.3V供电电压下,单个像元功耗为2.1μW。     

A 1.9 $e^{-}$ Random Noise CMOS Image Sensor With Active Feedback Operation in Each Pixel

A 1.9 e^- random noise CMOS image sensor has been developed by applying an active feedback operation (AFO), which uses a capacitive feedback effect to floating diffusion (FD) by a gate-source capacitance of a pixel source follower (SF), in a CMOS image sensor with a lateral overflow integration capacitor (LOFIC) technology. It is described that the AFO is suitable for CMOS image sensors with LOFIC because the design of the full well capacity and the FD can be independently optimized. The AFO theory is found to be explored to a large signal voltage in detail, as well as the conventional analysis of the capacitive feedback effect of the pixel SF for a small signal voltage. A 1/4-in 5.6- mum-pitch 640(H) times 480(V) pixel sensor chip in a 0.18-mum two-poly-Si three-metal CMOS technology achieves about 1.7 times the sensitivity with AFO compared with the case where the feedback operation is not positively used, resulting in an input-referred conversion gain of 210 muV/e^- and an input-referred noise of 1.9 e^-. A high well capacity of 130 000 e^- is also achieved.     

A 120-dB Dynamic Range CMOS Image Sensor With Programmable Power Responsivity

A high dynamic range CMOS image sensor providing a user-programmable power responsivity curve is presented. Each pixel integrates, besides a 4T active pixel structure, a voltage comparator and an analog memory to implement a time-to-saturation scheme while also providing the standard integrated photo-current signal. The sensor generates two 10-bit analog outputs allowing a typical dynamic range exceeding 120 dB with a temporal noise lower than 0.13% and a fixed pattern noise of 0.4% (1.7%) of the total signal swing (2 V) at low (high) irradiance without any external calibration procedures. A 140 times 140-pixel array has been fabricated in a 0.35-mum, two-poly four-metal (2P4M), 3.3-V standard CMOS technology. The chip measures 3.9 times 4.6 mm² with a pixel pitch of 15 mum and a fill factor of 20%.     

低照度CMOS图像传感器设计与实现

设计了一种基于电容反馈跨阻放大器型（Capacitive Trans-impedance Amplifier,CTIA）像元电路与双采样（Delta Double Sampling,DDS）的低照度CMOS图像传感器系统。采用CTIA像元电路提供稳定的光电二极管偏置电压以及高注入效率,完成在低照度情况下对微弱信号的读取;同时采用数字DDS结构,通过在片外实现像元积分信号与复位信号的量化结果在数字域的减法,达到抑制CMOS图像传感器中固定图案噪声的目的,进一步提高低照度CIS的成像质量。基于0.35 m标准CMOS工艺对此基于CTIA像元电路的CMOS图像传感器芯片进行流片,像元阵列为256256,像元尺寸为16 m16 m。测试结果表明该低照度CMOS图像传感器系统可探测到0.05 lx光照条件下的信号。     

包含交流耦合CTIA与数字CDS的CMOS图像传感器设计

设计了一种带隔直电容的交流耦合CTIA像元电路与数字相关双采样（DCDS）结构的CMOS图像传感器系统。在传统的CTIA像元电路中增加隔直电容,通过控制光电二极管的偏压,达到减小光电二极管暗电流的目的;同时采用片外数字CDS结构,通过在片外实现复位信号与像元积分信号的量化结果在数字域的减法,可以减小图像传感器像元的复位噪声和固定图案噪声（FPN）。基于0.35 m标准CMOS工艺对此CMOS图像传感器进行流片,像元阵列为256256,像元尺寸为16 m16 m。测试结果表明交流耦合CTIA像元电路可以将光电二极管的偏压控制在零偏点附近,此时其暗电流最小;采用了数字CDS结构后,图像传感器像元的时域噪声及固定图案噪声均有不同程度降低。     

High speed SOI CMOS image sensor with pinned photodiode on handle wafer

We have fabricated SOI CMOS active pixel image sensor with pinned photodiode on handle wafer. The structure of one pixel is a four-transistor type active pixel image sensor, which consists of a reset and a source follower transistor on seed wafer, and is comprised of a photodiode, a transfer gate, and a floating diffusion on handle wafer. The photodiode could be optimized for better quantum efficiency and low dark currents because the process of a photodiode on handle wafer is independent of that of transistors on seed wafer. Most of the wavelengths are absorbed within the visible range, because the optimized photodiode is located on the handle wafer. The response time of SOI CMOS active pixel sensor was about 2 times faster than that of bulk CMOS active pixel image sensor.     

A 1.5-V 550-/spl mu/W 176/spl times/144 autonomous CMOS active pixel image sensor

This paper addresses the development of a micropower 176/spl times/144 CMOS active pixel image sensor that dissipates one to two orders of magnitude less power than current state-of-the-art CMOS image sensors. The chip operates from a 1.5-V voltage source and the power consumption measured for the chip running from an internal 25.2-MHz clock yielding 30 frames per second is about 550 /spl mu/W. This amount enables the sensor to run from a watch battery. In order to achieve design goals, a low-power sensor design methodology is applied throughout the design process from system-level to process-level, while realizing the performance to satisfy the design specification. As an autonomous sensor, it can be operated with only three pads [GND, VDD (1.2-1.7 V), DATAOUT]. The die occupies 4 mm/sup 2/ of silicon.     

An Improved Global Shutter Pixel with Extended Output Range and Linearity of Compensation for CMOS Image Sensor

An improved global shutter pixel structure with extended output range and linearity of compensation is proposed for CMOS image sensor. The potential switching of the sample and hold capacitor bottom plate outside the array is used to solve the problem of the serious swing limitation, which will attenuate the dynamic range of the image sensor. The non-linear problem caused by the substrate bias effect in the output process of the pixel source follower is solved by using the mirror FD point negative feedback self-establishment technology outside the array. The approach proposed in this paper has been verified in a global shutter CMOS image sensor with a scale of 1024×1024 pixels. The test results show that the output range is expanded from 0.95V to 2V, and the error introduced by the nonlinearity is sharply reduced from 280mV to 0.3mV. Most importantly, the output range expansion circuit does not increase the additional pixel area and the power consumption. The power consumption of linearity correction circuit is only 23.1μW, accounting for less than 0.01％ of the whole chip power consumption.     

High-sensitivity and no-crosstalk pixel technology for embeddedCMOS image sensor

A high-photosensitivity and no-crosstalk pixel technology has been developed for an embedded active-pixel CMOS image sensor, by using a 0.35-μm CMOS logic process. To increase the photosensitivity, we developed a deep p-well photodiode and an antireflective film, consisting of Si₃N₄ film, for the photodiode surface. To eliminate the high voltage required for the reset transistor in the pixel, we used a depletion-type transistor as the reset transistor. The reset transistor also operates as an overflow control gate, which enables antiblooming overflow when excess charge is generated in the photodiode by high-illumination conditions. To suppress pixel crosstalk caused by obliquely incident light, a double-metal photoshield was used, while crosstalk caused by electron diffusion in the substrate was suppressed by using the deep p-well photodiode. A 1/3-in 330-k-pixel active-pixel CMOS image sensor was fabricated using this technology. A sensitivity improvement of 110% for 550-nm incident light was obtained by using the deep p-well photodiode, while an improvement of 24% was obtained by using the antireflective film. The pixel crosstalk was suppressed to less than 1% throughout the range of visible light     

一种6T像素全局曝光CMOS图像传感器

提出了一种基于6T像素结构的全局曝光CMOS图像传感器。通过采用PPD结构的6T像素、高复位电平和低阈值器件,提高了动态范围,并优化设计了像素单元的版图,使之获得较高的填充系数;模拟读出电路部分,通过采用双采样、增益放大和减小列级固定模式噪声(FPN)处理,以及对列选控制电路进行优化,减小了对全局PGA的运放设计要求。芯片的工作频率为20MHz,动态范围为66dB,实现了全局曝光方式CMOS图像传感器的设计。     

A wide dynamic range CMOS PFM digital pixel sensor with in-pixel variable voltage reference

This paper proposes a new pulse-frequency-modulation (PFM) digital pixel sensor (DPS) with a variable reference voltage. An in-pixel variable reference voltage generator is employed to ramp the reference voltage of the comparator locally such that the comparison of photo diode current and the reference voltage can take place earlier. This expands the dynamic range of the pixel sensor when the level of illumination is low. The complexity of routing of the proposed pixel sensor are comparable to that of digital pixel sensor with a constant reference voltage. The additional hardware cost of the proposed digital pixel sensor is only a capacitor and two static inverters, resulting in a fill factor that is comparable to those of digital pixel sensors with a constant global reference voltage. Factors that are critically to the performance of the proposed pixel sensor are examined in detail. The proposed digital pixel sensor has been designed in TSMC-0.18 μm 1.8 V CMOS technology and analyzed using Spectre with BSIM3V3 device models. Simulation results demonstrate that the proposed PFM digital pixel has a dynamic range of 120 dB when the integration time is set to 60 μs, approximately 40 dB more than the corresponding PFM digital pixel sensor with a constant reference voltage. The fill factor of the proposed pixel sensor is 20%, comparable to that of pixel sensors with a constant reference voltage.     

A sensitivity and linearity improvement of a 100-dB dynamic range CMOS image sensor using a lateral overflow integration capacitor

In a CMOS image sensor featuring a lateral overflow integration capacitor in a pixel, which integrates the overflowed charges from a fully depleted photodiode during the same exposure, the sensitivity in nonsaturated signal and the linearity in saturated overflow signal have been improved by introducing a new pixel circuit and its operation. The floating diffusion capacitance of the CMOS image sensor is as small as that of a four transistors type CMOS image sensor because the lateral overflow integration capacitor is located next to the reset switch. A 1/3-inch VGA format (640/sup H//spl times/480/sup V/ pixels), 7.5/spl times/7.5 /spl mu/m/sup 2/ pixel color CMOS image sensor fabricated through 0.35-/spl mu/m two-poly three-metal CMOS process results in a 100 dB dynamic range characteristic, with improved sensitivity and linearity.