A timing controller embedded driver IC with 3.24‐Gbps eDP interface for chip‐on‐glass TFT‐LCD applications

This paper presents a timing controller embedded driver (TED) IC with 3.24‐Gbps embedded display port (eDP), which is implemented using a 45‐nm high‐voltage CMOS process for the chip‐on‐glass (COG) TFT‐LCD applications. The proposed TED‐IC employs the input offset calibration scheme, the zero‐adjustable equalizer, and the phase locked loop‐based bang‐bang clock and data recovery to enhance the maximum data rate. Also, the proposed TED‐IC provides efficient power management by supporting advanced link power management feature of eDP standard v1.4. Additionally, the smart charge sharing is proposed to reduce the dynamic power consumption of output buffers. Measured result demonstrates the maximum data rate of 3.24 Gbps from a 1.1 V supply voltage with a 7.9‐inch QXGA 60‐Hz COG‐LCD prototype panel and 44% power saving from the display system.     

A novel low‐power gate driver architecture for large 8 K 120 Hz liquid crystal display employing IGZO technology

A novel low‐power gate driver architecture was developed for large 8 K 120 Hz liquid crystal display panel. For this application, not only high‐speed driving but also low power consumption is required. We employed a high mobility In‐Ga‐Zn‐O, dual V_GL level driving method, and gate driver circuit driven by DC supply. The simulation results show that our proposals meet 8 K 120 Hz driving requirements. Also, we have fabricated a prototype panel and confirmed both high‐speed driving and low power consumption.     

A reduced‐voltage differential signaling (RVDS) interface for chip‐on‐glass TFT‐LCD applications

Abstract— Reduced‐voltage differential signaling (RVDS) is a novel interface for TFT‐LCD panels with a chip‐on‐glass (COG) structure, which has a point‐to‐point topology and a voltage mode differential signaling scheme. The voltage‐driving interface scheme has advantages in high‐speed operation owing to its relatively small time constant for the resistive channel condition. And reduced‐voltage signaling can reduce the power consumption of a transmitter. The display source driver IC with an RVDS interface, which is fabricated by using a 0.25‐μm CMOS process with a 2.5‐V logic supply voltage, offers a high data rate up to 500 Mbps, low‐current consumption of 2.2 mA, and good EMI characteristics. Also, an RVDS interface has programmable options that control the bandwidth, system power, and EMI performance. Therefore, the RVDS interface is a competitive solution for low‐power, low‐cost, and slim notebook applications.     

Digital time‐modulation pixel memory circuit in LTPS technology

Abstract— A digital time‐modulation pixel memory circuit on glass substrate has been designed and verified for a 3‐μm low‐temperature polysilicon (LTPS) technology. From the experimental results, the proposed circuit can generate 4‐bit digital codes and the corresponding inversion data with a time‐modulation technique. While the liquid‐crystal‐display (LCD) panel operates in the still mode, which means the same image is displayed on the panel, a data driver for an LCD panel is not required to provide the image data of the frame by the proposed pixel memory circuit. This pixel memory circuit can store the frame data and generate its corresponding inversion data to refresh a static image without activating the data driver circuit. Therefore, the power consumption of a data driver can be reduced in the LCD panel.     

Robust integrated shift register circuit over clock noises for in‐cell touch applications

This paper proposes an integrated shift register circuit for an in‐cell touch panel that is robust over clock noises. It is composed of 10 thin film transistors and 1 capacitor, and the time division driving method is adopted to prevent the negative effect of display signals on the touch sensing. Two pre‐charging nodes are employed for reducing the uniformity degradation of gate pulses over time. In particular, the proposed circuit connects a drain of the first pre‐charging node's pull‐up thin film transistor (TFT) to the positive supply voltage instead of clock signals. This facilitates to lower coupling noises as well as to clock power consumption. The simulation program with an integrated circuit emphasis is conducted for the proposed circuit with low temperature poly‐silicon TFTs. The positive threshold voltage that shifts up to 12 V at the first pre‐charging pull‐up TFT can be compensated for without the uniformity degradation of gate pulses. For a 60‐Hz full‐HD display with a 120‐Hz reporting rate of touches, the clock power consumption of the proposed gate driver circuit is estimated as 7.13 mW with 160 stages of shift registers. In addition, the noise level at the first pre‐charging node is lowered to ?28.95 dB compared with 2.37 dB of the previous circuit.     

Low‐power‐consumption TFT‐LCD with dynamic memory embedded in the pixels

A low‐power‐consumption thin‐film‐transistor liquid‐crystal display (TFT‐LCD) with dynamic memory cells embedded in each pixel using low‐temperature poly‐Si technology has been developed. By holding data in the memory, the operating rate of the data driver can be dramatically reduced to 4 Hz. Eight levels of gray scale with low power consumption can be achieved by using the area‐ratio gray‐scale method. This TFT‐LCD can be used for displaying fine still images, with low power consumption.     

A novel gate driver circuit for depletion‐mode a‐IGZO TFTs

In this paper, a novel gate driver circuit, which can achieve high reliability for depletion mode in a‐InGaZnO thin‐film transistors (TFTs), was proposed. To prevent the leakage current paths for Q node effectively, the new driving method was proposed by adopting the negative gate‐to‐source voltage (V_GS) value for pull‐down units. The results showed all the V_OUT voltage waveforms were maintained at VGH voltage despite depletion‐mode operation. The proposed circuit could also obtain stable V_OUT voltage when the threshold voltage for all TFTs was changed from ?6.5 to +11.5 V. Therefore, the circuit can achieve high reliability regardless of threshold voltage value for a‐IGZO TFTs. In addition, the output characteristics and total power consumption were shown for the alternating current (AC)–driven and direct current (DC)–driven methods based on 120‐Hz full‐HD graphics (1920 × 1080) display panel. The results showed that the AC‐driven method could achieve improved V_OUT characteristics compared with DC‐driven method since the leakage current path for Q node can be completely eliminated. Although power consumption of the AC‐driven method can be slightly increased compared with the DC‐driven method for enhancement mode, consumption can be lower when the operation has depletion‐mode characteristics by preventing a leakage current path for pull‐down units. Consequently, the proposed gate driver circuit can overcome the problems caused by the characteristics of a‐IGZO TFTs.     

Latest developments for “system‐on‐glass” displays using low‐temperature poly‐Si TFTs

Abstract— A 2.3‐in.‐diagonal QVGA‐formatted “System‐On‐Glass” display has been developed by using low‐temperature poly‐Si TFT‐LCD technology. This display fully integrates 6‐bit RGB digital interface drivers as well as all the power supply circuitry to drive the LCD, which requires neither external driver ICs nor power‐supply ICs. This paper discusses the newly developed TFT circuit technologies used in this LCD. The development trend of the “System‐On‐Glass” display is also reviewed.     

A small‐area and low‐power data driver IC using two‐stage DAC with a capacitor array for active matrix flat‐panel displays

A small‐area and low‐power data driver integrated circuit (IC) using a two‐stage digital‐to‐analog converter (DAC) with a capacitor array is proposed for active matrix flat‐panel displays. The proposed data driver IC employs a capacitor array in the two‐stage DAC so as to reduce the DAC area and eliminate the need for a resistor string, which has high‐power consumption. To verify the proposed two‐stage DAC, a 20‐channel data driver IC with the proposed 10‐bit two‐stage DAC was fabricated using a 0.18‐μm complementary metal–oxide–semiconductor process with 1.8 and 6 V complementary metal–oxide–semiconductor devices. The proposed 10‐bit two‐stage DAC occupies only 43.8% of the area of a conventional 10‐bit two‐stage DAC. The measurement results show that the differential nonlinearity and integral nonlinearity are +0.58/?0.52 least significant bit and +0.62/?0.59 least significant bit, respectively. The measured interchannel deviation of the voltage outputs is 8.8 mV, and the measured power consumption of the 20‐channel data driver IC is reduced to 7.1 mW, which is less than half of the power consumed by the conventional one.     

1.5Gbps高速串行数据恢复电路的标准单元实现

在高速串行接口芯片的设计中,高速串行数据恢复电路是设计中的一个难点,由于其高达千兆的传输频率,大多采用模拟电路方式实现·然而同数字电路相比,模拟电路在噪声影响、面积、功耗、工艺敏感度和可测性方面都存在较大的劣势·提出了一个应用于SATA1·0中1·5Gbps高速串行接口的高速串行数据恢复电路,它没有用PLL或DLL等模拟电路的方法,它采用完全数字电路的设计,并用标准单元实现·与用模拟电路实现的串行数据恢复电路相比,此电路设计更加简单易实现,数据恢复快速,而且面积小功耗低·电路被应用在PATA/SATA桥接芯片的设计中,并在标准0·18CMOS工艺下投片生产·     

Design of dual‐outputs‐single‐stage a‐Si:H TFT gate driver for high resolution TFT‐LCD application

A new gate driver has been designed and fabricated by amorphous silicon technology. With utilizing the concept of sharing the noise free block in a single stage for gate driver, dual‐outputs signals could be generated in sequence. By increasing the number of output circuit block in proposed gate driver, number of outputs per stage could also be adding that improves the efficiency for area reduction. Besides, using single driving thin‐film‐transistor (TFT) for charging and discharging, the area of circuit is also decreased by diminishing the size of pulling down TFT. Moreover, the proposed gate driver has been successfully demonstrated in a 5.5‐inch Full HD (1080xRGBx1920) TFT‐liquid‐crystal display panel and passed reliability tests of the supporting foundry.     

Compact and power‐saving polysilicon data driver with common‐decoder DA converter (CD‐DAC)

Abstract— A common‐decoder architecture for a data‐driver circuit fabricated by using a polysilicon process has been developed. The architecture achieves a compact circuit and low‐power consumption. In application to an integrated polysilicon data driver for small‐sized displays, this architecture reduces the area of the data driver by removing the vertical bus lines that occupy a large area. It also suppresses the power consumption of the data bus by reducing the number of driven lines in the data bus during word‐to‐word transitions from six to two. By using a conventional 4‐μm design rule, we fabricated an active‐matrix OLED (AMOLED) panel with an integrated six‐bit data‐driver circuit with 384 outputs. The driver circuit had a height of 2.6 mm and a pitch between output lines of 84 μm. The maximum power consumption of the driver was only 5 mW, i.e., 3.8 mW for logic‐data transfer and 1.2 mW for reference‐voltage source. Furthermore, we also fabricated an active‐matrix LCD (AMLCD) panel including driver circuits of the same type as the integrated elements. Six‐bit full‐color images were successfully displayed on both panels.     

Pixel‐level data‐line multiplexing for low‐cost/high‐resolution AMLCDs

Abstract— We propose a novel data‐line multiplexing technique for low‐cost/high‐resolution active‐matrix liquid‐crystal displays (AMLCDs). This scheme reduces the number of data lines and driver chips required by one‐half without enormous multiplexing circuits. Another advantage of applying this technique is the reduction in power consumption. We demonstrated the technical feasibility of this method with application prototypes up to 15‐in. SXGA+ (1400 × 1050 pixels) AMLCDs with amorphous‐silicon (a‐Si) thin‐film‐transistor (TFT) technology. In this paper, we provide an explanation of the addressing mechanism in detail and clarify the feasibility with further technical discussion.     

TFT‐LCD driver IC with embedded non‐volatile memory for portable applications

Abstract— To improve the display quality and yield of the TFT‐LCD driver IC, non‐volatile multiple‐time‐programmable (MTP) memory, which consists of an EEPROM cell and our proposed sense amplifier and power control circuit (SP), was integrated into a TFT‐LCD driver IC. The proposed SP has a 30% smaller layout area and a 18% faster response time compared to that of the conventional SP. The proposed SP also has lower power consumption because it does not use a static current. The TFT‐LCD quality was also improved by tuning the characteristics of the driver IC and the panel with the VREF, OSC, and VCOM blocks, using non‐volatile MTP memory. When the display quality improved, the yield also improved, along with a reduction in the failure ratio of the display module, which consists of the driver IC and the panel. As a result, the TFT‐LCD driver IC with the non‐volatile MTP memory demonstrated improved display quality and a higher yield compared to conventional driver ICs without such a memory.     

Ultra‐low‐power LTPS TFT‐LCD technology using a multi‐bit pixel memory circuit

Abstract— Two types of low‐temperature poly‐Si TFT LCDs, which integrate a multi‐bit memory circuit and a liquid‐crystal driver within a pixel, have been developed using two different TFT process technologies. Both a 1.3‐in. 116‐ppi LCD having a 2‐bit pixel memory and a 1.5‐in. 130‐ppi LCD having a 5‐bit pixel memory consume very little power, less than 100 μW, which indicates that this technology is promising for mobile displays.     

4级灰度STN LCD驱动控制芯片的设计

提出了一种4级灰度的STNLCD驱动控制芯片的总体设计方案,重点讨论了关键模块——接口电路、SRAM模块、显示控制电路以及电源电路的设计。在实现多种显示功能的前提下,采用省电模式、门控时钟和重定时方法进行了低功耗优化设计。基于SMIC0．35umCMOS高压模型对驱动控制芯片的功能进行了仿真验证。     

A novel low‐power‐consumption all‐digital system‐on‐glass display with serial interface

Abstract— A new conceptual ultra‐compact LCD panel, which features a simple interface and lower‐power consumption by using low‐temperature polysilicon thin‐film transistor (LTPS‐TFT) technology has been developed. This panel is capable of switching operation modes based on an input command, and all the data are directly communicated with the circuit inside the panel through a Serial Peripheral Interface (SPI) protocol. The integration of the serial‐data‐receiver function on glass substrate has enabled the achievement of a significant reduction in the number of interface pins. Moreover, a low power consumption of 15 μW for a 2.26‐in. reflective LCD panel in combination with the technique of integrating a memory circuit in each pixel has been achieved.     

A 400‐dpi reflective storage ferroelectric liquid‐crystal display for highly readable,low‐power mobile display applications

Mobile products require longer battery lifetimes and increased information content from the display. A ferroelectric liquid‐crystal reflective storage mode was demonstrated. This display only needs updating when the image changes, resulting in ultra‐low power consumption. Passive‐matrix addressing allows for high‐resolution text to be displayed.     

Low‐temperature poly‐Si TFT‐LCD with an integrated analog circuit

We have developed a 6‐bit D/A converter and amplifier integrated low‐temperature poly‐Si TFT‐LCD in which an integrated signal‐line driver is driven by a 5‐V power supply. We have employed a D/A converter including a new capacitor array and an original amplifier comprised of serially connected comparators to achieve high accuracy. The D/A converter performs gamma correction using upper significant bits of input data. Control signals for these circuits were generated by the integrated timing circuit. These advances in integration have been achieved for the first time using 3‐μm design rule and improved LTPS TFT technologies and provide an advanced display system with lower power consumption, smaller module size, and higher durability.     

Low‐temperature poly‐Si TFT data drivers for an SVGA a‐Si TFT‐LCD panel

Low‐temperature poly‐Si TFT data drivers for an SVGA a‐Si TFT‐LCD panel have been developed. The data drivers include shift registers, sample‐and‐hold circuits, and operational amplifiers, and drive LCD panels using a line‐at‐a‐time addressing method. To reduce the power consumption of the shift register, a dot‐clock control circuit has been developed. Using this circuit, the power consumption of the shift register has been reduced to 36% of that of conventional circuits. To cancel the offset voltage generated by the operational amplifier, an offset cancellation circuit for low‐temperature poly‐Si TFTs has been developed. This circuit is also able to avoid any unstable operation of the operational amplifier. Using this circuit, the offset voltage has been reduced to one‐third of the value without using the offset cancellation circuit. These data drivers have been connected to an LCD panel and have realized an SVGA display on a 12.1‐in. a‐Si TFT‐LCD panel.