A Monolithic and Self-Referenced RF LC Clock Generator Compliant With USB 2.0

A monolithic and self-referenced radio frequency (RF) LC clock generator that is compliant with USB 2.0 is demonstrated in a system-on-chip (SoC). This work presents the first successful approach to replacing an external crystal (XTAL), the crystal oscillator (XO) and the phase-locked loop for clock generation in an IC supporting USB 2.0 using a standard CMOS fabrication process. It is shown that the primary design challenges with the implemented approach involve maintaining high frequency accuracy and low jitter. Techniques for addressing both are shown. In particular, the presented architecture exploits the effects of frequency division and low far-from-carrier phase noise to achieve low jitter. From a 1.536 GHz temperature-compensated LC reference oscillator, coherent clock signals are derived at 96MHz for the SoC logic and 12 MHz for an on-chip full-speed USB PHY. Though self-referenced, approximately plusmn400ppm total frequency accuracy is achieved over process variations, plusmn10% variation in the USB power supply voltage and temperature variation from -10 to +85degC. Measured period and cycle-to-cycle jitter are 6.78 ps_rms and 8.96 ps_rms, respectively. Fabricated in a 0.35 mum CMOS technology, the clock generator occupies 0.22 mm² and draws 9.5 mA from a 3.3-V supply, which is derived from the 5-V USB power supply     

An Efficient SoC Test Technique by Reusing On/Off-Chip Bus Bridge

Today's system-on-a-chip (SoC) is designed with reusable intellectual property cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, an efficiently testable design technique is introduced for an SoC with an on/off-chip bus bridge for the on-chip advanced high-performance bus and off-chip peripheral-component-interconnect bus. The bridge is exploited by maximally reusing the bridge function to achieve efficient functional and structural testing. The testing time can be significantly reduced by increasing the number of test channels and shortening the test-control protocols. Experimental results show that area overhead and testing times are considerably reduced in both functional- and structural-test modes. The proposed technique can be extended to the other types of on/off-chip bus bridges.      

皮秒级快速任意脉冲波形发生器

研制了一种基于光脉冲堆积和光电转换技术的任意脉冲波形发生器,其可输出一个由多路子脉冲堆积而成的电脉冲信号,该电脉冲形状可任意调整,脉冲前后沿陡峭（小于100 ps）。该任意脉冲波形发生器适用于任何需产生快速电脉冲的场合,在实验室、军用、工业加工等诸多领域的数据采集、波形分析和处理方面都有广阔的应用前景。目前该产品在国内虽有开发研制,但成熟的只有低速产品,因此研制出成熟可用的快速任意脉冲波形发生器有很大的现实意义。     

A Low-Power Single-Weight-Combiner 802.11abg SoC in 0.13 µm CMOS for Embedded Applications Utilizing An Area and Power Efficient Cartesian Phase Shifter and Mixer Circuit

A low-power 802.11abg SoC which achieves the best reported sensitivity as well as lowest reported power consumption and utilizes an extensive array of auto calibrations is reported. This SoC utilizes a two-antenna array receiver to build a single weight combiner (SWC) system. A new signal-path Cartesian phase generation and combination technique is proposed that shifts the RF signal in 22.5deg phase steps. A 3 dB improvement in received SNR is achieved in comparison to the single path receiver. The radio and AFE occupy 10 mm² of area in a digital 0.13 mum CMOS process of which 0.29 mm² is occupied by the SWC RF receiver. The radio+AFE consume 85 mW of power in active Rx mode of which 30 mW is utilized by the SWC RF front-end.     

iVisual: An Intelligent Visual Sensor SoC With 2790 fps CMOS Image Sensor and 205 GOPS/W Vision Processor

iVisual, an intelligent visual sensor SoC integrating 2790 fps CMOS image sensor and 76.8 GOPS, 374 mW vision processor, is implemented on a 7.5 mm × 9.4 mm die in a UMC 0.18 mum CMOS Image Sensor process. Light-in, answer-out SoC architecture is adopted to avoid possible privacy problems. A feature processor is designed to eliminate the dataflow mismatch between processor array and scalar processor to increase 36% of average throughput. To increase hardware utilization, an inter-processor synchronization scheme is adopted to increase 23% of average throughput. Memory access is reduced by 94% to save 726 mW of power consumption. A bitplane-based single port memory structure is adopted to reduce SRAM area. The 205 GOPS/W power efficiency and 1.16 GOPS/mm² area efficiency are therefore achieved by use of the proposed techniques.     

A “Flying-Adder” On-Chip Frequency Generator for Complex SoC Environment

The spirit of system-on-chip (SoC) approach is to integrate more and more system functions into one single chip. Consequently, the on-chip clock requirement could be very complicated due to the various functions the chip has to support. To fulfill those clock needs, it is not uncommon for more than several phase-locked loop (PLLs) to be used within one such large chip. Designing these on-chip PLLs is a very challenging task in term of cost and performance. To solve this problem for a HDTV SoC of over 50 millions transistors, a ldquoflying-adderrdquo architecture based PLL (FAPLL) is constructed. This generic FAPLL is instantiated multiple times in this SoC for different functions, resulting in significant chip cost reduction.     

An architecture and compiler for scalable on-chip communication

A dramatic increase in single chip capacity has led to a revolution in on-chip integration. Design reuse and ease of implementation have became important aspects of the design process. This paper describes a new scalable single-chip communication architecture for heterogeneous resources, adaptive system-on-a-chip (aSOC) and supporting software for application mapping. This architecture exhibits hardware simplicity and optimized support for compile-time scheduled communication. To illustrate the benefits of the architecture, four high-bandwidth signal processing applications including an MPEG-2 video encoder and a Doppler radar processor have been mapped to a prototype aSOC device using our design mapping technology. Through experimentation it is shown that aSOC communication outperforms a hierarchical bus-based system-on-chip (SoC) approach by up to a factor of five. A VLSI implementation of the communication architecture indicates clock rates of 400 MHz in 0.18-/spl mu/m technology for sustained on-chip communication. In comparison to previously-published results for an MPEG-2 decoder, our on-chip interconnect shows a runtime improvement of over a factor of four.     

基于DDS的任意波信号发生器设计

任意波形发生器己成为现代测试领域应用最为广泛的通用仪器之一,代表了信号源的发展方向。直接数字频率合成（DDS）技术的发明和应用是频率合成领域里的一次革命。基于DDS的任意波信号源利用FPGA所具有的高集成度、高速度、可实现大容量存储器功能的特性,有效地实现了DDS技术,极大地提高了函数发生器的性能,降低生产成本。     

Program and Verify Word-Line Voltage Regulator for Multilevel Flash Memories

This paper presents a word-line voltage generator for multilevel (ML) Flash memory programming. The required voltages are provided by a regulator supplied by an on-chip charge-pump voltage multiplier. A feedback loop including a digitally programmable resistive divider generates the staircase-shaped waveform needed for adequate ML programming accuracy as well as the read/verify voltage required for read and verify operations. A high-swing controlled-discharge circuit minimizes the settling time when switching from program to verify phases and vice versa. The same generator is used to provide the voltage required in read and in program mode, thus saving silicon area and minimizing current consumption. Experimental results of the proposed circuit integrated in a 4-level-cell 64-Mb NOR-type Flash memory are presented.     

谱分析方法的混合电路BIST

SoC芯片内对于混合信号电路测试有着举足轻重的作用.本文介绍了一种通过谱密度分析方法的混合电路内建自测试.此方法通过使用噪声源与比较器数字量化得到被测信号的频谱特性.它的主要特点是电路简单、抗干扰性能强和多点插入多路并行采集,不需要多位AD转换器和多路选择开关.此方法基本上是全数字式的,采用一位量化,数据处理速度快,能满足给定条件下的实时处理要求;并可利用系统内已有的资源,适应于SoC环境.本文给出了系统实现的详细结构和一个测试锁相环电路的测试仿真实例,验证了谱分析方法的测试有效性.     

A 0-dB IL 2140±30 MHz bandpass filter utilizing Q-enhancedspiral inductors in standard CMOS

A 3-pole Chebyshev bandpass filter, that employs on-chip passive elements with Q-enhancement technique, achieves an insertion loss of 0 dB and a passband of 60 MHz around a center frequency of 2140 MHz. The Q-enhancement technique is based on coupled-inductor negative resistance generator. In contrast to conventional negative resistance generator, this technique compensates resonator loss without introducing distortion in the filter response in the passband. Fabricated in a 0.25-μm CMOS, the filter consumes 7 mA from a 2.5-V supply. The filter occupies an area of 1.3 mm×2.7 mm     

Measurement of ultralow gate tunneling currents using floating-gate integrator technique

We report for the first time that a gate tunneling current measurement sensitivity better than 3/spl times/10/sup -22/ A has been achieved by using a floating-gate integrator technique. The technique involves monitoring the charge change in the floating-gate integrated with an on-chip op-amp and an on-chip feedback capacitor. We used this technique to study the stress-induced leakage current (SILC) and its cycling dependence of 70 /spl Aring/ oxides in the direct tunneling region at oxide voltage as low as 1.9 V. The technique has been validated through correlation to direct measurement on MOSFET arrays and theoretical calculations. The measured SILC current is modeled with an Inelastic trap-assisted tunneling model.     

Design and implementation of a reconfigurable mixed-signal SoC based on field programmable analog arrays

This work presents a reconfigurable mixed-signal system-on-chip (SoC), which integrates switched-capacitor-based field programmable analog arrays (FPAA), analog-to-digital converter (ADC), digital-to-analog converter, digital down converter, digital up converter, 32-bit reduced instruction-set computer central processing unit (CPU) and other digital IPs on a single chip with 0.18 μm CMOS technology. The FPAA intellectual property could be reconfigured as different function circuits, such as gain amplifier, divider, sine generator, and so on. This single-chip integrated mixed-signal system is a complete modern signal processing system, occupying a die area of 7×8 mm² and consuming 719 mW with a clock frequency of 150 MHz for CPU and 200 MHz for ADC/DAC. This SoC chip can help customers to shorten design cycles, save board area, reduce the system power consumption and depress the system integration risk, which would afford a big prospect of application for wireless communication.     

A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-Time

A portable clock generator, which solves the duty ratio and jitter problems of the input clock, has been developed. In the proposed clock generator, the complementary delay line generates a series of multiphase clocks. The 0-to-1 transition detector finds the 2 pi phase delayed position among the multiphase clocks produced by the complementary delay line, and then, the select signal generator chooses the proper path to generate the delayed output clock. As a result, the proposed open-loop and full-digital architecture achieves a fast lock time of two clock cycles. Also, it is a simple, robust and portable IP and consumes only 17 mW at an input clock frequency of 1.6 GHz. In addition, a complementary delay line is implemented to achieve high phase resolution over a wide frequency range. The proposed clock generator is implemented in a 0.18-mum CMOS process and, occupies an active area of 170 mum times 120 mum. Also, it operates at various input frequencies ranging from 800 MHz to 1.6 GHz.     

An ADC BIST with on-chip ramp generator

This work presents built-in self-test (BIST) techniques for the production testing of mixed signal circuits. The special test strategy for the typical mixed-signal component analog-to-digital converter (ADC) is discussed. The traditional test for such mixed-signal components can be completed through a DSP-based mixed-signal tester with an arbitrary waveform generator and a signal digitizer, but such a test is very costly and time consuming. Hence, a BIST strategy based on an on chip ramp generator (OCRG) is proposed in this work for testing ADC. This BIST method has an advantage testing ADC without DAC to overcome area overhead. This BIST method realizes the test controller, test pattern generation and output response analyser at the aspect of the on-chip circuitry. The demonstration of the proposed BIST is given through various simulation results in the last parts of this work.     

A 50.8–53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13- $mu$m CMOS

A 50.8-53-GHz clock generator with a quadruplicate-harmonic-locked phase detector (PD) is presented to achieve a low spur and a low reference frequency. The proposed quadruplicate-harmonic-locked PD, a low-voltage Colpitts voltage-controlled oscillator, and a wide-range divide-by-2 divider are also presented. This clock generator has been fabricated in a 0.13-mum process. The measured reference spur is -59.88 dBc at 51.02 GHz with an input reference frequency of 199.3 MHz. The area is 0.93 mm times 1 mm with the on-chip loop filter and pads. It dissipates 87 mW without buffers from a 1.5-V supply.     

一种SoC片上调试与可测性的整合设计

随着SoC的复杂度和规模的不断增长,SoC的片上调试与可测性变得越来越困难和重要。片上调试与可测性都是系统芯片设计的重要组成部分。文章针对某款32位SoC,充分利用CPU核原有的调试结构,提出一种可测试系统与调试系统的一体化结构设计,并针对不同的模块利用不同的测试策略。基于JTAG端口,该结构能够进行系统程序的调试、边界扫描的测试、扫描链的测试、嵌入式SRAM的内建自测试,同时有效地降低了电路逻辑规模,实现了在测试覆盖率和测试代价之间的一个有效折衷。     

Optimization of test resources for 3D SoC based on game theory

The ever-increasing complexity of on-chip interconnection poses great challenges for the architecture of conventional system-on-chip (SoC) in semiconductor industry. The rapid development of process technology enables the creation of stacked 3-dimensional (3D) SoC by means of through-silicon-via (TSV). Stacked 3D SoC testing consists of two major issues, test architecture optimization and test scheduling. This paper proposed game theory based optimization of test scheduling and test architecture to achieve win-win result as well as individual rationality for each player in a game. Game theory helps to achieve equilibrium between two correlated sides to find an optimal solution. Experimental results on handcrafted 3D SoCs built from ITC’2 benchmarks demonstrate that the proposed approach achieves comparable or better test times at negligible computing time.     

A Single-Chip CMOS Transceiver Front-End for DCS-1800 Wireless Communications

This work describes the design and realization of a low voltage single-chip wireless transceiver front-end in a standard 0.25 m CMOS technology. The presented prototype integrates the LNA, down-converters, VCO, quadrature generator, up-converter and pre-amplifier on a single die. A high level of integration is achieved by using a low-IF topology for reception, a direct quadrature up-conversion topology for transmission and an oscillator with on-chip integrated inductor. The final objective of this design is to develop a complete transceiver system for wireless communications at 1.8 GHz that can be built with a minimum of surrounding components: only an antenna, a duplexer, a power amplifier and a baseband signal processing chip. The presented circuit consumes 240 mW from a 2.5 V supply and occupies a die area of 8.6 mm².     

Compact Thermally Tunable Silicon Wavelength Switch: Modeling and Characterization

A wavelength-selective photonic switch is developed based on a Si microring resonator using thermooptic effect. The 10-mum-diameter microring resonator uses single-mode strip Si waveguides of dimension 0.25 mum times 0.45 mum operating at 1.5 mum. Full-width at half-maximum are in the range 0.1-0.2 nm. The ultrawide tunable range (>6.4 nm) and wide free spectral range (~18 nm) of the switch element enables wavelength reconflgurable multichannel matrix switch by wavelength multiplexing/demultiplexing. Average rise delay time of 14 mus with low switching power of 3.15 mW has been achieved with 0.2-nm wavelength tuning and 78 mus, 104 mW for 6.4-nm tuning. Fall delay times are usually less than 10 mus. Thermal simulations show 10%-20% agreement with the measurements up to 3.2-nm tuning. The compact size of the switch shows its potential as an active element in photonic integrated circuits.