The separation of generation lifetimes of Si and SiGe using capacitance-transient measurements on MOS capacitors formed by plasma anodisation of Si:Si0.9Ge0.1:Si substrates

A simple technique leading to the measurement of minority carrier lifetimes of UHV compatible LPCVD Si and SiGe by C–t depth profiling of Metal:Oxide:Si:SiGe:Si structures is reported. A high quality gate oxide is realised by low temperature (<100°C) plasma anodisation thereby reducing any oxidation effects on the underlying epitaxial layer quality. Capacitance response times were observed for an impurity concentration of 2.5×10¹⁷ cm⁻³, giving rise to generation lifetimes of the Si and Si_0.9Ge_0.1 of >0.55 and 2.6 μs respectively, reflective of very high quality epitaxial semiconductor material.     

GaN-based optoelectronic devices on sapphire and Si substrates

A recessed gate AlGaN/GaN high-electron mobility transistor (HEMT) on sapphire (0 0 0 1), a GaN metal-semiconductor field-effect transistor (MESFET) and an InGaN multiple-quantum well green light-emitting diode (LED) on Si (1 1 1) substrates have been grown by metalorganic chemical vapor deposition. The AlGaN/GaN intermediate layers have been used for the growth of GaN MESFET and LED on Si substrates. A two-dimensional electron gas mobility as high as 9260 cm²/V s with a sheet carrier density of 4.8×10¹² cm⁻² was measured at 4.6 K for the AlGaN/GaN heterostructure on the sapphire substrate. The recessed gate device on sapphire showed a maximum extrinsic transconductance of 146 mS/mm and a drain–source current of 900 mA/mm for the AlGaN/GaN HEMT with a gate length of 2.1 μm at 25°C. The GaN MESFET on Si showed a maximum extrinsic transconductance of 25 mS/mm and a drain–source current of 169 mA/mm with a complete pinch-off for the 2.5-μm-gate length. The LED on Si exhibited an operating voltage of 18 V, a series resistance of 300 Ω, an optical output power of 10 μW and a peak emission wavelength of 505 nm with a full-width at half-maximum of 33 nm at 20 mA drive current.     

Template approaches to growth of oriented oxide heterostructures on SiO2/Si

A template approach to growing highly oriented ferroelectric oxide heterostructures on SiO₂/Si substrates is presented. In this method, a thin “template” of a layered perovskite is used to induce the growth of the subsequent layers in the desired orientation. The efficacy of this “template” approach is illustrated through the example of growth of ferroelectric La-Sr-Co-0/Pb-Zr-Ti-O/La-Sr-Co-O heterostructures on SiO₂Si. Discrete test capacitors fabricated from these heterostructures grown using the template approach exhibit remnant polarization values in the range of 10–15 μ C/cm² and show very little degradation after 10¹¹ bipolar fatigue cycles. In contrast, test capacitors fabricated without the template layer showed very little crystallographic texture and poor ferroelectric properties.     

Traps with near-midgap energies at the bonded Si/SiO<Subscript>2</Subscript> interface in silicon-on-insulator structures

Capture centers (traps) are studied in silicon-on-insulator (SOI) structures obtained by bonding and hydrogen-induced stratification. These centers are located at the Si/SiO₂ interface and in the bulk of the split-off Si layer. The parameters of the centers were determined using charge deep-level transient spectroscopy (Q-DLTS) with scanning over the rate window at fixed temperatures. Such a method allows one to study the traps near the Si midgap at temperatures near 295 K. It is shown that the density of traps with a continuous energy spectrum, which are located at the bonded Si/SiO₂ interface, decreases by more than four orders of magnitude at the mid-gap compared with the peak density observed at the activation energy E _a ≈0.2–0.3 eV. The capture centers are also found in the split-off Si layer of the fabricated SOI structures. Their activation energy at room temperature is E _a =0.53 eV, the capture cross section is 10^?19 cm², and the concentration is (0.7–1.7)×10¹³ cm^?3. It is assumed that these capture centers are related to deep bulk levels induced by electrically active impurities (defects) in the split-off Si layer close to the Si/SiO₂ interface.     

Recrystallization and dielectric properties of CaHfOx films on Si

The recrystallization and dielectric behavior for amorphous CaHfO_x films on Si substrates has been investigated. Upon conventional annealing in air, the CaHfO_x films remain amorphous up to an annealing temperature of 800 °C for annealing times of 1 h. This recrystallization temperature is significantly higher than that reported for HfO₂ subjected to rapid thermal annealing. Metal–insulator–semiconductor structures with Pt gate electrodes were fabricated with various CaHfO_x film thickness for capacitance–voltage and leakage current measurements. From this, the permittivity of CaHfO_x was determined, along with interface layer capacitance for films on Si. The enhanced stability against polycrystalline grain growth, along with the thermodynamic stability of both CaO and HfO₂ in contact with Si, suggests that CaHfO_x may be an attractive gate dielectric for future generation metal–oxide–semiconductor field-effect transistor applications.     

In situ X-ray diffraction study of thin film Ir/Si solid state reactions

The solid state reaction between a thin (30 nm) Ir film and different Si substrates (p-type Si(1 0 0), n- and p-type Si(1 1 1), silicon on insulator (SOI) and polycrystalline Si) was studied using a combination of in situ X-ray diffraction (XRD), in situ sheet resistance and laser light scattering measurements. No significant influence of either the dopants or the substrate orientation was detected as a phase formation sequence of IrSi, Ir₃Si₄,Ir₃Si₅ and IrSi₃ was found for all samples. The presence of a thin (<4 nm) amorphous IrSi film at room temperature and its subsequent crystallization could be deduced from the appearance of a broad semi-amorphous diffraction peak in the XRD spectrum around 400 °C. The results were verified using ex situ Rutherford Backscattering Spectroscopy, Scanning Electron Microscopy and 4-point probe measurements on quenched samples. The activation energy of the crystallization process and the silicide growth was determined using a Kissinger analysis on ramp anneals with different ramp rates. In addition, the influence of up to 25 volumetric % (20.5 atomic %) of Ir to the silicide formation in the Ni/Si system was studied on SOI and polycrystalline Si substrates. In the presence of Ir, the temperature range over which the low resistivity NiSi exists, is reduced both through an increase in formation temperature and an earlier consumption by the formation of NiSi₂. After the heat treatment, a continuous distribution of Ir throughout the NiSi₂ phase was detected using X-ray photoelectron spectroscopy depth profiling. A low sheet resistance of was maintained on both substrates up to 900 °C.     

Low-temperature conductance measurements of surface states in HfO2–Si structures with different gate materials

Metal-oxide-semiconductor capacitors based on HfO₂ gate stack with different metal and metal compound gates (Al, TiN, NiSi and NiAlN) are compared to study the effect of the gate electrode material on the trap density at the insulator–semiconductor interface.C–V and G–ω measurements were made in the frequency range from 1 kHz to 1 MHz in the temperature range 180–300 K. From the maximum of the plot G/ω vs. ln(ω) the density of interface states was calculated, and from its position on the frequency axis the trap cross-section was found. Reducing temperature makes it possible to decrease leakage current through the dielectric and to investigate the states located closer to the band edge.The structures under study were shown to contain significant interface trap densities located near the valence band edge (around 2×10¹¹ cm⁻²eV⁻¹ for Al and up to (3.5–5.5)×10¹² cm⁻² eV⁻¹ for other gate materials). The peak in the surface state distribution is situated at 0.18 eV above the valence band edge for Al electrode. The capture cross-section is 5.8×10⁻¹⁷ cm² at 200 K for Al–HfO₂–Si structure.     

NMOSFET characteristics on a double hetero-epitaxial Si/γ-Al2O3/Si structure fabricated by a new MBE growth method

A new MBE growth method for the fabrication of a high-quality double hetero-epitaxial Si/γ-Al₂O₃/Si structure was recently developed. In the present work, characteristics of NMOSFETs fabricated on the Si/γ-Al₂O₃/Si structure were investigated, and compared with those on a Si/MgAl₂O₄/Si structure. A γ-Al₂O₃ layer was created from a MgAl₂O₄ layer by reaction with Si beams as follows: MgAl₂O₄ + Si → γ-Al₂O₃ + SiO ↑ + Mg ↑. The MBE growth of Si on the effectively restructured γ-Al₂O₃ layer was then performed at a substrate temperature of 700° C, 150° C lower than for the MBE growth of Si on a MgAl₂O₄/Si substrate. The electron field effect mobility and leakage current between source and drain for the NMOSFETs fabricated on Si/γ-Al₂O₃/Si structures were 660 cm²/V · s and 2.8 pA/μm respectively, and exhibited a higher level of performance than those on a Si/MgAl₂O₄/Si structure. In the Si/MgAl₂O₄/Si, SIMS measurements confirmed that autodoped Al and Mg atoms near the interface between the Si epi-layer and MgAl₂O₄/Si substrate diffused anomalously and accumulated at the surface during device fabrication processes. These autodoped Al and Mg atoms acted as ionized impurities during test operation. Suppression of autodoping from insulator layers during the MBE growth of Si was thus deemed essential to the improvement of NMOSFET characteristics. In the Si/γ-Al₂O₃/Si structure, autodoped atoms were scarcely detectable. It was therefore concluded that the Si/γ-Al₂O₃/Si structure under study was very promising for SOI device applications.     

Transients during pre-breakdown and hard breakdown of thin gate oxides in metal–SiO2–Si capacitors

Time–resolved electrical measurements show transient phenomena occurring during degradation and intrinsic dielectric breakdown of gate oxide layers under constant voltage Fowler–Nordheim stress. We have studied such transients in metal/oxide/semiconductor (MOS) capacitors with an n⁺ poly-crystalline Si/SiO₂/n-type Si stack and with oxide thickness between 35 and 5.6 nm. The data adds new information concerning the intrinsic breakdown mechanism and these are shown and discussed together with the adopted measurement techniques.     

A detailed study of current–voltage characteristics in Au/SiO2/n-GaAs in wide temperature range

The forward and reverse-bias current–voltage (I–V) characteristics of Au/SiO₂/n-GaAs (MIS) type Schottky barrier diode (SBDs) have been investigated in the wide temperature range of 80–400 K. The zero-bias barrier height (_Bo) and ideality factor (n) assuming the thermionic emission (TE) mechanism show strong temperature dependence. While n decreases, _Bo increases with increasing temperature. Such temperature dependence of _Bo is an obvious disagreement with the reported negative temperature coefficient (α_temp) of barrier height. Therefore, we have reported a modification which includes the n and electron-tunneling parameter (αχ^1/2δ) in the expression of reverse-saturation current (I₀). After this modification, the value of α_temp obtained as −4 × 10⁻⁴ eV/K which is very close to α_temp of GaAs band-gap (−5.4 × 10⁻⁴ eV/K). Richardson plot of the ln(I₀/T²) versus 1/T has two linear region; the first region is (200–400 K) and the second region (80–150 K). The values of the activation energy (E_a) and Richardson constant were obtained from this plot and the values of E_a and Richardson constants (A^*) are much lower than the known values. These behaviors of the Au/SiO₂/n-GaAs (MIS) type (SBDs) have been interpreted by the assumption of a double-Gaussian distribution of barrier heights (BHs) at the metal–semiconductor interface giving a mean BHs () of 1.20 and 0.68 eV and standard deviation (σ_s) of 0.1503 and 0.0755 V, respectively. Thus the modified ln versus q/kT for two different temperature ranges (200–400 K and 80–150 K) plot then gives mean barrier heights and A^*, 1.18 and 0.66 eV and 7.08 and 3.81 A/cm² K², respectively. This value of the A^* 7.08 A/cm² K² is very close to the theoretical value of 8.16 A/cm² K² for n-type GaAs. Hence, all these behaviours of the forward-bias I–V characteristics of the Au/SiO₂/n-GaAs (MIS) type SBDs can be successfully explained on the basis of a TE mechanism with a double-Gaussian distribution of the BHs.     

Investigation of Si/SiGe/Si heterostructure implanted by H ion and annealed in vacuum and dry O2 ambient

The 20-nm-thick Si cap layer/74-nm-thick Si_0.72Ge_0.28 epilayer/Si heterostructures implanted by 25 keV H⁺ ion to a dose of 1×10¹⁶ cm⁻² were annealed in ultra-high vacuum ambient and dry O₂ ambient at the temperature of 800 °C for 30 min, respectively. Rutherford backscattering/ion channeling (RBS/C), Raman spectra, high-resolution X-ray diffraction (HRXRD) and atomic force microscopy (AFM) were used to characterize the structural characteristics of the Si_0.72Ge_0.28 layer. Investigations by RBS/C demonstrated that the crystal quality of the Si/Si_0.72Ge_0.28/Si heterostructure sample implanted by 25 keV H⁺ in conjunction with subsequent annealing in dry O₂ ambient is superior to that of identical sample annealing in ultra-high vacuum ambient. The less strain relaxation of SiGe layer of the Si/Si_0.72Ge_0.28/Si heterostructures implanted by H ion and annealed in dry O₂ ambient at the temperature of 800 °C for 30 min could be doublechecked by Raman spectra as well as HRXRD, which was compared with that in an identical sample annealed in ultra-high vacuum ambient for identical thermal budget. In addition, the SiGe layer of the H-implanted Si/SiGe/Si heterostructural sample annealed in dry O₂ ambient accompanied by better crystal quality and less strain relaxation made its surface morphology superior to that of the sample annealed in ultra-high vacuum ambient at the temperature of 800 °C for 30 min, which was also verified by AFM images.     

Interfacial layer quality effects on low-frequency noise (1/f) in p-MOSFETs with advanced gate stacks

The effects of interfacial layer quality on the low-frequency noise behavior of p-channel MOSFETs with high-κ gate dielectric and metal gate are investigated. Devices with chemically grown SiO₂ interfacial layers (0.8 nm) are compared with N₂O (0.8 nm) interfacial oxides. A 0.4 nm SiO₂ interfacial layer device is used for comparison purposes. A cross-over kind of behavior has been observed in N₂O devices, which occur at lower gate voltages (1.2–1.3 V) when normalized spectral densities and input referred noise are investigated. This behavior is found to be closely related to the observed transconductance variation in these devices. The dominant mechanism of 1/f noise is found to be Hooge’s mobility fluctuations. Hooge’s parameter, as a figure of merit, shows an increase for 0.4 nm devices when compared to 0.8 nm devices, while 0.8 nm N₂O devices confirm their cross-over nature.     

Electroluminescence from Au/Si/SiO2/p-Si structure

Si/SiO₂ films have been grown using the two-target alternation magnetron sputtering technique. The thickness of the SiO₂ layer in all the films was 8 nm and that of the Si layer in five types of the films ranged from 4 to 20 nm in steps of 4 nm. Visible electroluminescence (EL) has been observed from the Au/Si/SiO₂/p-Si structures at a forward bias of 5 V or larger. A broad band with one peak 650–660 nm appears in all the EL spectra of the structures. The effects of the thickness of the Si layer in the Si/SiO₂ films and of input electrical power on the EL spectra are studied systematically.     

Fabrication of Strain-Relaxed Si<Subscript>1 − <Emphasis Type="Italic">x</Emphasis></Subscript>Ge<Subscript>x</Subscript>/Si(001) Buffer Layers of Low Surface Roughness

The results are presented of the fabrication of strain-relaxed graded Si_{1 − x} Ge_x/Si(001) buffer layers with a maximum Ge fraction of about 0.25 that have a low density of threading dislocations (<10⁶ cm⁻²) and low surface roughness. The buffer layers are grown by atmospheric-pressure hydride CVD. It is found that chemical mechanical polishing can reduce their surface roughness to a level comparable with that of the original Si(001) substrates. It is shown that the polished buffer layers can serve as substrates for MBE-grown SiGe/Si heterostructures.__________Translated from Mikroelektronika, Vol. 34, No. 4, 2005, pp. 243–250.Original Russian Text Copyright © 2005 by Vostokov, Drozdov, Krasil’nik, Kuznetsov, Novikov, Perevoshchikov, Shaleev.     

Thermal stability of Si/Gen/Si heterostructures by photoreflectance

The thermal stability of Si/Ge_n/Si(001) heterostructures includingn = 1, 6, 20, and 100 monolayers (ML’s) is studied in connection with their electronic structures through the measurement of photoreflectance (PR). The PR spectra are observed at 90 K over the energy range 0.85–4.0 eV. Comparing the PR signals of Si/Ge _n /Si(001) heterostructures before and after thermal annealing at 600° C, it is found that the samples with less than 6 ML Ge show no change whereas those with more than 20 ML Ge show large changes. The result suggests that Si/Ge _n /Si heterostructures with Ge layer thickness less than 6 ML’s are thermally stable. For the heterostructures with 20 and 100 ML Ge, the relaxation of strain in the Ge layer is found to occur from the PR spectra ofE ₀(Ge),E ₁(Ge) andE ₁ +Δ ₁(Ge), andE ₁(Si).     

Thermal Ta2O5––alternative to SiO2 for storage capacitor application

Tantalum pentoxide thin layers (10–100 nm) obtained by thermal oxidation of rf sputtered Ta films on Si have been investigated with respect of their dielectric, structural and electric properties. It is established that stoichiometric Ta₂O₅ detected at the surface of the layers is reduced to tantalum suboxides in their depth. The oxide parameters are discussed in terms of a presence of an unavoidable ultrathin SiO₂ between Si and Ta₂O₅ and bond defects in both the oxide and the interface transition region. Conditions which guarantee obtaining high quality tantalum oxide with a dielectric constant of 32–35 and a leakage current less than 10⁻⁷–10⁻⁸ A/cm² at 1.5 V (SiO₂ equivalent thickness of 2.5–3 nm) are established. These specifications make the layers obtained suitable alternative to SiO₂ for high density DRAMs application.     

Investigation of high-K gate stacks with epitaxial Gd2O3 and FUSI NiSi metal gates down to CET=0.86 nm

Novel gate stacks with epitaxial gadolinium oxide (Gd₂O₃) high-k dielectrics and fully silicided (FUSI) nickel silicide (NiSi) gate electrodes are investigated. Ultra-low leakage current densities down to 10^–7 A cm^–2 are observed at a capacitance equivalent oxide thickness of CET=1.8 nm. The influence of a titanium nitride (TiN) capping layer during silicidation is studied. Furthermore, films with an ultra-thin CET of 0.86 nm at a Gd₂O₃ thickness of 3.1 nm yield current densities down to 0.5 A cm⁻² at V_g=+1 V. The extracted dielectric constant for these gate stacks ranges from k=13 to 14. These results emphasize the potential of NiSi/Gd₂O₃ gate stacks for future material-based scaling of CMOS technology.     

Charge trapping and interface states in hydrogen annealed HfO2–Si structures

Metal–oxide–semiconductor (MOS) capacitors based on HfO₂ gate stacks with Al and TiN gates are compared to study the effect of the gate electrode material to the properties of insulator–semiconductor interface. The structures under study were shown to contain interface trap densities of around 2 × 10¹¹ cm⁻² eV⁻¹ for Al gate and up to 5.5 × 10¹² cm⁻² eV⁻¹ for TiN gate. The peak in the surface state distribution was found at 0.19 eV above the valence band edge for Al electrode. The respective capture cross-section is 6 × 10⁻¹⁷ cm² at 200 K.The charge injection experiments have revealed the presence of hole traps inside the dielectric layer. The Al-gate structure contains traps with effective capture cross-section of 1 × 10⁻²⁰ cm², and there are two types of traps in the TiN-gate structure with cross-sections of 3.5 × 10⁻¹⁹ and 1 × 10⁻²⁰ cm². Trap concentration in the structure with Al electrode was considerably lower than in the structure with TiN electrode.     

Study of dc conduction mechanisms in dysprosium–manganese oxide insulator thin films grown on Si substrates

Samples of amorphous and crystalline (Dy–Mn) oxide thin films have been prepared on Si(p) substrates. The crystal structure of the oxide film annealed under different conditions was investigated by the X-ray diffraction method (XRD). The percentage weight composition of the compound-oxide films was determined by the X-ray fluorescence (XRF) spectroscopy method. It was observed that Dy oxide and Mn oxide prevent each other to crystallize alone or making a solid solution even at 600 °C, but a compound of DyMnO₃ was formed through the solid-state reaction at T > 800 °C. Samples in form of Al/oxide/Si MOS structures were characterised by measuring their capacitance as a function of gate voltage C(V_g) in order to determine the fixed and interface charge densities as well as the oxide voltage in terms of gate voltage. The total surface charge density was in the device-grade of 10¹⁰–10¹¹ cm⁻². The dc measurements at room temperature show that the main mechanism controlling the current flow is the Richardson–Schottky (RS) mechanism. The parameters of the RS model like the field lowering coefficients and the dynamic relative permittivity were determined. The leakage current density of the samples was studied as a function of temperature in a range of (293–380 K). It was observed that the temperature dependence of crystalline (Dy–Mn) oxide films has a property that higher temperature reduces the current, which may be important in the application in circuits that operate under extreme conditions. Thermal activation energies of electrical conduction were determined.     

ESD robustness prediction and protection device design in partially depleted SOI technology

In this paper we investigate and develop models for partially-depleted silicon-on-insulator (SOI) (PD–SOI) device failure under EOS/ESD stress. The model and experimental data show that due to increased device self-heating, the second-breakdown current per micron width (I_t2) for salicided PD-SOI metal-oxide semiconductor field effect transistor (MOSFET)s with Si film thickness of 100 nm is about 50% of that in their bulk counterparts under human body model (HBM–ESD) stress pulses. Furthermore, I_t2 did not scale with device width. Therefore, ESD protection devices with non-silicided S/D diffusions and source-body tied MOSFETs are investigated for improved ESD protection levels. Compact ESD protection networks using the source-body tied device may have been shown to achieve HBM–ESD protection levels of ±3.75 kV (Smith JC, Lien M, Veeraghaven S. An ESD protection circuit for TFSOI technology. International SOI Conf. Proc. 1996. pp. 170–71).