Novel Silicon?Carbon (Si:C) Schottky Barrier Enhancement Layer for Dark-Current Suppression in Ge-on-SOI MSM Photodetectors

This letter reports the first demonstration of an evanescent coupled germanium-on-silicon-on-insulator (Ge-on-SOI) metalsemiconductormetal (MSM) photodetector with a novel siliconcarbon (Si:C) Schottky barrier enhancement layer. Through the insertion of a Si:C barrier layer between the metal/Ge interface, the hole Schottky barrier height $phi_{rm bh}$ can effectively be enhanced to $simkern1pt$0.52 eV above the valence band edge. As a result, significant dark-current $I_{rm Dark}$ suppression by more than four orders of magnitude was demonstrated, leading to an impressive $I_{rm Dark}$ of $sim$11.5 nA for an applied bias $V_{A}$ of 1.0 V. Optical measurements performed at a photon wavelength of 1550 nm revealed the achievement of good internal responsivity and quantum efficiency of $sim$530 mA/W and 42.4%, respectively, making such a high-performance Ge-on-SOI MSM photodetector a promising option for optical communication applications.     

Characteristics of MSM photodetectors with trench electrodes onp-type Si wafer

U-grooved metal-semiconductor-metal photodetectors (UMSM-PD's) having various trench depths of interdigitated electrodes and an intrinsic hydrogenated amorphous silicon (i-a-Si:H) to c-Si heterojunction have been fabricated successfully on a p-type [100] Si wafer. The U-grooved structures on c-Si were achieved with a simple orientation-dependent etching (ODE) process. Some important characteristics of the obtained UMSM-PDs are presented and discussed. An UMSM-PD with a 70 nm i-a-Si:H overlayer, 1.45 μm-deep recessed electrodes, and 3 μm finger width and spacing, had a full width at half maximum (FWHM) of 50.6 ps and a full-time of 132 ps for its temporal response under a bias of 15 V. The significant improvements of transient response for UMSM-PD, as compared to the conventional one, were attributed to the trench electrodes resulted in a stronger lateral electric field in the light absorption region of photodetector. At a bias of 20 V, this UMSM-PD had a responsivity of 0.25 A/W as measured with an 0.83-μm incident semiconductor laser, a high photo/dark current ratio about 2000, and an internal quantum efficiency of 36%. This high photo/dark current ratio would be due to the additional i-a-Si:H overlayer on Si wafer. These mentioned performances were much better than those of the conventional Si-based planar MSM-PD     

Highly reliable CVD-WSi metal gate electrode for nMOSFETs

In this paper, we first propose an improved chemical vapor deposition (CVD) WSi/sub x/ metal gate suitable for use in nMOSFETs. We studied the relationship between the Si/W ratio of CVD-WSi/sub x/ film and electrical properties of MOSFETs. As a result, it was found that the Si/W ratio strongly affects carrier mobility and the reliability of gate oxide. In the case of higher Si/W ratio, both electron and hole mobility can be improved. For CVD-WSi/sub 3.9/ electrode, electron mobility and hole mobility at 1.2 V of |V/sub g/-V/sub th/| are 331 and 78 cm/sup 2//V/spl middot/s, respectively. These values are almost the same as those for n/sup +/-poly-Si electrode. The improvement of carrier mobility by controlling the Si/W ratio is due to suppression of fluorine contamination in gate oxide. F contamination at the Si/W ratio of 3.9 is found to be less than that at the Si/W ratio of 2.4 from XPS analysis. Workfunction of CVD-WSi/sub 3.9/ gate estimated from C-V measurements is 4.3 eV. In CVD-WSi/sub 3.9/ gate MOSFETs with gate length of 50 nm, a drive current of 636 /spl mu/A//spl mu/m was achieved for off-state leakage current of 35 nA//spl mu/m at power supply voltage of 1.0 V. By using CVD-WSi/sub 3.9/ gate electrode, highly reliable metal gate nMOSFETs can be realized.     

Anodic Oxidation of Si in Oxygen/Chlorine Plasma

By adding a few percent of chlorine to oxygen plasma, the anodization rate of Si was enhanced; for example, the rate was doubled for oxygen containing 3-percent chlorine. With a chlorine concentration of 1.5 percent, the density of trap states at the Si-SiO/sub 2/ interface was reduced from 7 X 10/sup 11//cm/sup 2//spl dot/eV to 5 X 10/sup 11//cm/sup 2/ /spl dot/eV at the midgap of Si; after annealing at 800/spl deg/C in argon for 60 min, it was reduced to 8 X 10/sup 10//cm/sup 2//spl dot/eV, and did not return to the original value after heating the specimen to 800/spl deg/C. The density and capture cross section of traps in plasma-anodic oxide were also measured using the constant-current avalanche-injection method. The number of electron traps with small cross sections in plasma-anodic SiO/sub 2/ films was reduced by annealing them at 800/spl deg/C in argon, but SiO/sub 2/ films which were anodized in oxygen/chlorine plasma showed an increase of trap density under the same annealing condition.     

A high efficient 820 nm MOS Ge quantum dot photodetector

A Ge quantum dot photodetector has been demonstrated using a metal-oxide-semiconductor (MOS) tunneling structure. The oxide film was grown by liquid phase deposition (LPD) at 50/spl deg/C. The photodetector with five-period Ge quantum dot has responsivity of 130, 0.16, and 0.08 mA/W at wavelengths of 820 nm, 1300 nm, and 1550 nm, respectively. The device with 20-period Ge quantum dot shows responsivity of 600 mA/W at the wavelength of 850 nm. The room temperature dark current density is as low as 0.06 mA/cm/sup 2/. The high performance of the photodetectors at 820 nm makes it feasible to integrate electrooptical devices into Si chips for short-range optical communication.     

Low-noise silicon carbide X-ray sensor with wide operating temperature range

A silicon carbide (SiC) sensor is presented with high energy resolution in X-ray spectroscopy over a wide temperature range (27-100/spl deg/C). The sensor, consisting of a Schottky barrier diode on high resistivity epitaxial SiC, is characterised by an extremely low noise due to its ultra-low reverse current density even at high operating temperature (15 pA/cm/sup 2/ at 27/spl deg/C and 0.5 nA/cm/sup 2/ at 100/spl deg/C). Equivalent noise charges as low as 17 electrons rms at 27/spl deg/C and 47 electrons rms at 100/spl deg/C have been measured, allowing X-ray spectroscopy with an energy resolution as low as 315 eV and 797 eV FWHM, respectively.     

Ge outdiffusion effect on flicker noise in strained-Si nMOSFETs

The flicker noise characteristics of strained-Si nMOSFETs are significantly dependent on the gate oxide formation. At high temperature (900/spl deg/C) thermal oxidation, the Si interstitials at the Si/oxide interface were injected into the underneath Si-SiGe heterojunction, and enhanced the Ge outdiffusion into the Si/oxide interface. The Ge atoms at Si/oxide interface act as trap centers, and the strained-Si nMOSFET with thermal gate oxide yields a much larger flicker noise than the control Si device. The Ge outdiffusion is suppressed for the device with the low temperature (700/spl deg/C) tetraethylorthosilicate gate oxide. The capacitance-voltage measurements of the strained-Si devices with thermal oxide also show that the Si/oxide interface trap density increases and the Si-SiGe heterojunction is smeared out due to the Ge outdiffusion.     

High-speed Si-based metal-semiconductor-metal photodetectors with an additional composition-graded i-a-Si1−xGex:H layer

The response-speed of Si-based metal-semiconductor-metal (MSM) photodetectors was improved by depositing a composition-graded intrinsic hydrogenated amorphous silicon–germanium (i-a-Si_1−xGe_x:H) layer on crystalline silicon (c-Si). In contrast to the non-composition-graded one (using intrinsic hydrogenated amorphous silicon (i-a-Si:H) layer), the full width at half maximum (FWHM) and fall time of the photodetector transient response were improved from 145.2, 404.6 to 107.6, 223.4 ps respectively. The experimental results showed that the device responsivity and quantum efficiency were increased from 0.329 (A/W) and 0.492 to 0.414 and 0.619 respectively by the employed composition-graded technique. We propose that this enhancement is due to a smoother barrier that is formed at the c-Si and i-a-Si_1−xGe_x:H interface. A lower deposition temperature of i-a-Si_1−xGe_x:H layer could be used to further reduce the fall time of the device transient response from 315.6 (250 °C) to 97.6 (180 °C) ps. To improve the contact properties between Cr electrode and i-a-Si_1−xGe_x:H layer, an annealing technique in hydrogen ambient was employed. The device knee voltage, which is the applied voltage at which the device current start to enter the saturation region in its current (log-scale) versus applied voltage characteristics, could be reduced to around 3.5 V after annealing.     

Electrical properties and thermal stability of CVD HfOxNy gate dielectric with poly-Si gate electrode

High-quality, ultrathin chemical vapor deposition (CVD) hafnium oxynitride (HfOxNy) gate dielectric with poly-silicon (Si) gate electrode has been investigated for the first time. This CVD HfOxNy gate dielectric film remains amorphous after 950 /spl deg/C N/sub 2/ annealing. Compared with HfO/sub 2/ films with poly-Si gate electrode and similar equivalent oxide thickness (EOT), CVD HfOxNy shows significantly reduction in leakage-current density and boron penetration and superior thermal and electrical stability.     

Effects of localized contamination with copper in MOSFETs

Using a relatively large size MOSFET (W/L= 15/15 /spl mu/m), we investigated the degradation of MOSFET characteristics due to localized copper contamination. In order to contaminate a part of the active region of MOSFET, silicon nitride (Si/sub 3/N/sub 4/) over the active region, which is known to be a protective film against copper, was etched by reactive ion etching (RIE). As the area of localized copper contamination is about 3-4 /spl mu/m or above, apart from the edge of the gate electrode, no degradation was observed after thermal treatment at 450/spl deg/C for 2 h in N/sub 2/ ambient, based on the result of the increase in interface trap density (/spl Delta/D/sub it/).     

The hetero-epitaxial SiCN/Si MSM photodetector for high-temperature deep-UV detecting applications

A visible-blind ultraviolet (UV) photodetector (PD) with metal-semiconductor-metal (MSM) structure has been developed on a cubic-crystalline SiCN film. The cubic-crystalline SiCN film was deposited on Si substrate with rapid thermal chemical vapor deposition (RTCVD). The optoelectron performances of the SiCN-MSM PD have been examined by the measurement of photo and dark currents and the currents' ratio under various operating temperatures. The current ratio for 254-nm UV light of the detector is about 6.5 at room temperature and 2.3 at 200/spl deg/C, respectively. The results are better than the counterpart /spl beta/-SiC of 5.4 at room temperature, and less than 2 for above 100/spl deg/C, thus offering potential applications for low-cost and high-temperature UV detection.     

Electrical properties of amorphous high-/spl kappa/ HfTaTiO gate dielectric with dielectric constants of 40-60

High-quality Hf-based gate dielectrics with dielectric constants of 40-60 have been demonstrated. Laminated stacks of Hf, Ta, and Ti with a thickness of /spl sim/10 /spl Aring/ each was deposited on Si followed by rapid thermal anneal. X-ray diffraction analysis showed that the crystallization temperature of the laminated dielectric stack is increased up to 900/spl deg/C. The excellent electrical properties of HfTaTiO dielectrics with TaN electrode have been demonstrated, including low interface state density (D/sub it/), leakage current, and trap density. The effect of binary and ternary laminated metals on the enhancement of dielectric constant and electrical properties has been studied.     

Selective vapor-liquid-solid epitaxial growth of micro-Si probe electrode arrays with on-chip MOSFETs on Si (111) substrates

This paper reports on a fabrication technique for realizing micro-Si probe arrays with MOSFETs on the same Si substrate. Micro-Si probe arrays have been successfully fabricated on Si (111) substrates by selective vapor-liquid-solid (VLS) growth using catalytic Au dot arrays and Si/sub 2/H/sub 6/ used as the gas source for a molecular-beam-epitaxy. The Si probes can be grown at temperatures ranging from 500/spl deg/C to 700/spl deg/C. In this paper, MOSFETs were fabricated on Si (111) substrates and Au dots were placed at the drain regions of the MOSFETs in order to grow the Si probes. VLS growth at 700/spl deg/C for 2 h was carried out on these substrates. Consequently, the MOSFETs can be used in on-chip circuits for the VLS-Si probe array. The electrical characteristics of the MOSFETs were measured before and after the VLS process. After the VLS process, no changes in the MOSFET characteristics were observed due to the effects of Au-diffusion, and the results confirmed that VLS growth at a temperature of 700/spl deg/C allows fabrication of micro-Si probes without deterioration of the MOSFETs. VLS-Si probes with controlled conductance were realized. The as-grown Si probes were of high resistance, but could be changed to various conductivities by impurity diffusion.     

Charge trapping in ultrathin hafnium oxide

The charge trapping properties of ultrathin HfO/sub 2/ in MOS capacitors during constant voltage stress have been investigated. The effects of stress voltage, substrate type, annealing temperature, and gate electrode are presented in this letter. It is shown that the generation of interface-trap density under constant-voltage stress is much more significant for samples with Pt gate electrodes than that with Al gates. The trapping-induced flatband shift in HfO/sub 2/ with Al gates increases monotonically with injection fluence for p-type Si substrates, while it shows a turnaround phenomenon for n-type Si substrates due to the shift of the charge centroid. The trapping-induced flatband shift is nearly independent of stress voltage for p-type substrates, while it increases dramatically with stress voltage for n-type Si substrates due to two competing mechanisms. The trap density can be reduced by increasing the annealing temperature from 500/spl deg/C to 600/spl deg/C. The typical trapping probability for JVD HfO/sub 2/ is similar to that for ALD HfO/sub 2/.     

Memory characteristics of MOSFETs with densely stacked silicon nanocrystal Layers in the gate oxide synthesized by low-energy ion beam

Densely stacked silicon nanocrystal layers embedded in the gate oxide of MOSFETs are synthesized with Si ion implantation into an SiO/sub 2/ layer at an implantation energy of 2 keV. In this letter, the memory characteristics of MOSFETs with 7-nm tunnel oxide and 20-nm control oxide at various temperatures have been investigated. A threshold voltage window of /spl sim/ 0.5 V is achieved under write/erase (W/E) voltages of +12 V/-12 V for 1 ms. The devices exhibit good endurance up to 10/sup 5/ W/E cycles even at a high operation temperature of 150/spl deg/C. They also have good retention characteristics with an extrapolated ten-year memory window of /spl sim/ 0.3 V at 100/spl deg/C.     

Optical subthreshold current method for extracting the interface states in MOS systems

Optical subthreshold current method (OSCM) is proposed for characterizing the interface states in MOS systems using the current-voltage characteristics under a photonic excitation. An optical source with a subbandgap (E/sub ph/相似文献   

Enhancing leakage suppression in carbon-rich silicon junctions

Carbon-incorporated devices exhibit an increase in junction leakage relative to pure Si devices. The authors demonstrate that a leakage suppression of /spl sim/ 50 times can be achieved in carbon-rich (Si:C) junctions. This is accomplished by a prolonged annealing for 1 to 10 min at 850 /spl deg/C (much lower than typical annealing temperature of >1000/spl deg/C) and is attributed to a decrease in interstitial carbon concentration. After a 10-min annealing, the Si:C junctions display a leakage of 4/spl times/10/sup -13/ A//spl mu/m, which is much lower than that of 1050 /spl deg/C spike annealed Si junctions and well within the I/sub off/ requirements of low-standby-power device at the 45-nm node. Carbon-incorporated transistors with a gate length of 0.18 /spl mu/m exhibit an I/sub off/ reduction of /spl sim/ 10 times, compared to pure Si transistors, and both transistors have a similar subthreshold slope of 81 mV/dec.     

Sub-500/spl deg/C solid-phase epitaxy of ultra-abrupt p/sup +/-silicon elevated contacts and diodes

A well-controlled low-temperature process, demonstrated from 350/spl deg/C to 500/spl deg/C, has been developed for epitaxially growing elevated contacts and near-ideal diode junctions of Al-doped Si in contact windows to the Si substrate. A physical-vapor-deposited (PVD) amorphous silicon layer is converted to monocrystalline silicon selectively in the contact windows by using a PVD aluminum layer as a transport medium. This is a solid-phase-epitaxy (SPE) process by which the grown Si is Al-doped to at least 10/sup 18/ cm/sup -3/. Contact resistivity below 10/sup -7/ /spl Omega//spl middot/cm/sup 2/ is achieved to both p/sup -/ and p/sup +/ bulk-silicon regions. The elevated contacts have also been employed to fabricate p/sup +/-n diodes and p/sup +/-n-p bipolar transistors, the electrical characterization of which indicates a practically defect-free epitaxy at the interface.     

Thin-film transistors on plastic and glass substrates using silicon deposited by microwave plasma ECR-CVD

Thin-film transistors (TFTs) were fabricated on polyimide and glass substrates at low temperatures using microwave ECR-CVD deposited amorphous and nanocrystalline silicon as active layers. The amorphous Si TFT fabricated at 200 /spl deg/C on the polyimide foil had a saturation region field effect mobility of 4.5 cm/sup 2//V-s, a linear region mobility of 5.1 cm/sup 2//V-s, a threshold voltage of 3.7 V, a subthreshold swing of 0.69 V/decade, and an ON/OFF current ratio of 7.9 /spl times/ 10/sup 6/. This large mobility and high ON/OFF current ratio were attributed to the high-quality channel materials with less dangling bond defect states. Nanocrystalline Si TFTs fabricated on glass substrates at 400 /spl deg/C showed a saturation region mobility of 14.1 cm/sup 2//V-s, a linear region mobility of 15.3 cm/sup 2//V-s, a threshold voltage of 3.6 V, and an ON/OFF current ratio of 6.7 /spl times/ 10/sup 6/. TFT performance was mostly independent of substrate type when fabrication conditions were the same.     

AlGaAsSb-InGaAsSb HPTs with high optical gain and wide dynamic range

Novel heterojunction phototransistors based on AlGaAsSb-InGaAsSb material systems are fabricated and their characteristics are demonstrated. Responsivity of a phototransistor is measured with applied bias voltage at four different wavelengths. The maximum responsivity around 1400 A/W and minimum noise equivalent power of 1.83/spl times/10/sup -14/ W/Hz/sup 1/2/ from this phototransistor with bias of 4.0 V at a wavelength of 2.05 /spl mu/m were measured at 20/spl deg/C and -20/spl deg/C, respectively. Noise equivalent power of the phototransistor is considerably lower compared with commercially available InGaAs p-i-n photodiodes. Collector current measurements with applied incident power are performed for two phototransistors. Currents of 400 nA at low intensity of 0.425 /spl mu/W/cm/sup 2/ and of 30 mA at high intensity of 100 mW/cm/sup 2/ are determined. Collector current increases nearly by five orders of magnitude between these two input intensities. High and constant optical gain of 500 in the 0.46-nW to 40-/spl mu/W input power range is achieved, which demonstrates high dynamic range for such devices at these power levels.