IDEAS08: An Strategy for Automatic Conformance Testing in Embedded Systems

Software testing is an expensive and time-consuming activity; it is also error-prone due to human factors. But, it still is the most common effort used in the software industry to achieve an acceptable level of quality for its products. An alternative is to use formal verification approaches, although they are not widespread in industry yet. This paper proposes an automatic verification approach to aid system testing based on refinement checking, where the underlying formalisms are hidden from the developers. Our approach consists in using a controlled natural language (a subset of English) to describe requirements (where it is automatically translated into the formal specification language CSP) and extracting a model directly from a mobile phone using a developed tool support; these artifacts are normalized in the same abstraction level and compared using the refinement checker FDR. This approach is being used at Motorola; the source of our case study.     

On Formal Modeling and Validation of Wireless Sensor Network Protocols

Formal verification is becoming more and more important in the field of wireless networks (WSN). The general purpose formal method called Event-B is the latest incarnation of the B Method: it is a proof based approach with a formal notation and refinement technique for modeling and verifying systems. Refinement enables implementation level features to be proven correct with respect to an abstract specification of the system. This paper proposes an initial attempt to model and verify consistency and correctness of a WSN operation in its different layers. Several formal models are introduced for this type of networks. In the first time, coloured Petri net are used to elaborate network layer models, then each one will be detailed by an Event-B formalism, while proofs are carried out using the RODIN platform which is an integrated development framework for Event-B.

     

Co-synthesis and co-simulation of control-dominated embedded systems

This paper presents a methodology for hardware/software co-design with particular emphasis on the problems related to the concurrent simulation and synthesis of hardware and software parts of the overall system. The proposed approach aims at overcoming the problem of having two separate simulation environments by defining a VHDL-based modeling strategy for software execution, thus enabling the simulation of hardware and software modules within the same VHDL-based CAD framework. The proposed methodology is oriented towards the application field of control-dominated embedded systems implemented onto a single chip.     

On supporting rapid prototyping of embedded systems with reconfigurable architectures

Reducing time-to-market while improving product quality is a big challenge. This paper proposes a software-supported framework for rapid prototyping that offers a concurrent fast hardware/software system-level design. The introduced framework enables the constant evaluation and verification of the prototype under development, while it provides automatic functionality mapping to hardware via High-Level Synthesis techniques. We evaluate our framework and its software instantiation with a computer vision algorithm. Based on our experimentation, we show that our approach reduces the development time by almost 64×, it prunes the hardware design space by 34×, while maintaining designs that trade-off high Quality-of-Report on the Pareto frontier.     

A Methodology for Variable Structure System Specification: Formalism,Framework, and Its Application to ATM-Based Network System

This paper presents a formalism-based methodology and its implemented environment which constitutes a sound framework for real-time systems development. The software and/or hardware systems developed in such a formal manner are wellstructured and maintainable. We first propose a set-theoretic VSSS (Variable Structure System Specification) formalism. This formalism is the core of the presented methodology which supports a means of formal specification for real-time systems. We then develop the environment, including VSSS language definition, a translator for the language, and supporting libraries for real-time execution. Finally, a demonstration of the methodology in development of a real-time event manager, a subsystem of an ATM-based communication system, shows the correctness and efficiency of the methodology.     

Hardware/software codesign: a systematic approach targeting data-intensive applications

This article presents a systematic approach to hardware/software codesign targeting data-intensive applications. It focuses on the application processes that can be represented in directed acrylic graphs (DAGs) and use a synchronous dataflow (SDF) model, the popular form of dataflow employed in DSP systems when running the process. The codesign system is based on the ultrasonic reconfigurable platform, a system designed jointly at Imperial College and the SONY Broadcast Laboratory. This system is modeled as a loosely coupled structure consisting of a single instruction processor and multiple reconfigurable hardware elements. The paper also introduces and demonstrates a task-based hardware/software codesign environment specialized for real-time video applications. Both the automated partitioning and scheduling environment and the task manager program help to provide a fast robust for supporting demanding applications in the codesign system.     

VHDL-based rapid system prototyping

The Rapid Prototyping of Application-Specific Signal Processors (RASSP) [1–3] program of the US Department of Defense (ARPA and Tri-Services) targets a 4X improvement in the design, prototyping, manufacturing, and support processes (relative to current practice). Based on a current practice study (1993) [4], the prototyping time from system requirements definition to production and deployment, of multiboard signal processors, is between 37 and 73 months. Out of this time, 25–49 months is devoted to detailed hardware/software (HW/SW) design and integration (with 10–24 months devoted to the latter task of integration). With the utilization of a promising top-down hardware-less codesign methodology based on VHDL models of HW/SW components at multiple abstractions, reduction in design time has been shown especially in the area of hardware/software integration [5]. The authors describe a top-down design approach in VHDL starting with the capture of system requirements in an executable form and through successive stages of design refinement, ending with a detailed hardware design. This hardware/software codesign process is based on the RASSP program design methodology called virtual prototyping, wherein VHDL models are used throughout the design process to capture the necessary information to describe the design as it develops through successive refinement and review. Examples are presented to illustrate the information captured at each stage in the process. Links between stages are described to clarify the flow of information from requirements to hardware.     

基于android平台的鼠标的设计与实现

针对当前基于Android平台的电子产品的市场需求,以谷歌发布的Gingerbread源码为软件平台,以东南大学国家专用集成电路系统工程技术研究中心设计的基于国产CPU的sep6200芯片为硬件平台,在分析Android输入系统框架的基础上,设计并实现了软件鼠标和硬件鼠标功能,方案设计灵活。对于手持终端设备来说,鼠标的支持大大提高了用户的体验性能,具有一定的市场应用价值。     

Hardware-accelerated design space exploration framework for communication systems

The efficient hardware implementation of signal processing algorithms requires a rigid characterization of the interdependencies between system parameters and hardware costs. Pure software simulation of bit-true implementations of algorithms with high computational complexity is prohibitive because of the excessive runtime. Therefore, we present a field-programmable gate array (FPGA) based hybrid hardware-in-the-loop design space exploration (DSE) framework combining high-level tools (e.g. MATLAB, C++) with a System-on-Chip (SoC) template mapped on FPGA-based emulation systems. This combination significantly accelerates the design process and characterization of highly optimized hardware modules. Furthermore, the approach helps to quantify the interdependencies between system parameters and hardware costs. The achievable emulation speedup using bit-true hardware modules is a key enabling the optimization of complex signal processing systems using Monte Carlo approaches which are infeasible for pure software simulation due to the large required stimuli sets. The framework supports a divide-and-conquer approach through a flexible partitioning of complex algorithms across the system resources on different layers of abstraction. This facilitates to efficiently split the design process among different teams. The presented framework comprises a generic state of the art SoC infrastructure template, a transparent communication layer including MATLAB and hardware interfaces, module wrappers and DSE facilities. The hardware template is synthesizable for a variety of FPGA-based platforms. Implementation and DSE results for two case studies from the different application fields of synthetic aperture radar image processing and interference alignment in communication systems are presented.     

Real-Time Embedded Software Design for Mobile and Ubiquitous Systems

Currently available application frameworks that target at the automatic design of real-time embedded software are poor in integrating functional and non-functional requirements for mobile and ubiquitous systems. In this work, we present the internal architecture and design flow of a newly proposed framework called Verifiable Embedded Real-Time Application Framework (VERTAF), which integrates three techniques namely software component-based reuse, formal synthesis, and formal verification. The proposed architecture for VERTAF is component-based which allows plug-and-play for the scheduler and the verifier. The architecture is also easily extensible because reusable hardware and software design components can be added. Application examples developed using VERTAF demonstrate significantly reduced relative design effort, which shows how high-level reuse of software components combined with automatic synthesis and verification increases design productivity.     

Applying formal methods within structured development

The introduction and use of formal (mathematically based) specification in substantial systems development has been hampered by the additional burdens it places on practitioners. BT and Leeds Metropolitan University have developed a framework for the gradual introduction of formal specification starting with its use as a review technique, applied to a standard range of systems development deliverables such as data and process models. The benefits of this approach are immediate and can also be more extensive. The paper describes the philosophy behind the general approach, offers an example of applying the Rigorous Review Technique, and summarises the benefits that can accrue     

基于DSP的固态放大链控保系统设计

固态放大链控保系统承担着雷达功率放大系统工作状态和技术参数的监视、调节、控制和保护任务。本文分别从硬件和软件两个层次,描述了基于TMS320F28335型数字信号处理器和EPM1270T14416硬件可编程逻辑器件的雷达固态放大链控保系统的设计和实现,深入地阐述了硬件系统结构,以及功率衰减控制、调制脉冲保护和功放双工切换的软件实现。目前,该控保系统已在多种型号雷达的固态放大链中得到成功应用。     

Matisse: A System-on-Chip Design Methodology Emphasizing Dynamic Memory Management

MATISSE is a design environment intended for developing systems characterized by a tight interaction between control and data-flow behavior, intensive data storage and transfer, and stringent real-time requirements. Matisse bridges the gap from a system specification, using a concurrent object-oriented language, to an optimized embedded single-chip hardware/software implementation. Matisse supports stepwise exploration and refinement of dynamic memory management, memory architecture exploration, and gradual incorporation of timing constraints before going to traditional tools for hardware synthesis, software compilation, and inter-processor communication synthesis. With this approach, specifications of embedded systems can be written in a high-level programming language using data abstraction. Application of MATISSE on telecom protocol processing systems in the ATM area shows significant improvements in area usage and power consumption.     

A System-Based Approach to the Formal Development of Embedded Controllers for a Railway

We describe a formal approach to the development of embedded controllers for a railway. The approach starts with a system-level specification modeling the system under control and the desired control behavior. Correctness-preserving refinement is then used to add more and more implementation detail to the models and to decompose the models into sub-systems to arrive at models of individual controllers. The B Method is used as the formal notation and methodology.     

Technology '88: design automation

Developments during 1987 are reviewed. These include hardware improvements, the proliferation of personal computers hosting CAE programs, the growing need for open systems, the refinement of standards, and the profusion of applications software. An expert opinion is offered by Donald E. Thomas, professor of electrical and computer engineering at Carnegie Mellon University, who outlines the major trends as he sees them     

A smart software radio: concept development and demonstration

A testbed system was developed for smart networking radio algorithms. The associated modular software environment and Phase I hardware testbed are described. It provides the framework for the development of advanced processing algorithms, adaptive multirate systems, and operational radio algorithms and modules. Modular software radio technology allows for the insertion of new algorithms, the quantitative characterization of waveform performance, and the separation of the waveform definition from the details of the implementation to enhance portability. The testbed is representative of SPEAKeasy II-class open architecture software radios. The FLIPWAVE spread-spectrum modem invented at the US Air Force Research Laboratory (AFRL) was developed and evaluated using this testbed. The waveform is presented with experimental results. A unique feature of this modem is a new single-channel quadraphase differential RAKE receiver processor, which illustrates the contributions of the testbed toward the flexibility and portability of novel modems     

UML状态机到B形式化规约的转换

文章研究在高可信软件工程中集成形式化方法。以软件设计的UML状态机模型为起点．将其转换为B形式化模型，然后在B工具环境中遵循B方法的精化原则和正确性验证方法，开发出可靠的实现模型。提出一套从UML状态机到B形式化规约的转换规则，涵盖UML基本状态图、分层状态图和并发状态图。实例分析表明．这套转换规则行之有效。