Compact MOS Implementation of a Reaction-Diffusion CNN

A biologically inspired single layer cellular neural network (CNN) with trigger wave formation capability is presented. A novel compact MOS cell circuit is proposed which exhibits a third order I-V characteristic with negative differential resistance (NDR). Certain D.C. characteristics of both the proposed cell and the network are described and corresponding theoretical estimations are presented. It is shown that the CNN formed by resistive coupling of these cells has very low complexity and realizes a reaction-diffusion system. The dynamical network behavior is demonstrated by transient simulations of a 2D cell array at the circuit level.Koray Karahalilolu received the B.Sc., M.Sc., and Ph.D. degrees in electrical engineering from Boaziçi University, Istanbul, Turkey, in 1993, 1996, and 2002, respectively.Currently he is a Research Assistant Professor with the Department of Electrical Engineering, University of Nebraska, Lincoln. He also worked as a teaching assistant with the Department of Electrical and Electronics Engineering at Boaziçi University.His research interests include VLSI neural networks, device modeling and simulation, analog circuits and systems, and nanodevice system applications.Sina Balkr received the B.S. degree in electrical engineering from Boaziçi University, Istanbul, Turkey, in 1987, and the M.S. and Ph.D. degrees in electrical engineering from Northwestern University, Evanston, IL, in 1989 and 1992, respectively.Between August 1992 and August 1998, he was with the Department of Electrical and Electronics Engineering, Boaziçi University, as an Assistant and Associate Professor. Currently, he is with the Department of Electrical Engineering, University of Nebraska-Lincoln. His research interests include CAD of VLSI systems, analog VLSI design automation, and focal-plane computation arrays for image processing.     

An FPGA Based Coprocessor for GLCM and Haralick Texture Features and their Application in Prostate Cancer Classification

Grey Level Co-occurrence Matrix (GLCM), one of the best known tool for texture analysis, estimates image properties related to second-order statistics. These image properties commonly known as Haralick texture features can be used for image classification, image segmentation, and remote sensing applications. However, their computations are highly intensive especially for very large images such as medical ones. Therefore, methods to accelerate their computations are highly desired. This paper proposes the use of programmable hardware to accelerate the calculation of GLCM and Haralick texture features. Further, as an example of the speedup offered by programmable logic, a multispectral computer vision system for automatic diagnosis of prostatic cancer has been implemented. The performance is then compared against a microprocessor based solution.Muhammad Atif Tahir received a BE degree in Computer Systems Engineering from NED University of Eng. and Tech. Karachi, Pakistan, and an MSc in Computer Engineering from KFUPM, Dhahran, Saudi Arabia. He is currently a PhD research student in School of Computer Science at Queens University Belfast, UK. His main research interests are Custom Computing using FPGAs, Image/Signal Processing, Pattern Recognition, QoS Routing and Optimization heuristics.Ahmed Bouridane obtained an Ingéniorat dEtat degree in Electronics from the National Polytechnic School of Algiers ENP, an MPhil degree in VLSI design for Signal Processing from the University of Newcastle Upon Tyne (UK) and a PhD degree in Computer Vision from the University of Nottingham (UK). Dr A Bouridane held several positions in R&D before joining Queens University Belfast where he is now a Reader in Computer Science. His research interests are in High Performance Image/Signal Processing, Image/Video Watermarking, Custom Computing using FPGAs, Computer Vision and High Performance Architectures for Image/Signal Processing.Fatih Kurugollu received his B.Sc, M.Sc. and Ph.D degree in computer science from the Istanbul Technical University, Istanbul, Turkey in 1989, 1994 aand 2000, respectively. He is currently a lecturer in Computer Science at Queens University, Belfast (UK). His research interest include soft computing for image and video object segmentation, hardware architectures for image and video applications and image watermarking.     

Mobile Phone Antenna Performance and Power Absorption in Terms of Handset Size and Distance from User’s Head

In this work numerical simulation and measurements of three-dimensional radiation patterns of a mobile handset model in the presence of a human head phantom were performed at 1800 MHz. Based on theoretical and experimental results, the influence of the human head on the radiation efficiency of the handset has been investigated as a function of the handset size and the distance between the head and the handset during its operation. Furthermore, the relative amount of the electromagnetic power absorbed in the head has been obtained. It was found that significant reduction of the absorbed power (about 50%) with proportional increment of the handset radiation efficiency could be achieved by moving the phone for 1 cm only away from the head. Agreement between theoretical and experimental results was found to be very good.Theodore Zervos was born in Athens, Greece, on October 5, 1978. He received the diploma in Electrical & Computer Engineering from the University of Patras, Patras, Greece, in 2001. He is currently a Postgraduate Student at the Laboratory of Electromagnetics, Department of Electrical & Computer Engineering, University of Patras. He is also a doctoral scholar at the Mobile Communications Laboratory of the Institute of Informatics and Telecommunications of NCSR Demokritos, Athens. His research interests include electromagnetic modelling, EM radiation measurements and interaction between the human body and mobile handsets antenna. Dipl. T. Zervos is a Member of the Technical Chamber of Greece. In June 2002, his thesis received the 2nd Award of Excellence in Telecommunications from Ericsson.Antonis Alexandridis (1962) is senior researcher in the Institute of informatics and Telecommunications (IIT) of Greek National Research Centre (NCSR) Demokritos. He received the diploma in Electrical Engineering from Technical University ofPatras, Greece (1985), and the Ph.D. degree from the same University (1992). From 1993 he is working in the Mobile Communications Lab of NCSR. Since 1999 he is responsible for the operation of the RF Anechoic Chamber of the IIT. His current interests include mobile communications, propagation models, spread spectrum systems and CDMA techniques, EMC measurements, human exposure to EM fields, interaction between human body and mobile terminals antennas and smart antennas.Vladimir V. Petrovic was born in 1965 in Belgrade, Serbia. He received the B.Sc., M.Sc., and D.Sc., degrees from the University of Belgrade, Serbia and Montenegro in 1989, 1993, and 1996, respectively. He joined the Faculty of Electrical Engineering, University of Belgrade in 1990, where at present he is an Assistant Professor in Electromagnetics and Fundamentals of Electrical Engineering. He is a co-author of a chapter in a monograph, a software package AWAS 2.0 (Artech House – Boston, London, 2002) and several journal and conference articles. His research interests are in numerical electromagnetics, especially in radiation and propagation problems in layered media.Kostas Dangakis was born in Kavala, Greece, in 1950. He received his Diploma in Electrical Engineering from NTUA (Athens, 1973) and his Ph.D. on Digital Modulation/Data Transmission from Techn. Univ. of Patras, Dept. of Electrical Engineering (1984). Since 1977, he has worked at the Inst. of Inform. & Telecom. (IIT) of NCSR Demokritos, in projects related to voice/data/video signal encryption, synchronisation techniques in TDM systems, digital modulation techniques/data transmission, Spread Spectrum/CDMA techniques, mobile communications, conformance testing (DECT, ERMES), radio propagation, channel characterization and antennas. He is research director at IIT and has been project leader of several R & D projects.Branko M. Kolundzija Antonije R. Djordjevic was born in Belgrade, Yugoslavia, on April 28, 1952. He received the B.Sc., M.Sc., and D.Sc. degrees from the Faculty of Electrical Engineering, University of Belgrade, in 1975, 1977, and 1979, respectively. In 1975, he joined the School of Electrical Engineering, University of Belgrade, as a Teaching Assistant. He was promoted to an Assistant Professor, Associate Professor, and Professor, in 1982, 1988, and 1992, respectively. In 1983, he was a Visiting Associate Professor at Rochester Institute of Technology, Rochester, NY. Since 1992, he has also been an Adjunct Scholar with Syracuse University, Syracuse, NY. In 1997, he was elected a Corresponding Member of the Serbian Academy of Sciences and Arts. His main area of interest is numerical electromagnetics, in particular applied to fast digital signal interconnects, wire and surface antennas, microwave passive circuits, and electromagnetic-compatibility problems.C. Soras received both his diploma and Ph.D. in electrical engineering from the University of Patras, Patras, Greece, in 1981 and 1989 respectively. He was a Lecturer in the Laboratory of Electromagnetics of the Electrical and Computer Engineering department of the University of Patras in Greece from 1991 to 2001, where currently serves as an Assistant Professor. He is teaching the basic electromagnetic courses and at the senior undergraduate / graduate level computational electromagnetics. His current research interests focus on computational electromagnetics, multiple element antennas for diversity and MIMO terminal devices and indoor radio wave propagation. Prof. Soras is a member of IEEE, Applied Computational Electromagnetics Society and the Technical Chamber of Greece.     

A Crystal-Based Low-Voltage All-Digital Programmable Ring Oscillator

We have designed and implemented a flexible programmable multi-channel digitally-controlled oscillator (MDCO) on an Altera MAX9400 Complex Programmable Logic Device (CPLD) chip. Based on elaborate experiments with the system, we have developed techniques by which to improve its linearity, resolution and stability in an improved MDCO design. This new architecture is programmable to oscillate from 0 Hz to a maximum that is determined by the oscillator master processing clock and the technology limitations. As crystal-based-programmable-delay cells (CBPDC) control its dominant propagation delay, the oscillator frequency thermal drift and jitter are reduced.In a complementary parallel development, to design high-speed and low-power sub-systems for high-speed applications, we have designed high-speed DCO and MDCOs by using the parameters of TSMC 0.25 um CMOS process with level 49 HSPICE models. At 3.3 Volts, the oscillation frequency has been increased up to 315 MHz in our ASIC MDCO design by using dynamic high-speed data flip-flops. In terms of specific applications, this architecture is suitable for digital wireless transceivers that use different bands for their transmit and receive modes, such as GSM and DECT. Yet to further enhance the operation of our DCOs, we have developed a new design technique by which to allow these blocks to operate at extremely low supply voltages. We have named this after IBMs work (Assaderaghi et al., IEDM Transactions, vol. 44, 414–422, March 1997) as DTMOS-like design style. Here, we use gate-bulk connected PMOS devices each in a separate Nwell to bring the PMOS-device threshold voltage further lower for operation with one Volt and below supplies. A wide-band 123 MHz, 0.6 mW@ 1 V DCO core is designed and simulated in the same 0.25 um CMOS process.Seyed Reza Abdollahi was born in Sary, I. R. of Iran, in 1974. He received the B.S. degree in electronics engineering from Isfahan University of Technology, Isfahan, and M.Sc. degree in electronics engineering from the University of Tehran, I. R. of Iran, in 1997 and 2000, respectively. He has joined VLSI Circuits and Systems Lab. of Electrical and Computer Engineering Department of the University of Tehran since 1997, where he has worked on digital wireless communication integrated circuits. He is currently involved in the development of low-power communication circuits for battery-operated systems.Sied Mehdi Fakhraie was born in Dezfoul, Iran, in 1960. He received his M.Sc. degree in electronics from the University of Tehran, Tehran, Iran, in 1989 an the Ph.D. degree in electrical and computer engineering from the University of Toronto, Toronto, ON, Canada in 1995. Since 1995, he has been with the Department of Electrical and Computer Engineering, University of Tehran, where he is now an Associate Professor. He has been the founder of the VLSI Circuits and Systems Laboratory and is now Director of Silicon Intelligence and VLSI Signal Processing Laboratory. From September 2000 to April 2003, he was with Valence Semiconductor Inc. and has worked in Dubai, UAE, and Markham, Canada offices of Valence as Director of ASIC/SoC Design and also technical lead of Integrated Broadband Gateway and Family Radio System baseband processors. During the summers of 1998, 1999, and 2000, he was a visiting professor at the University of Toronto, where he continued his work on efficient implementation of artificial neural networks. He is coauthor of the book VLSI-Compatible Implementation of Artificial Neural Networks (Boston, MA: Kluwer, 1997). He has also published more than 70 reviewed conference and journal papers. He has worked on many industrial IC design projects including design of network processors and home gateway access devices, DSL modems, pagers, and one- and two-way wireless messaging systems, and digital signal processors for personal and mobile communication devices. His research interests include system design and ASIC implementation of integrated systems, novel techniques for high-speed digital circuit design, and system-integration and efficient VLSI implementation of intelligent systems.Mahmoud Kamarei received his M.Sc. degree in electrical engineering from the University of Tehran, Iran in 1979, his CES in telecommunications from the Ecole National Superieure des Telecommunications of Paris, France in 1981, his Diplome d Etudes Approfondies and his Ph.D. from Institute National Polytechnique de Grenoble (INPG), France, both in electronics, in 1982 and in 1985. Since 1982, he has been a researcher at INPGs Laboratoire de lElectromagnetisme, Micro–Ondes et Optoelectronique. Dr. Kamarei also was Maiter de Conferences at J. Fourier University of Grenoble until September 1991. He returned to Iran in 1991. He works as a Professor and Associate Dean in Research of the Faculty of Engineering, University of Tehran, Iran.     

A Prototype Processing-In-Memory (PIM) Chip for the Data-Intensive Architecture (DIVA) System

The Data-Intensive Architecture (DIVA) system employs Processing-In-Memory (PIM) chips as smart-memory coprocessors. This architecture exploits inherent memory bandwidth both on chip and across the system to target several classes of bandwidth-limited applications, including multimedia applications and pointer-based and sparse-matrix computations. The DIVA project has built a prototype development system using PIM chips in place of standard DRAMs to demonstrate these concepts. We have recently ported several demonstration kernels to this platform and have exhibited a speedup of 35X on a matrix transpose operation.This paper focuses on the 32-bit scalar and 256-bit WideWord integer processing components of the first DIVA prototype PIM chip, which was fabricated in TSMC 0.18 m technology. In conjunction with other publications, this paper demonstrates that impressive gains can be achieved with very little smart logic added to memory devices. A second PIM prototype that includes WideWord floating-point capability is scheduled to tape out in August 2003.Jeffrey Draper is a Research Assistant Professor in the Department of Electrical Engineering at the University of Southern California. He holds this appointment in conjunction with a Project Leader position at the Information Sciences Institute of the University of Southern California. Dr. Drapers research group has participated in many DARPA-sponsored large-scale VLSI development efforts. He is a member of the IEEE Computer Society and has conducted research in the areas of processing-in-memory architectures, thermal management, VLSI, interconnection networks, and modeling/performance evaluation. Dr. Draper received a BSEE from Texas A&M University and an MS and PhD from the University of Texas at Austin.J. Tim Barrett is a Senior Electrical Engineer at the Information Sciences Institute of the University of Southern California. Mr. Barrett has managed, designed and implemented the hardware, low-level software and integration of many computer systems. Applications of these systems include scalable supercomputers at USC Information Sciences Institute, the long distance telephone switch at AT&T Bell Labs, building energy management at Barber-Colman Company, and laser entertainment performance instruments at Aura Technologies and Laser Images Inc. He is a member of IEEE Solid State Circuits Society and received his MSCS from the University of Illinois Chicago and BSEE from the University of Iowa.Jeff Sondeen is a Research Associate at the Information Sciences Institute of the University of Southern California, where he supports and maintains CAD technology files, libraries, and tools for implementing VLSI designs. Previously he has worked at Silicon Compilers and Hewlett-Packard in CAD tool and test chip development. He received an MSEE from the University of Michigan.Sumit Mediratta is currently pursuing a PhD in Electrical Engineering at the University of Southern California. He received a Bachelor of Engineering degree in Electronics and Telecommunication from the Shri Govind Ram Sekseria Institute of Technology and Science, India. His research interests include interconnection networks, VLSI, processing-in-memory architectures, high-speed data communication and synchronization techniques and network interfaces for high-performance architectures.Chang Woo Kang received a BS in electrical engineering from Chung-ang University, Seoul, South Korea, in 1997 and an MS in electrical engineering from the University of Southern California, Los Angeles, in 1999. He is currently pursuing a PhD in electrical engineering at the University of Southern California. His research includes VLSI system design and algorithms for low-power logic synthesis and physical design.Ihn Kim is a PhD student in the Department of Electrical Engineering at the University of Southern California. He is also a Staff Engineer at QLogic. His research interests include user-level network interface, network processor architectures, and modeling/performance evaluation of system area networks. He is a member of the IEEE Computer Society. He received an MS at KAIST (Korea Advanced Institute of Science and Technology).Gokhan Daglikoca is an Application Engineer at Cadence Design Systems, Inc, where he specializes in High-Performance ASIC and Microprocessor Design Methodologies. He is a member of IEEE. Gokhan Daglikoca received a BS from Istanbul Technical University and an MS from the University of Southern California.     

High-Radix Logarithm with Selection by Rounding: Algorithm and Implementation

A high-radix digit-recurrence algorithm for the computation of the logarithm, and an analysis of the tradeoffs between area and speed for its implementation, are presented in this paper. Selection by rounding is used in iterations j 2, and by table look-up in the first iteration. A sequential architecture is proposed, and estimates of the execution time and hardware requirements are obtained for n = 16, 24, 32, 53 and 64 bits of precision and for radix values from r = 8 to r = 1024. These estimates are obtained according to an approximate model for the delay and area of the main logic blocks. We show that the most efficient implementations are obtained for radices ranging from r = 32 to r = 256, reducing the execution time by half with respect to a radix-4 implementation with redundant arithmetic.Jose-Alejandro Piñeiro was born in Domayo, Spain. He received the Ph.D. degree in Computer Engineering in 2003, and the M.Sc. degree (1999) and B.Sc. degree (1998) in Physics (Electronics), from the University of Santiago de Compostela, Spain. Since 2004, he has been with Intel Barcelona Research Center, Intel Labs-UPC, whose research focuses on new microarchitectural paradigms and code generation techniques for IA-32, EM64T and IPF families. His research interests are also in the area of computer arithmetic, VLSI design, computer graphics and numerical processors.Milo D. Ercegovac is a Professor and Chair in the UCLA Computer Science Department. He earned his MS (72) and Ph.D. (75) in computer science from the University of Illinois, Urbana-Champaign, and BS in electrical engineering (65) from the University of Belgrade, Yugoslavia. Dr. Ercegovac specializes in research and teaching in digital arithmetic, digital design, and computer system architecture. His research contributions have been extensively published in journals and conference proceedings. He is a coauthor of two textbooks on digital design and of a monograph in the area of digital arithmetic. Dr. Ercegovac has been involved in organizing the IEEE Symposia on Computer Arithmetic since 1978. He served as an editor of the IEEE Transactions on Computers and as a subject area editor for the Journal of Parallel and Distributed Computing. Dr. Ercegovac is a senior member of the IEEE Computer Society and a member of the ACM.Javier D. Bruguera received the B.S. degree in Physics and the Ph.D. degree from the University of Santiago de Compostela (Spain) in 1984 and 1989, respectively. Currently, he is a professor in the Department of Electronic and Computer Engineering at the University of Santiago de Compostela. Previously, he was an assistant professor in the Department of Electrical, Electronic and Computer Engineering at the University of Oviedo, Spain, and an assistant professor in the Department of Electronic Engineering at the University of A Coruña, Spain. He was a visiting researcher in the Application Center of Microelectronics at Siemens in Munich, Germany, and in the Department of Electrical Engineering and Computer Science at the University of California, Irvine. Dr. Brugueras primary research interests are in the area of computer arithmetic, processor design, digital design for signal and image processing and parallel architectures.     

Strongly Consistent Access Algorithms for Wireless Data Networks

In wireless data networks such as the WAP systems, the cached data may be time-sensitive and strong consistency must be maintained (i.e., the data presented to the user at the WAP handset must be the same as that in the origin server). In this paper, we study the cached data access algorithms in such systems. Two caching algorithms are investigated. In Algorithm I, Pull-Each-Read, whenever a data access occurs, the client always asks the server whether the cached entry in the client is valid or not. In Algorithm II, Callback, the server always invalidates the cached entry in the client whenever an update occurs. Analytic models are proposed to evaluate the performance of these algorithms. Our studies show that Algorithm II outperforms Algorithm I if the data access rate is high and the access pattern is irregular. We also design an adaptive mechanism to effectively switch between the two algorithms to take advantages of both algorithms. We also apply the single-level cached data access algorithms for the multi-level cache hierarchy. Our study indicates that with appropriate arrangement, strongly consistent cached data access for wireless Internet (such as WAP) can be efficiently supported.Yuguang Fang received the B.S. and M.S. degrees in Mathematics from Qufu Normal University, Qufu, Shandong, China, in 1984 and 1987, respectively, a Ph.D degree from Department of Systems, Control and Industrial Engineering at Case Western Reserve University, Cleveland, Ohio, in January 1994, and a Ph.D degree from Department of Electrical and Computer Engineering at Boston University, Massachusetts, in May 1997.From 1987 to 1988, he held research and teaching positions in both Department of Mathematics and the Institute of Automation at Qufu Normal University. He held a post-doctoral position in Department of Electrical and Computer Engineering at Boston University from June 1994 to August 1995. From June 1997 to July 1998, he was a Visiting Assistant Professor in Department of Electrical Engineering at the University of Texas at Dallas. From July 1998 to May 2000, he was an Assistant Professor in the Department of Electrical and Computer Engineering at New Jersey Institute of Technology, Newark, New Jersey. From May 2000 to July 2003, he was an Assistant Professor in the Department of Electrical and Computer Engineering at University of Florida, Gainesville, Florida, where he has been an Associate Professor since August 2003. His research interests span many areas including wireless networks, mobile computing, mobile communications, automatic control, and neural networks. He has published over ninety papers in refereed professional journals and conferences. He received the National Science Foundation Faculty Early Career Development Award in 2001 and the Office of Naval Research Young Investigator Award in 2002. He is listed in Marquis Whos Who in Science and Engineering, Whos Who in America and Whos Who in World.Dr. Fang has actively engaged in many professional activities. He is a senior member of the IEEE and a member of the ACM. He is an Editor for IEEE Transactions on Communications, an Editor for IEEE Transactions on Wireless Communications, an Editor for ACM Wireless Networks, an Area Editor for ACM Mobile Computing and Communications Review, an Associate Editor for Wiley International Journal on Wireless Communications and Mobile Computing, and an Editor for IEEE Wireless Communications. He was an Editor for IEEE Journal on Selected Areas in Communications: Wireless Communications Series and the feature editor for Scanning the Literature in IEEE Wireless Communications (formerly IEEE Personal Communications). He has also actively involved with many professional conferences such as ACM MobiCom02, ACM MobiCom01, IEEE INFOCOM04, INFOCOM03, INFOCOM00, INFOCOM98, IEEE WCNC02, WCNC00 (Technical Program Vice-Chair), WCNC99, and International Conference on Computer Communications and Networking (IC3N98) (Technical Program Vice-Chair).Yi-Bing Lin received his BSEE degree from National Cheng Kung University in 1983, and his Ph.D. degree in Computer Science from the University of Washington in 1990. From 1990 to 1995, he was with the Applied Research Area at Bell Communications Research (Bellcore), Morristown, NJ. In 1995, he was appointed as a professor of Department of Computer Science and Information Engineering (CSIE), National Chiao Tung University (NCTU). In 1996, he was appointed as Deputy Director of Microelectronics and Information Systems Research Center, NCTU. During 1997-1999, he was elected as Chairman of CSIE, NCTU. His current research interests include design and analysis of personal communications services network, mobile computing, distributed simulation, and performance modeling. Dr. Lin has published over 150 journal articles and more than 200 conference papers.Dr. Lin is a senior technical editor of IEEE Network, an editor of IEEE Trans. on Wireless Communications, an associate editor of IEEE Trans. on Vehicular Technology, an associate editor of IEEE Communications Survey and Tutorials, an editor of IEEE Personal Communications Magazine, an editor of Computer Networks, an area editor of ACM Mobile Computing and Communication Review, a columnist of ACM Simulation Digest, an editor of International Journal of Communications Systems, an editor of ACM/Baltzer Wireless Networks, an editor of Computer Simulation Modeling and Analysis, an editor of Journal of Information Science and Engineering, Program Chair for the 8th Workshop on Distributed and Parallel Simulation, General Chair for the 9th Workshop on Distributed and Parallel Simulation. Program Chair for the 2nd International Mobile Computing Conference, Guest Editor for the ACM/Baltzer MONET special issue on Personal Communications, a Guest Editor for IEEE Transactions on Computers special issue on Mobile Computing, a Guest Editor for IEEE Transactions on Computers special issue on Wireless Internet, and a Guest Editor for IEEE Communications Magazine special issue on Active, Programmable, and Mobile Code Networking. Lin is the author of the book Wireless and Mobile Network Architecture (co-author with Imrich Chlamtac; published by John Wiley & Sons). Lin received 1998, 2000 and 2002 Outstanding Research Awards from National Science Council, ROC, and 1998 Outstanding Youth Electrical Engineer Award from CIEE, ROC. He also received the NCTU Outstanding Teaching Award in 2002. Lin is an Adjunct Research Fellow of Academia Sinica, and is Chair Professor of Providence University. Lin serves as consultant of many telecommunications companies including FarEasTone and Chung Hwa Telecom. Lin is an IEEE Fellow.     

Overcoming Test Setup Limitations by Applying Model-Based Testing to High-Precision ADCs

Test setup limitations, such as noise and parasitics, increasingly impede repeatable and accurate linearity measurements in high-volume production testing of high-precision data converters. Model-based testing has been shown to reduce the adverse effects of noise [14].In this work, we present two enhancements of the linear model-based approach: one is a change of the modeling strategy in order to account for measurement errors induced, for example, by parasitics associated with the device contactor, and another is a Design-for-Test feature that significantly improves the models ability to reduce the effect of measurement noise on the accuracy of the test outcome.The authors acknowledge the support by Analog Devices B.V., Limerick, Ireland and Enterprise Ireland under the Strategic Research Grant ST/00/26.Carsten Wegener has been awarded the academic degree of a Diplom-Ingenieur in Electronic Circuits and Systems by the Technical University of Dresden, Germany, in 1997. During a period of two years, 1996 through 1998, he attended the lecture series for the Vordiplom in Mathematics at Humboldt-University at Berlin, Germany.In Spring 1998, he moved permanently to Ireland, where he started to work with the Test Department of Analog Devices B.V. in Limerick. In Autumn of the same year he took up his PhD-studies with Dr M.P. Kennedy in the area of model-based testing of mixed-signal integrated circuits. He has been awarded the PhD degree by the National University of Ireland in December 2003.He has contributed to numerous conferences, publishing works in areas of nonlinear oscillator dynamics and mixed-signal testing. In Ireland, he has taught MATLAB courses to design and test engineers at Analog Devices B.V., and graduate courses on Digital Design-for-Test and Mixed-signal Test and Testability at the Department of Microelectronic Engineering, University College Cork.Michael Peter Kennedy received the B.E. degree in electronics from the National University of Ireland in 1984, and the M.S. and Ph.D. degrees from the University of California at Berkeley (UC Berkeley) in 1987 and 1991, respectively, for his contributions to the study of neural networks and nonlinear dynamics.He worked as a Design Engineer with Philips Electronics, a Postdoctoral Research Engineer with the Electronics Research Laboratory, UC Berkeley, and as a Professeur Invité with the EPFL, Switzerland. He returned to University College Dublin in 1992 as a College Lecturer in the Department of Electronic and Electrical Engineering. He was appointed Professor of Microelectronic Engineering at University College Cork in 2000.He has published 200 articles in the area of nonlinear circuits and systems and has taught courses on nonlinear dynamics and chaos. His research interests are nonlinear circuits and systems for applications in communications and signal processing. Since 1995 he has been active in research into algorithms for mixed-signal testing. Since 1994, he has led international basic and applied research projects on chaotic communications valued at over USD 2M.Dr. Kennedy was elected a Fellow of the IEEE in 1998. He received the Third Millenium Medal from the IEEE in 2000, the IEEE Circuits and Systems Society Golden Jubilee Medal, and the inaugural Parsons Award for excellence in Engineering Sciences from the Royal Irish Academy in 2001.     

A Layer 3 Movement Detection Algorithm Driving Handovers in Mobile IP

The evolution and the spreading of wireless access technology and the consequent increase of user mobility will make handover procedures critical for the provision of Quality of Service in the next generation wireless Internet. Often, layer 3 handovers are supposed to be driven by access layer procedures. In this way, the movement detection delay can be reduced, but at the expenses of making the Mobile IP protocol dependent of lower layer implementations. Furthermore, this approach may not be effective when users roam among heterogeneous networks. Nevertheless, movement detection algorithms, which operate at the Mobile IP layer, imply appreciable delays, usually intolerable for real time services.In this paper, we propose a Mobile IP handover scheme based on a novel movement detection algorithm at layer 3, able to timely manage migrations by exploiting advertisements losses, combined with a two-timers mechanism.We analyze the performance of our algorithm in terms of handover delay and throughput, and we show that our solution is able to decrease the movement detection delay as much as 47% with respect to other literature solutions that pursue similar approaches. In addition, this feature implies also higher values of the throughput seen by the TCP layer.This work has been carried out in the framework of the FIRB Project PRIMO, co-financed by the Italian Ministry for Education, Higher Education and Research (MIUR).Nicola Blefari Melazzi received his Laurea degree in Electrical Engineering in 1989, magna cum laude with publication of his thesis, and earned the Dottore di Ricerca (Ph.D.) in Information and Communication Engineering in 1994, both at the University of Roma La Sapienza, Italy. In 1993 he joined the University of Roma Tor Vergata, as an Assistant Professor. From 1998 to 2002 he has been an Associate Professor at the University of Perugia. In 2002 he came back to the University of Roma Tor Vergata as a Full Professor of Telecommunications.Dr. Blefari-Melazzi has been involved in consulting activities and research projects, including standardization and performance evaluation work. His research projects have been funded by the Italian Ministry of Education, University and Research, by the Italian National Research Council, by industries, by the European Union and by the European Space Agency. He also reviewed research proposals and research projects.Dr. Blefari-Melazzi served as reviewer, TPC member, session chair and guest-editor to IEEE conferences and journals.His research interests include the performance evaluation, design and control of broadband integrated networks, wireless LANs and satellite networks. He is also conducting research on multimedia traffic modeling, mobile and personal communications, quality of service guarantees and real time services support in the Internet.Mauro Femminella received his Laurea degree in Electronic Engineering in 1999, magna cum laude with publication of his thesis, and earned the Ph.D. degree in Electronic Engineering in 2003, both at the University of Perugia, Italy. He was Consulting Engineer for the University of Perugia, and for the consortia CoRiTel and RadioLabs. Actually he holds a position as contract researcher at the Department of Information and Electronic Engineering at the University of Perugia.He was involved in a number of research projects co-funded by the European Union (programs ACTS and IST), by the Italian Ministry for Education, Higher Education and Research (MIUR), and by the European Space Agency (ESA).He is co-author of a number of papers in international conferences and journals.His research interests focus on design and performance evaluation of satellite networks, content delivery networks, IP quality of service and IP mobility.Fabio Pugini received his laurea degree (M.S.) in Electronic Engineering (magna cum laude) in 2000 from University of Rome La Sapienza. He was with the INFOCOM Dept. of the same University during 2001 and 2002 as Ph.D. student in Computer Science. His main research interests regarded Mobility issues and QoS provision in IP networks. He was consulting engineer for the DIEI Department of the University of Perugia and was involved in the following European Projects: SUITED, WHYLESS.COM, FIFTH. In 2002 he received his M.B.A. degree from University of Rome Tor Vergata. He worked as a system analyst in MBDA Missile Defense Systems and currently he is with McKinsey & Company as a Junior Associate.     

IEEE-Compliant IDCT on FPGA-Augmented TriMedia

This paper presents a TriMedia processor extended with an IDCT reconfigurable design, and assesses the performance gain such an extension has when performing MPEG-2 decoding. We first propose the skeleton of an extension of the TriMedia architecture, which consists of a Field-Programmable Gate Array (FPGA)-based Reconfigurable Functional Unit (RFU), a Configuration Unit managing the reconfiguration of the RFU, and their associated instructions. Then, we address the computation of the 8 × 8 (2-D) IDCT on such extended TriMedia and propose a scheme to implement the 1-D IDCT operation on the RFU. When mapped on an ACEX EP1K100 FPGA from Altera, the proposed 1-D IDCT exhibits a latency of 16 and a recovery of 2 TriMedia@200 MHz cycles, and occupies 45% of the logic cells of the device. By configuring the 1-D IDCT on the RFU at application launch-time, the IEEE-compliant 2-D IDCT can be computed with the throughput of 1/32 IDCT/cycle. This figure translates to an improvement over the standard TriMedia of more than 40% in terms of computing time when 2-D IDCT is carried out in the framework of MPEG-2 decoding. Finally, the proposed reconfigurable IDCT is compared to a number of existing designs.Mihai Sima was born in Bucharest, Romania. He received the MS degree in Electrical Engineering from Politehnica University of Bucharest, and the Ph.D. degree in Electrical Engineering from Delft University of Technology, The Netherlands. He had been with the Microelectronics Company in Bucharest for 3 years, where he was involved in instrumentation electronics for integrated circuit testing. Subsequently, he joined the Telecommunications Department of Politehnica University of Bucharest, where he had been involved in digital signal processing and speech recognition for 6 years. More recently, he had been with the Faculty of Electrical Engineering, Mathematics, and Computer Science, Delft University of Technology, where he worked on reconfigurable architectures for mediaprocessing domain. He is currently an assistant professor with the Department of Electrical and Computer Engineering, University of Victoria, B.C., Canada. His research interests include computer architecture, reconfigurable computing, embedded systems, digital signal processing, and speech recognition.Sorin D. Coofan was born in Mizil, Romania. He received the MS degree in Computer Science from the Politehnica University of Bucharest, Romania, and the Ph.D. degree in Electrical Engineering from Delft University of Technology, The Netherlands. He had worked with the Research & Development Institute for Electronic Components (ICCE) in Bucharest for a decade, being involved in structured design of digital systems, design rule checking of ICs layout, logic and mixed-mode simulation of electronic circuits, testability analysis, and image processing. He is currently an associate professor with the Faculty of Electrical Engineering, Mathematics, and Computer Science, Delft University of Technology, The Netherlands. His research interests include computer arithmetic, parallel architectures, embedded systems, reconfigurable computing, nano-electronics, neural networks, computational geometry, and computer aided design.Jos T.J. van Eijndhoven was born in Roosendaal, The Netherlands. He studied Electrical Engineering at the Eindhoven University of Technology, The Netherlands, obtaining the M.Sc. and Ph.D. degrees in 1981 and 1984, respectively, for a work on piecewise linear circuit simulation. Then, he became a senior research member in the design automation group of the Eindhoven University of Technology. In 1986 he spent a sabbatical period at the IBM Thomas J. Watson Research Laboratory, Yorktown Heights, New York, for research on high level synthesis. In 1998 he joined Philips Research Laboratories in Eindhoven, The Netherlands, to work on the architectural design of programmable multimedia hardware and the associated mapping of media processing applications.Stamatis Vassiliadis was born in Manolates, Samos, Greece. He is a professor with the Faculty of Electrical Engineering, Mathematics, and Computer Science, Delft University of Technology, The Netherlands. He has also served in the faculties of Cornell University, Ithaca, NY, and the State University of New York (S.U.N.Y.), Binghamton, NY.He hadworked for a decade with IBM in the AdvancedWorkstations and Systems laboratory in Austin TX, the Mid-Hudson Valley Laboratory in Poughkeepsie, NY, and the Glendale Laboratory in Endicott, NY. In IBM he was involved in a number of projects regarding computer design, organizations, and architectures and the leadership to advanced research projects. A number of his design and implementation proposals have been implemented in commerciallyavailable systems and processors including the IBM 9370 model 60 computer system, the IBM POWER II, the IBM AS/400 Models 400, 500, and 510, Server Models 40S and 50S, the IBM AS/400 Advanced 36, and the IBM S/390 G4 and G5 computer systems. For his work, he received numerous awards including 23 levels of Publication Achievement Awards, 15 levels of Invention Achievement Awards and an Outstanding Innovation Award for Engineering/Scientific Hardware Design in 1989. In 1990 he has been awarded the highest number of USA patents in IBM, six of his 70 USA patents being rated with the highest patent ranking in IBM.Kees A. Vissers graduated the Delft University of Technology, receiving his M.Sc. in 1980. He started directly with Philips Research Laboratories in Eindhoven where he was involved in highlevel simulation and high-level synthesis. He had been heading the research on hardware/software co-design and system level design for many years, and had a significant contribution to the TriMedia VLIW processor. From 1987 till 1988 he was a visiting researcher at Carnegie Mellon University, Pittsburgh, Pennsylvania, with the group of Don Thomas. He is currently a Research Fellow with University of California at Berkeley, Department of Electrical Engineering and Computer Sciences. His research interests include video processing, embedded media processing systems, and reconfigurable computing.     

VLSI Architecture for Lifting-Based Shape-Adaptive Discrete Wavelet Transform with Odd-Symmetric Filters

In this paper, a VLSI architecture for lifting-based shape-adaptive discrete wavelet transform (SA-DWT) with odd-symmetric filters is proposed. The proposed architecture is comprised of a stage-based boundary extension strategy and the shape-adaptive boundary handling units. The former could reduce the complexity of multiplexers that are introduced to solve the shape-adaptive boundary extension. The latter consists of two multiplexers and can solve the shape-adaptive boundary extension locally without any additional register. Two case studies are presented, including the JPEG 2000 default (9, 7) filter and MPEG-4 default (9, 3) filter. According to comparison results with previous architectures, the efficiency of the proposed architectures is proven.Chao-Tsung Huang was born in Kaohsiung, Taiwan in 1979. He received the B.S. degree from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan in 2001. He is currently working toward the Ph.D. degree at the Graduate Institute of Electronics Engineering, National Taiwan University. His major research interests include VLSI design and implementation for 1-D, 2-D, and 3-D Discrete Wavelet Transform. cthuang@video.ee.ntu.edu.twPo-Chih Tseng was born in Tao-Yuan, Taiwan in 1977. He received the B.S. degree in Electrical and Control Engineering from National Chiao Tung University in 1999 and the M.S. degree in Electrical Engineering from National Taiwan University in 2001. He currently is pursuing the Ph.D. degree at the Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University. His research interests include VLSI design and implementation for signal processing systems, energy-efficient reconfigurable computing for multimedia systems, and power-aware image and video coding systems. pctseng@video.ee.ntu.edu.twLiang-Gee Chen (S84–M86–SM94–F01) received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1979, 1981, and 1986, respectively.In 1988, he joined the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. During 1993–1994, he was a Visiting Consultant in the DSP Research Department, AT&T Bell Labs, Murray Hill, NJ. In 1997, he was a Visiting Scholar of the Department of Electrical Engineering, University of Washington, Seattle. Currently, he is Professor at National Taiwan University, Taipei, Taiwan, R.O.C. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY since 1996, as Associate Editor of the IEEE TRANSACTIONS ON VLSI SYSTEMS since 1999, and as Associate Editor of IEEE TRANSACTIONS CIRCUITS AND SYSTEMS II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of Video Signal Processing Systems. He is also the Associate Editor of the PROCEEDINGS OF THE IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001–2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi. lgchen@video.ee.ntu.edu.tw     

Optimization and Design of a Low Power Switched Current A/D-ΣΔ-Modulator for Voice Band Applications

This paper presents a third order switched current -modulator. The modulator is optimized at the system level for minimum power consumption by careful design of the noise transfer function. A thorough noise analysis of the cascode type current copiers used to implement the modulator, together with a new methodology for evaluating the nonlinear settling behavior is presented. This leads to a new optimization methodology that minimize the power consumption in switched current circuits for given design parameters. The optimization methodology takes process variations into account. The modulator is implemented in a standard 2.4 m CMOS process only using MOS capacitors. For a power supply of 3.3 V the power consumption is approximately 2.5 mW when operating at a sampling rate of 600 kHz. Under these condition the peak SNR it measured to 74.5 dB with a signal band width of 5.5 kHz. Due to internal clamping in the integrators and proper scaling the modulator shows excellent stability properties. In order to compare the performance of the modulator presented in this paper to other -modulators two figure-of-merits (FOMs) are proposed. From these figure-of-merits it is found that the performance of the modulator presented in this paper is significantely higher than the perforamce of other switched current -modulators reported. Also, the figure-of-merits show that the performance is comparable to the performance of reported switched capacitor -modulators.     

High Dynamic Range Design for ΣΔM with Wide Input Ranges

A new design algorithm is introduced to improve the input ranges of Sigma-Delta Modulation (M). Modified digital error correction techniques are proposed and employed to carry out the wide range DAC of a modulator. This design algorithm includes the advantages from both single-bit M and multi-bit M. This paper utilizes a second order lowpass modulator as an explanatory example to demonstrate our design process as well as the performance improvement. The analytical results from a quasilinear model are described to offer a theoretical explanation of the system performance. This algorithm can also be applied to bandpass and MASH architectures.     

Scaling Analysis of On-Chip Power Grid Voltage Variations in Nanometer Scale ULSI

This paper presents a detailed scaling analysis of the power supply distribution network voltage drop in DSM technologies. The effects of chip temperature, electromigration and interconnect technology scaling (including resistivity increase of Cu interconnects due to electron surface scattering and finite barrier thickness) are taken into consideration during this analysis. It is shown that the voltage drop effect in the power/ground (P/G) distribution network increases rapidly with technology scaling, and that using well-known countermeasures such as wire-sizing and/or decoupling capacitor insertion which are typically used in the present design methodologies may be insufficient to limit the voltage fluctuations over the power grid for future technologies. It is also shown that such voltage drops on power supply lines of switching devices in a clock distribution network can introduce significant amount of skew which in turn degrades the signal integrity.This work was done when the author was with the Dept. of EESystems, University of Southern California.Amir H. Ajami received his B.S. degree in electrical engineering from the University of Tehran, Tehran, Iran in 1993. He received his M.S. and Ph.D. degrees in electrical engineering from the University of Southern California, Los Angeles, CA, in 1999 and 2002, respectively.He is currently a member of consulting staff in research and development division at MagmaDesign Automation, Inc., Santa Clara, CA. He has previously held positions at Cadence Design Systems, Inc., andMagma Design Automations, Inc., in 1999 and 2000, respectively. His research interests are in the area of technology scaling issues in high-performance VLSI designs with emphasis on full-chip thermal analysis, thermalaware timing and power optimization methodologies, and signal integrity. He has coauthored several papers on the modeling and analysis of the effects of substrate thermal gradients on performance degradation and development of thermal-aware physical-synthesis optimization algorithms.Dr. Ajami is a member of Association of Computing Machinery (ACM) and IEEE. HE serves on the technical program committee of the 2005 IEEE International Symposium on Quality Electronics Design.Kaustav Banerjee received the Ph.D. degree in electrical engineering and computer sciences from the University of California at Berkeley in 1999. He was with Stanford University, Stanford, CA, from 1999 to 2002 as a Research Associate at the Center for Integrated Systems. In July 2002, he joined the faculty of the Electrical and Computer Engineering Department at the University of California, Santa Barbara, as an Assistant Professor. From February 2002 to August 2002 he was a Visiting Professor at the Circuit Research Labs of Intel in Hillsboro, Oregon. In the past, he has also held summer/visiting positions at Texas Instruments Inc., Dallas, Texas, Fujitsu Labs and the Swiss Federal Institute of Technology (EPFL). His present research interests focus on a wide variety of nanometer scale issues in high-performance VLSI and mixed-signal designs, as well as on circuits and systems issues in emerging nanoelectronics. He is also interested in some exploratory interconnect and circuit architectures including 3-D ICs. At UCSB, Dr. Banerjee mentors several doctoral and masters students. He also co-advises graduate students at Stanford University, University of Illinois at Urbana-Champaign and EPFL-Switzerland. He has co-directed two doctoral dissertations at Stanford University and the University of Southern California. Dr. Banerjee served as Technical Program Chair of the 2002 IEEE International Symposium on Quality Electronic Design (ISQED 02), and is the General Chair of ISQED 05. He also serves or has served on the technical program committees of the IEEE International Electron Devices Meeting, the IEEE International Reliability Physics Symposium, the EOS/ESD Symposium and the ACM International Symposium on Physical Design. His research has been chronicled in over 100 journals and refereed international conference papers and a book chapter. He has also co-edited a book titled Emerging Nanoelectronics: Life with and after CMOS by Kluwer in 2004. Dr. Banerjee has been recognized through the ACM SIGDA Outstanding New Faculty Award (2004) as well as a Best Paper Award at the Design Automation Conference (2001). He is listed in Whos Who in America and Whos Who in Science and Engineering.Massoud Pedram received a B.S. degree in Electrical Engineering from the California Institute of Technology in 1986 and M.S. and Ph.D. degrees in Electrical Engineering and Computer Sciences from the University of California, Berkeley in 1989 and 1991, respectively. He then joined the department of Electrical Engineering, Systems at the University of Southern California where he is currently a professor. Dr. Pedram has served on the technical program committee of a number of conferences, including the Design automation Conference (DAC), Design and Test in Europe Conference (DATE), Asia-Pacific Design automation Conference (ASP-DAC), and International Conference on Computer Aided Design (ICCAD). He served as the Technical Co-chair and General Co-chair of the International Symposium on Low Power Electronics and Design (SLPED) in 1996 and 1997, respectively. He was the Technical Program Chair and the General Chair of the 2002 and 2003 International Symposium on Physical Design. Dr. Pedram has published four books, 60 journal papers, and more than 150 conference papers. His research has received a number of awards including two ICCD Best Paper Awards, a Distinguished Citation from ICCAD, a DAC Best Paper Award, and an IEEE Transactions on VLSI Systems Best Paper Award. He is a recipient of the NSFs Young Investigator Award (1994) and the Presidential Faculty Fellows Award (a.k.a. PECASE Award) (1996).Dr. Pedram is a Fellow of the IEEE, a member of the Board of Governors for the IEEE Circuits and systems Society, an associate editor of the IEEE Transactions on Computer Aided Design, the IEEE Transactions on Circuits and Systems, and the IEEE Circuits and Systems Society Distinguished Lecturer Program Chair. He is also an Advisory Board Member of the ACM Interest Group on Design Automation, and an associate editor of the ACM Transactions on Design Automation of Electronic Systems. His current work focuses on developing computer aided design methodologies and techniques for low power design, synthesis, and physical design. For more information, please go to URL address: .     

Iterative Decoding of Orthogonal Space-Time Coded CPM Systems

We present an iterative decoding/demodulation technique for an orthogonal space-time coded continuous-phase modulation (OST-CPM) system. A low-complexity soft input and soft output (SISO) demodulator is developed based on the bidirectional soft output Viterbi algorithm (BSOVA) for the multiple antennas CPM systems. By taking advantage of the orthogonal structure, the complexity of extrinsic information extraction can be significantly reduced at each iteration.Shengli Fu received the B.S. and M.S. degree in telecommunication engineering from Beijing University of Posts and Telecommunications, Beijing, China, in 1994 and 1997, respectively. In 2000, he enrolled at the Wright State University, Dayton, OH, where he received the M.S. degree in Computer Engineering. He currently pursues his Ph.D. degree in the Department of Electrical and Computer Engineering at the University of Delaware.His research interests include information and coding theory, MIMO wireless communication systems, and acoustic and visual signal processing.Genyuan Wang received B.Sc and MS. degrees in Mathematics from the Shanxi Normal University, Xian, China, in 1985 and 1988, respectively, and his Ph.D. degree in Electrical Engineering from Xidian University, Xian China, in 1998.From July, 1988 to September 1994, he worked at Shanxi Normal University as an Assistant Professor and then an Associate Professor. From September 1994 to May 1998, he worked at Xidian University as a research assistant. Currently, he is Post-Doctoral Fellow at Department of Electrical and Computer Engineering, University of Delaware. His research interests are radar imaging and radar signal processing, adaptive filter, OFDM system, channel equalization and space-time coding.Xiang-Gen Xia (M97,S00) received his B.S. degree in mathematics from Nanjing Normal University, Nanjing, China, and his M.S. degree in mathematics from Nankai University, Tianjin, China, and his Ph.D. degree in Electrical Engineering from the University of Southern California, Los Angeles, in 1983, 1986, and 1992, respectively.He was a Senior/Research Staff Member at Hughes Research Laboratories, Malibu, California, during 1995--1996. In September 1996, he joined the Department of Electrical and Computer Engineering, University of Delaware, Newark, Delaware, where he is a Professor. He was a Visiting Professor at the Chinese University of Hong Kong during 2002–2003. Before 1995, he held visiting positions in a few institutions. His current research interests include space-time coding, MIMO and OFDM systems, and SAR and ISAR imaging. Dr. Xia has over 100 refereed journal articles published, and 6 U.S. patents awarded. He is the author of the book Modulated Coding for Intersymbol Interference Channels (New York, Marcel Dekker, 2000).Dr. Xia received the National Science Foundation (NSF) Faculty Early Career Development (CAREER) Program Award in 1997, the Office of Naval Research (ONR) Young Investigator Award in 1998, and the Outstanding Overseas Young Investigator Award from the National Nature Science Foundation of China in 2001. He also received the Outstanding Junior Faculty Award of the Engineering School of the University of Delaware in 2001. He is currently an Associate Editor of the IEEE Transactions on Mobile Computing, the IEEE Signal Processing Letters, the IEEE Transactions on Signal Processing, the International Journal of Signal Processing, and the EURASIP Journal of Applied Signal Processing. He was a guest editor of Space-Time Coding and Its Applications in the EURASIP Journal of Applied Signal Processing in 2002. He is also a Member of the Signal Processing for Communications Technical Committee and the Sensor Array and Multichannel (SAM) Technical Committee in the IEEE Signal Processing Society.     

Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test

This paper presents the results of resistive-open defect insertion in different locations of Infineon 0.13 m embedded-SRAM with the main purpose of verifying the presence of dynamic faults. This study is based on the injection of resistive defects as their presence in VDSM technologies is more and more frequent. Electrical simulations have been performed to evaluate the effects of those defects in terms of detected functional faults. Read destructive, deceptive read destructive and dynamic read destructive faults have been reproduced and accurately characterized. The dependence of the fault detection has been put in relation with memory operating conditions, resistance value and clock cycle, and the importance of at speed testing for dynamic fault models has been pointed out. Finally resistive Address Decoder Open Faults (ADOF) have been simulated and the conditions that maximize the fault detection have been discussed as well as the resulting implications for memory test.This work has been partially funded by the French government under the framework of the MEDEA + A503 ASSOCIATE European program.A paper based on this work was presented at the Eighth IEEE European Test Workshop, Maastricht, The Netherlands, May 2003.Simone Borri received the M.Sc. Degree (summa cum laude) in Electronics Engineering from the University of Pisa (Italy) in 1995. In 1997 he joined STMicroelectronics as a digital designer in the DSP development group of S.S.D. (formerly Parthus, now Ceva), Dublin, Ireland. From 1998 to 2000 he was with ST Microelectronics, Milan, Italy as ASIC DSP designer in the Car Communication business unit. Since 2000 he is with Infineon Technologies, Sophia-Antipolis, France as Staff design engineer in the embedded-SRAM design group. He has recently joined the Secure Mobile System Business Unit. His current interests include BIST, DFT techniques and SoC verification. Simone is an IEEE member since 1995.Magali Hage-Hassan was born near Lyon (France) in 1979. She received a Master of Science degree of Microelectronics and Automatics from the Institute of Engineering Sciences of Montpellier in 2003. She is currently working for Infineon in the memory library department in Sophia-Antipolis. She participated to the European research project MEDEA associate. Hage-Hassans interest include memory test.Luigi Dilillo was born in Barletta (Italy) in 1974. At this moment he is doing his last year of Ph.D. in the Microelectronics Department of the Laboratory of Informatics, Robotics and Microelectronics of Montpellier (LIRMM) in France. He received his degree in Electrical Engineering in 2001, at Politecnico di Torino (Italy). His researches include MEMS and digital circuits. At this moment he is working on delay-fault testing, and memory testing.Patrick Girard is presently Researcher at CNRS (French National Center for Scientific Research), and works in the Microelectronics Department of the LIRMM (Laboratory of Informatics, Robotics and Microelectronics of Montpellier—France). His research interests include the various aspects of digital testing, with special emphasis on DfT, logic BIST, delay fault testing and diagnosis, low power testing and memory testing. He has authored and co-authored 1 book and more than 100 papers on these fields. He has managed several European research projects and industrial research contracts. He is Editor-in-Chief of JOLPE—Journal of Low Power Electronics, and Associate Editor of JEC—Journal of Embedded Computing. He will serve as Program vice-Chair for the International Conference on Embedded And Ubiquitous Computing in 2005 and as Program Chair for the IEEE International Workshop on Electronic Design, Test & Applications in 2006. He is also topic chair of two European conferences (DATE and ETS) and is member of the program committee of several other international conferences. Patrick GIRARD obtained the Ph.D. degree in microelectronics from the University of Montpellier in 1992 and the Habilitation à Diriger des Recherches degree from the University of Montpellier in 2003.Serge Pravossoudovitch was born in 1957. He is currently professor in the electrical and computer engineering department of the University of Montpellier and his research activities are performed at LIRMM (Laboratoire dInformatique, de Robotique et de Microélectronique de Montpellier). He got the Ph.D. degree in electrical engineering in 1983 for his work on symbolic layout for IC design. Since 1984, he is working in the testing domain. He obtained the doctorat détat degree in 1987 for his work on switch level automatic test pattern generation. He is presently interested in memory testing, delay fault testing, design for testability and power consumption optimization. He has authored and co-authored numerous papers on these fields, and has supervised several Ph.D. dissertations. He has also participated to several European projects (Microelectronic regulation, Esprit, Medea).Arnaud Virazel was born in Montpellier (France) in 1974. He is presently assistant professor at the university of Montpellier, and works with the LIRMM (Laboratoire dInformatique, de Robotique et de Microélectronique de Montpellier). He received the B.Sc. (1995) and the M.Sc. (1997) degrees in Electrical Engineering and the Ph.D. (2001) degree in Microelectronics, all from the University of Montpellier/LIRMM. A. Virazels interests include delay testing, memory testing and power optimization during test.     

Solutions for H∞ Filtering of Two-Dimensional Systems

Thispaper deals with the H filtering problemfor linear discrete-time two-dimensional (2-D) systems describedby the Roesser model. It firstly establishes a version of thebounded real lemma to give a sufficient condition for quantificationof the H noise attenuation for 2-D systems.Based on the bounded real lemma, the H filteringproblem is investigated for filters of an observer-based structureor a general state equation form and the solutions are obtainedin terms of Riccati inequalities or linear matrix inequalities.The design approach is illustrated by an example of a stationaryfield in image processing.     

Controlling Inductive Coupling in Wide Global Signal Busses Through Swizzling

Recent advances in Deep Submicron (DSM) design and manufacturing technologies have brought to the forefront the importance of inductive coupling amongst long interconnect in high performance microprocessors. Inductive coupling has been shown to depend directly on the overlap length between adjacent signal wires, the activity on these wires and the distance separating them. This paper presents a technique—known as swizzling—that exploits the inductive coupling dependence on distance to reduce the effect of any particular attacker on any of its victims. In the swizzling technique, the order of signal wires in global signal busses is continuously re-arranged to move attackers and victims away from each other. This paper shows that this technique significantly reduces the inductive coupling for the most vulnerable wires neighboring the attacker with zero area and routing resource penalty.Bassel Soudan (S89, M94) received his B.Sc. degree in Electrical Engineering with highest honors from the Department of Electrical Engineering and Computer Science at the University of Illinois at Chicago in 1986. He received his M.Sc. and Ph.D. degrees in 1988 and 1994 respectively from the Department of Electrical and Computer Engineering at the Illinois Institute of Technology.From 1994 through 1996, he was with Design Technology group at Intel Corporation in Hillsboro Oregon where he was involved in the development of Intels Athena suite of EDA CAD tools. He was particularly involved with the design of full chip layout tools and then the verification and validation effort of the suite. From 1996 through 1999, he was with the Merced Microprocessor Design Team at Intel in Santa Clara California. He was a member of the Full-Chip Layout Design Automation team responsible for developing, maintaining, and supporting the suite of full chip layout tools utilized by the project. In the last six months of the project, he was part of the team responsible for assembling and verifying the design. Since 1999, he is an assistant professor at the Department of Electrical/Electronics and Computer Engineering at the University of Sharjah in the United Arab Emirates. His primary research interests include interconnect design, high performance computer architecture and design of new EDA tools and methodologies.He is a member of the IEEE, the IEEE Circuits and Systems Society, the IEEE Computer Society, the ACM, the ACM Special Interest Group on Design Automation, and the ACM Special Interest Group on Microarchitecture.     

Asymptotic behavior of periodicH ∞ a posteriori filters

The asymptotic behavior of linear periodic discrete-timeH a posteriori filters is discussed in this paper. We extend existing results for time-invariantH filters to study the problems arising from periodic discrete-time systems. Based on quasi-lifting techniques, a sufficient condition for ensuring feasibility and convergence ofH a posteriori filters is given.     

Carrier Frequency Recovery Technique in OFDM Systems

Orthogonal frequency division multiplexing (OFDM) systems are highly sensitive to carrier frequency errors. In this paper, a new method utilizing pilots to do frequency synchronization in frequency domain is proposed with large estimation range. It needs no such prerequisite assumption that a perfect symbol timing synchronization [IEEE Transactions on Communications 42 (1994) 2908; 45 (1997) 1613] has been done before performing integer carrier frequency synchronization. Also, a new adjusting model for fine carrier frequency is proposed. Simulation and performance analysis show that our overall frequency estimator has high accuracy. The corresponding FPGA circuit through test in high definition TV (HDTV) prototype in Team of Expert Engineering Group (TEEG) in China proves its availability and feasibility.Bo Ai (M2001) was born in Shannxi Province in China on February 7, 1974. He received a B.Sc. degree from Engineering Institute of Armed Police Force and a Master degree, a Ph.D degree from Xidian University in 1997, 2002 and 2004 in China respectively. He has once participated in the key research project on HDTV in TEEG (Team of Engineering Expert Group) of China, and has published over forty papers in his research area till now. He is senior member of Chinese Electronics Institute (CIE), an editorial commitee member of journal of Computer Simulations. His current interests are the research and applications of OFDM technique with emphasis on synchronization.Jian-hua Ge was born in September, 1961 in JiangSu Province in China. He received the B.Sc., Master and Ph.D. degree from Xidian University in 1982, 1985 and 1989 respectively. He is now the professor in both Xidian University in Xian and Shanghai Jiaotong University in Shanghai. He is the senior member of Chinese Electronics Institute. He has won lots of scientific and technical prizes in China and published many papers. His interests are transmission communications and web security.Yong Wang (M2003) was born in Shannxi Province in China in 1976. He received a B.Sc. and Master degree from Xidian University in China in 1997 and 2002 respectively, and is now working towards the Ph.D. degree on communications in the Key Laboratory of ISN in Xidian University. He has once participated in the key research project on HDTV in TEEG of China and his interests are broadband multimedia communications.Dian-fu Zhang was born in Shannxi Province in China in 1954. He received a B.Sc. degree from Xidian University in China in 1977. He is now working as a professor and the chairman of the telecommunication department in Engineering College of Armed Police Force. His interests are mobile communications.Jun Liu was born in Beijing in China in 1963. He received his B.Sc. degree from Nanjing University Of Aeronautics and Astronautics in China in 1984. He is now a professor in Engineering College Of Armed Police Force. His research interests include integrated circuit design and artificial intelligence.