移动数字信号基带处理平台的设计与实现

设计了基于ARM,DSP和FPGA多处理器的分时长期演进系统(TD-LTE)移动数字信号基带处理平台。该处理平台能够灵活实现移动通信中基带信号的各种操作,主要功能模块包括协议软件实现、物理层算法实现、系统定时等。经测试,在LTE模式及20MHz带宽下,平台符合LTE标准技术指标要求,验证了其实时性、高效性。另外,该基带处理平台从硬件设计上还满足TD-SCDMA,WCDMA,CDMA2000等各种无线通信系统的数字信号处理需求,只需适当修改部分软件,即可实现多种制式的基带处理功能,具有良好的通用性。     

恩智消展出首款可编程多模LTE调制解调器

恩智浦半导体（NXP Scmiconductors）在巴塞罗那举办的世界移动大会上演示出第一个LTE/HSPA/UMTS/EDGE/GPRS/GSM多模基带平台。此平台是下一代软件无线电（SDR）系统解决方案的构造基础。以恩智浦新式数字信号处理核心——嵌入艺术节矢量处理器（EVP）为动力,     

3G移动终端基带信号处理器设计与实现

文章设计了一种基于先进微处理器(ARM)、数字信号处理器(DSP)和现场可编程门阵列(FPGA)体系结构的3G移动终端基带信号处理器。该处理器能灵活实现移动通信系统中基带信号的各种处理,通过无线信号实现移动终端同基站之间的发送与接收,而且能够于不同基站之间进行信号切换。该系统的硬件设计包括以ARM主控模块、DSP实时数据处理模块和FPGA信号生成模块,移动终端软件包括应用层软件、通信协议软件和物理层软件,很好地满足了标准兼容和客户对于功能改善和低成本的需求。     

3G和后3G时代的基带处理技术

基带处理是现代无线通信系统最为核心与关键的技术之一，其研制和实现具有很高的挑战性。本文分析了3G和后3G时代基带处理技术的实现特点，阐述了基于软件无线电具有强大运算能力和灵活性、模块化、开放式结构特征的下一代数字信号处理平台。     

无线目标设计平台加速LTE基带设计和开发

在2010中国LTE峰会上,Xilinx(赛灵思)公司展示了为加速LTE基站设计和开发而专门打造的LTE基带目标设计平台和多模无线目标设计平台. Xilinx无线通信部总监Manuel Uhm介绍说,基带处理是实现产品差异化的关键.但是,3.9/4G系统的出现为设备制造商提出了一个严峻的挑战,因为他们必须努力改进传统的DSP中心通道卡,才能满足新技术的商业需求.特别是,LTE通过提高数据速率,降低端到端的延迟,以及使用处理量更大的先进算法,扮演了催化剂的角色.     

Tensilica发布第二代ConnX基带DSP引擎

Tensilica日前发布第二代基带引擎ConnX BBE16,用于LTE（长期演进技术）及4G基带SoC（片上系统）的设计。ConnX BBE16的16路MAC（乘数累加器）架构经过特别优化,以满足无线DSP（数字信号处理）算法需求．     

赛灵思与Wintegra联手开发LTE基带目标设计平台

全球可编程逻辑解决方案厂商赛灵思公司和美国芯片厂商Wintegra公司联合开发3GPP-LTE基带目标设计平台,相对于传统的设计方法而言将大幅降低基带处理的材料清单成本和功耗。该平台建立在两家公司目前可用的组件基础之上,不仅实现了高度的灵活性与可扩展性,同时还将加速LTE产品的开发进程。     

一种低功耗软件无线电信号处理平台

介绍一种应用于软件无线电的数字信号处理平台,通过对平台设计架构、硬件实现方案及软件可配置功能的阐述,提出了GMSK和CPM两种无线通信波形软件实现方案。该平台采用OMAP+FPGA的架构,具有通用性好、扩展性强等特点,适合于高性能、低功耗的应用场合,可广泛应用于在无线通信、导航定位、图像处理等数字信号处理领域。     

一种P/L频段高度综合化航空平台的设计

为进一步提升航空平台综合化程度,设计了一种用于航空平台的P/L频段功能高度综合化硬件平台方案。该方案通过射频直接采集2 GHz以下的低频射频信号,在数字域分离出探测、通信、导航、识别以及无源侦察等功能所需基带I/Q信号,最后通过软件完成各种信号的功能处理,实现了对探测、通信、导航、识别以及无源侦察等功能共信道和共信号预处理的高度综合设计。硬件实现验证了该方案能够有效降低硬件系统设计的成本和复杂性,降低系统功耗,有力推进了软件无线电在航空平台综合化中的应用。     

安捷伦推出LTE信号分析解决方案

安捷伦科技日前推出用于89600系列矢量信号分析软件的新型3GPP LTE调制分析选件。该选件为当今的射频和基带工程师,提供对LTE收发信机和元器件进行LTE物理层测试与故障诊断所需的全面的信号分析解决方案。从基带到天线,无论是数字信号还是模拟信号,无论是上行链路还是下行链路,Agilent 3GPP LTE选件都能执行LTE信号分析。     

基于MSC8156AMC平台的PRACH基带信号生成

MSC8156AMC具有很强大的处理能力,是LTE解决方案的理想平台,系统基于此平台实现。LTE系统中采用PRACH信道实现物理随机接入,PRACH基带信号生成包含有DFT和长序列的IFFT过程,具有很高的时间复杂度,为满足LTE系统的实时性要求,要选择低运算量的信号处理方案。根据PRACH前导序列的特点,DFT运算可以通过适当的变形采用查表方式实现,避免了大量的复数乘运算。长序列IFFT运算通过Cooley-Turkey算法分解为多级短序列IFFT,减少了运算量。上述方案满足了系统的实时性要求。     

基于Intel AVX2的LTE DFT和IDFT快速算法

通用处理器（GPP,General Purpose Processor）技术的快速发展,为LTE基带信号实时处理提供了一条新的途径。在LTE系统中,DFT和IDFT分别是手机上行发送和基站上行接收中的重要模块。根据3GPP协议,LTE DFT和IDFT处理点数是复合数,文章通过混合基算法以取代直接计算算法,并充分利用GPP平台大存储量的优势及Intel AVX2指令进行并行计算能力,最终使得该算法实现平均每处理1点仅耗时2个cycles,接近FPGA硬件处理性能,满足了LTE系统的实时性要求。经验证,基于GPP平台的DFT和IDFT模块运行结果正确,并且耗时极短。     

An open baseband processing architecture for future mobile terminal design [accepted from open call]

This article introduces an open wireless architecture (OWA) mobile terminal design, focusing on the open baseband processing platform, to support different existing and future wireless communication standards through multi-dimensional open baseband processing modules with open interface parameters and baseband management systems. The article describes a multilayer, open architecture platform to maximize system flexibility and minimize terminal power consumption, so as to provide an integrated and converged next-generation wireless and mobile communication terminal system. The OWA platform is fully compatible with the computer architecture, with interface-based rather than transmission-specific system architecture, for complete openness and simplicity.     

基于SCA软件无线电硬件平台的设计

介绍了一种基于SCA软件无线电硬件平台的具体设计方案,通过对平台的资源需求估计,确定以DSP+ FPGA为核心器件构建一套具有高度灵活性和开放性的通用通信平台,该平台能够完成信号的基带和中频处理,从而实现多模式、多频段、多信道等通信功能.     

基于GPP的LTE上行链路并行策略研究

3GPP LTE系统需要支持很高的空口速率,这就对基带部分的信号处理时间提出了很高的要求。单线程的串行处理已经很难达到系统要求,需要引入并行化方法来实现高速的数据处理。在英特尔多核处理器上,针对LTE上行物理信道的特点,使用OpenMP并行化方法对上行数据进行了并行化处理,并通过测试比较,验证这种方法取得了很好的效果。     

Implementation of LTE system on an SDR platform using CUDA and UHD

In this paper, we present an implementation of a long term evolution (LTE) system on a software defined radio (SDR) platform using a conventional personal computer that adopts a graphic processing unit (GPU) and a universal software radio peripheral2 (USRP2) with a URSP hardware driver (UHD) to implement an SDR software modem and a radio frequency transceiver, respectively. The central processing unit executes C++ control code that can access the USRP2 via the UHD. We have adopted the Ettus Research UHD due to its high degree of flexibility in the design of the transceiver chain. By taking advantage of this benefit, a simple cognitive radio engine has been implemented using libraries provided by the UHD. We have implemented the software modem on a GPU that is suitable for parallel computing due to its powerful arithmetic and logic units. A parallel programming method is proposed that exploits the single instruction multiple data architecture of the GPU. We focus on the implementation of the Turbo decoder due to its high computational requirements and difficulty in parallelizing the algorithm. The implemented system is analyzed primarily in terms of computation time using the compute unified device architecture profiler. From our experimental tests using the implemented system, we have measured the total processing time for a single frame of both transmit and receive LTE data. We find that it takes 5.00 and 8.58 ms for transmit and receive, respectively. This confirms that the implemented system is capable of real-time processing of all the baseband signal processing algorithms required for LTE systems.     

Energy Aware Signal Processing for Software Defined Radio Baseband Implementation

The fast pacing diversity and evolution of wireless communications require a wide variety of baseband implementations within a short time-to-market. Besides, the exponentially increased design complexity and design cost of deep sub-micron silicon highly desire the designs to be reused as much as possible. This yields an increasing demand for reconfigurable/ programmable baseband solutions. Implementing all baseband functionalities on programmable architectures, as foreseen in the tier-2 SDR, will become necessary in the future. However, the energy efficiency of SDR baseband platforms is a major concern. This brings a challenging gap that is continuously broadened by the exploding baseband complexity. We advocate a system level approach to bridge the gap. Specifically, we fully leverage the advantages (programmability) of SDR platforms to compensate its disadvantages (energy efficiency). Highly flexible and dynamic baseband signal processing algorithms are designed and implemented to exploit the abundant dynamics in the environment and the user requirement. Instead of always performing the best effort, the baseband can dynamically and autonomously adjust its work load to optimize the average energy consumption. In this paper, we will introduce such baseband signal processing techniques optimized for SDR implementations. The methodology and design steps will be presented together with 3 representative case studies in HSDPA, WiMAX and 3GPP LTE.     

基于ZSP500的TD-SCDMA系统设计

对ZSP500的结构和功能进行了介绍,在此基础上提出了基于ZSP500的TD-SCDMA硬件平台,具体介绍了在该平台上数字基带信号处理的过程与实现.对基于ZSP的设计在移动通信中的应用前景进行了展望.     

基于蓝牙系统的基带处理仿真教学实验的设计与实现

提出了一种适用于教学的蓝牙基带处理仿真实验，着重研究了基于蓝牙系统的基带包结构和差错控制方法，以及跳频扩频、保密通信等原理及其实现方法。仿真软件界面知识点丰富，有助于理解和掌握无线通信系统对基带信号的处理方法，在教学实践中获得了很好的效果。     

A complex baseband platform for spatial-temporal mobile radio channel simulations

Joint spatial-temporal signal processing has been recognized as the key to reducing the effects of the intersymbol and cochannel interference seen in very high bit-rate mobile radio communications systems. Developing hardware simulators that can simulate mobile radio propagation scenarios in time and space domains is essential for evaluating the real-time performance of spatial-temporal signal processing schemes. This paper outlines a complex baseband platform developed for spatial-temporal mobile radio channel simulations. The platform consists of a complex baseband fading/array response simulator, a digital signal processor (DSP) board, and a general-purpose parameter estimator that uses systolic array implementation of the recursive least square (RLS) algorithm. Results of experiments conducted using the developed platform are presented to confirm the proper operation of the system.