航天电子元器件检测过程中的静电防护研究

以航天电子元器件为研究对象,分析其在被检测过程中产生静电放电的原因及静电放电对元器件的危害机理。总结一些静电防护技术确保元器件在检测过程中能够避免静电对其危害。     

企业静电防护项目管理因素分析及对策研究

半导体制程持续朝向精密化迅速发展,静电放电事件对电子产品所造成的损坏也一直是关注的重点。中达电子作为工业自动化行业一线企业,在静电防护推行方面,得到了公司管理层的大力支持与协助。于2010年筹备成立的静电防护项目组对各组装工厂的静电敏感器件及生产工艺流程进行指导,并从宏观及日常细微之处提供支持及帮助,促使中达电子集团能在此领域更上一个新台阶。     

关于静电标准的“碰撞”

IEC61000-4-2标准探讨随着科学技术的发展,静电已经远远不是物理范畴原来的物理含义.静电在石化、电报装置,各个领域造成易燃易爆的危害事故,受到世人的关注.特别是随着微电子器件的发展,静电造成的危害更是不容忽视.静电放电可能给微电子器件造成隐性损伤或者说潜在性失效,潜在性失效一般的测试方法是很难判断的,因此,就更需要从管理层面上规范生产过程中的一些工艺,规范人的行为.所以制定静电防护标准,研究静电放电管理层面上的工作就显得十分重要.     

浅谈静电损失及防护

静电放电是日常生活中的多见现象,其主要是由不同物质相互摩擦,导致电荷积累成高电压,瞬时静电甚至可达几万伏,对电子元器件的危害是十分巨大的,必须予以重视。本文简要概述了静电的产生和来源、静电的危害,并提出了静电放电的几点防护措施,以期对静电敏感器件使用者起到一定的借鉴作用。     

基于干法刻蚀技术的氮化镓MEMS加工工艺(英文)

氮化镓(GaN)材料已成功应用于光电子器件、高频功率器件等领域.近年来,由于GaN优异的材料特性,例如机械、热、化学稳定性以及生物兼容性等,使基于GaN的微机电系统(MEMS)得到了学术界的广泛关注.针对氮化镓MEMS结构的有效的图形化及释放技术是工艺研究的重点.设计、采用了一种全干法刻蚀技术,实现了(111)晶向硅衬底上的氮化镓基MEMS微结构的加工制造.利用提出的工艺方案,实现了多种悬浮GaN微结构的加工与测试表征实验.通过电子扫描显微镜(SEM)和光学轮廓仪进行了基本形貌表征;利用微拉曼光谱实验进行了加工结构的残余应力表征.     

氮化镓纳米片的制备及测试表征

二维GaN纳米结构的制备对二维GaN基电子、光电子等纳米器件具有重要意义。本文采用化学气相沉积(CVD)制备二维GaN纳米片时,使用液态金属催化剂,成功制备了二维GaN纳米片,得到制备GaN纳米片的最佳工艺条件。通过对制备的GaN纳米片进行扫描电子显微镜(SEM)、能谱仪(EDS)以及X射线衍射仪(XRD)测试表征,结果表明：制备的GaN纳米片是表面光滑、大小薄厚均匀、结晶度良好的六方钎锌矿结构GaN纳米片。     

静电防护工程的研究与进展

静电放电已成为信息化时代的公害之一,它不仅是危险场所的点火源、引爆源,而且是信息化设备的电磁干扰源。章在论述静电放电危害、静电放电的特点、作用机理和形成静电危害基本条件的同时,报道了我国在静电检测与静电防护工程研究方面的成果与进展,提出了“信号自屏蔽－电荷耦合”测试原理、真实静电感度测试方法、织物电位测试方法和人体静电动态电位测试技术,建立了电火工品静电发火数理模型、“静电危险场所”等级划分标准和分类防护措施、预测静电危害的逻辑关系图和静电防护的一般原则与对策。章介绍了部分实验数据和该领域当前研究的热点问题及发展趋势。     

ESD30C静电放电仿真系统

静电现象广泛存在于自然界、工业生产和人们的日常生活中,随着科学技术的发展,静电技术得到广泛的应用,但是静电同时也给人们带来重大损失和危害,如何提高产品的防静电能力成为大家关注的焦点,要进行防静电试验必须首先建立静电放电仿真系统.本文介绍了ESD30C静电放电仿真系统,论述了该测试系统建立的必要性、功能、系统组成及使用方法.     

关于举办首届“静电防护与标准化学术交流会”的通知

各相关单位:随着石化、电子等工业生产领域高分子材料、ESD敏感器件广泛应用,静电放电造成的危害备受人们关注,静电防护工作已成为现代化工业生产过程中必不可少的工作之一。为进一步提升我国工业化生产的静电防护技术与标准化水平.提升我国科技产品质量与可靠性.增强我国工业化生产安全性,由中国标准化研究院     

各种结构等离子体显示屏放电过程的研究

采用放大单元的方法研究了表面放电结构、对向放电结构和新型荫罩式等离子体显示屏（SMPDP）的放电过程。分别制作了放大倍数为40的表面放电结构、对向放电结构和荫罩式结构PDP的放大单元。建立了放大单元的光辐射特性测试系统，采用高速ICCD拍摄了相应结构的放电过程并分析研究了各自的放电特性。结果表明，SMPDP的放电过程为非均匀场中的对向放电过程，具有较表面放电结构和对向放电结构更优越的放电性能。     

Electrostatic pulse breakdown in nmos devices

The electrostatic discharge (ESD) sensitivity of small dimension n-channel metal oxide semiconductor (NMOS) field effect transistors (FETs) has been investigated. NMOS FETs of varying dimensions and a constant gate oxide thickness of 400® were each subjected to a single ESD voltage pulse of between 50 and 250V at temperatures between 25 and 200°C. Over 4000 devices were used, all resident on a single 3 inch silicon wafer. The object of the experiment was to determine the dependence of device ESD sensitivity on temperature, voltage and device dimensions as well as to investigate the mechanisms that cause oxide breakdown as a result of ESD damage. No temperature dependence of device ESD sensitivity was observed within the range of the experiment. A significant voltage dependence was observed, with degradation accounting for over 80 per cent of devices at 250V. A cumulative ESD effect was observed, whereby the degradation of device performance was found to increase with the number of applied pulses. Analysis of the breakdown characteristics revealed that the cause of damage was oxide breakdown. Application of the ESD pulse appears to lead to oxide breakdown through impact ionization within the oxide, the very short duration of the pulse not being favourable to processes involving electron trapping unless these traps are already present in the oxide.     

传感器参数自动标定及掉电记录保护装置的研制

介绍了传感器静态标定过程及步骤,并设计了一种基于51单片机的传感器参数自动标定及掉电记录保护装置。给出了掉电记录保护功能的硬件实现方案及相关芯片X5045的使用。同时在Visual Basic环境下编写了上位机程序,来实现单片机与PC机通信及数据转换。     

Electrostatic discharge: mechanisms,protection techniques and effects on integrated circuit reliability

Electrostatic discharge (ESD) was once considered a problem only for unprotected, insulated-gate field-effect transistors, but the ever shrinking geometries of all semiconductor devices have made them vulnerable to this phenomenon. ESD models and on-chip device protection techniques are reviewed, together with current evidence concerning latent defects and their effect on device reliability. A brief discussion on the importance of ESD controls in the assembly environment is also included, with an emphasis on realistic cost-effective measures. Finally, the impact of continued scaling on ESD vulnerability and protection structure limitations, are examined.     

ESD in integrated circuits

A review of the effects of electrostatic discharge (ESD) on semiconductor integrated circuits is presented. The principles of the human body model (HBM), the machine model (MM) and the charged device model (CDM) test methods are outlined, and their relative merits and drawbacks are discussed. Techniques, such as the transmission line pulse method, which may be used to characterise ESD protection circuit elements are also presented. The concept of ESD protection circuit designs and some typical ESD protection circuit elements are presented. The main design and process parameters are identified, and the main categories of damage under ESD conditions are shown. Models of the behaviour of the protection circuit elements under high current conditions are presented, and the boundary conditions for damage are discussed. The issues that will influence ESD protection circuit behaviour in the future are discussed.     

Optimal T2 Control Chart with a Double Sampling Scheme – An Alternative to the MEWMA Chart

Recent studies have shown that a double sampling (DS) scheme yields improvements in detection times of process shifts over variable ratio sampling (VRS) methods that have been extensively studied in the literature. Additionally, a DS scheme is more practical than some of the VRS methods since the sampling interval is fixed. In this paper, we investigate the effect of double sampling on cost, a criterion as important as detection rate. We study economic statistical design of the DS T² chart (ESD DS T²) so that designs are found that are economically optimal but yet meet desired statistical properties such as having low probabilities of false searches and high probabilities of rapid detection of process shifts. Through an illustrative example, we show that relatively large benefits can be achieved in a comparison with the classical T² chart and the statistical DS T² charts with our ESD DS T² approach. Furthermore, the economic performance of the ESD DS T² charts is favorably compared to the MEWMA and other VRS T² control charts in the literature. Copyright © 2011 John Wiley & Sons, Ltd.     

Tungsten trioxide thin films prepared by electrostatic spray deposition technique

Tungsten trioxide (WO₃) thin films deposited on a Pt-coated alumina substrate using the electrostatic spray deposition (ESD) technique is reported in this paper. As precursor solution, tungsten (VI) ethoxide in ethanol was used. The morphology and the microstructure of the films were studied using scanning electron microscopy coupled with energy dispersive X-ray analysis, transmission electron microscopy, X-ray diffraction, and Raman spectroscopy. Dense to porous morphologies were obtained by tuning the deposition temperature. Impedance spectroscopy and current-voltage measurements were used to study the electrical behaviour of the films in air, in temperature range 300-500 °C. The activation energy was estimated from Arrhenius plots. Considering the obtained results, the ESD technique proved to be an effective technique for the fabrication of porous tungsten trioxide thin films.     

Using a system-on-a-chip implantable device to filter circulating infected cells in blood or lymph

This paper describes a system on a chip (SoC) that makes use of nanoscale cellular adhesion mechanisms in an integrated electronic microsystem to filter infected cells from blood or lymph. An example of a human immunodeficiency virus-specific SoC is explored in depth. Such systems work in vivo, and blood and lymph are filtered on a continuous basis. With the intelligence on the chip, captured cells can be identified and lyzed, expelled, or otherwise acted upon. These types of systems transfer the burden of research from traditional chemotherapy to bioengineering and system design.     

装有贝塞尔盒型能量分析仪的电离规和四极质谱计的研制

贝塞尔盒型能量分析仪由三部分组成 :一个圆筒形电极、一个中心圆盘和两个带中心孔的侧板 ,该分析仪结构简单、结实 ,十分适用于电离规和四极质谱计上。对电离规而言 ,分析仪被放置于电离器及离子收集器之间。在栅型电离器中所产生的离子被分离并注入到能量分析仪中。分析仪依据其激发的能量把电离器中产生的气相离子和栅网表面上脱附的电子激励解吸的离子分离开。如果应用一个法拉第杯型离子收集器和一个灵敏的直流放大器来进行离子流测量的话 ,那么该电离规测量范围在 10 - 1 0 ～ 10 - 3Pa之间。当二次电子倍增器采用脉冲计数方法时 ,所测量的压力范围在 10 - 1 1～ 10 - 6 Pa之间 (Ax TRAN,ISX2 ,U L VAC公司 ) .其典型灵敏度对氮气而言为 (6 .7± 0 .2 )× 10 - 3Pa- 1 和对氢而言为 (2 .3± 0 .0 4 )× 10 - 3Pa- 1 。对四极质谱计而言 ,能量分析仪被置于在电离器和四极滤质器之间。装有该分析仪的质谱计 ,给出了没有电子激励解吸离子的简单质谱。该分析仪能使四极质谱计的离子收集器免受从栅网表面发射的 X射线的辐射 ,和从电离器中的离子以及被激发的分子在退激励过程中释放的紫外线的辐射。这种屏蔽作用改善了在 10 - 3Pa范围内的气体中微量杂质的检测极限 ,使之降至亿分之几     

An efficient BIST method for non-traditional faults of embedded memory arrays

In this work, a built-in self-testing (BIST) method is proposed to detect nontraditional faults of embedded memory arrays for a system-on-chip (SoC) design. The nontraditional faults include single-cell read-sensitive faults and read coupling faults. The BIST method can efficiently deal with embedded memory arrays spatially distributed on the entire SoC chip. The concept of redundant read-write operations is applied to detect all embedded memory arrays with different sizes simultaneously. The redundant operations do not affect the fault coverage of all nontraditional faults discussed in this paper. The method has the advantages of low hardware overhead, short test time, and high fault coverage for nontraditional memory defects.     

能量分析器型真空电离规性能研究

电子激励脱附(ESD)效应和软X射线效应是影响电离真空计测量下限的两大重要因素。基于能量分析器研制了电离真空规,在极高真空校准装置上对其开展性能研究,包括不同压力或不同阴极发射电流下的离子流、ESD效应和软X射线影响。结果表明,系统压力介于10^-8 Pa和10^-6 Pa之间,当气体发生电离,能量分析器电压在低于阳极电压约25 V时收集极能得到最大的气相离子流。系统压力在10-7~10^-8 Pa量级,采用2.5 mA的发射电流可得到比1 mA更大的气相离子流值。分离气相离子与ESD离子的能量筒电压差约为30 V,规管栅极除气后可降低ESD效应至除气前的37.5%。电离规的软X射线带来的本底干扰对应等效压力约为9×10^-11 Pa。