采用Xtensa可配置处理器技术开发视频加速引擎

掌上多媒体设备的增长极大地改变了终端多媒体芯片供应商对产品的定位需求。这些芯片提供商的IC设计目标不再仅仅针对一两种多媒体编解码     

Tensilica Xtensa LX处理器在EEMBC办公自动化基准测试获得最高得分

为单芯片系统(SOC)设计优化特定应用可配置处理器的设计自动化公司Tensilica，Inc．宣布，它获得了可授权处理器核心前所未有的最高记录得分，这是在嵌入式微处理器基准协会(EEMBC)的办公自动化基准测试中任何处理器都未曾获得过的最高得分。EEMBC基准测试得分是由EEMBC验证实验室(ECL)独立进行的，它确认Xtensa LX处理器比大得多的PowerPC 440GX核心快了接近四倍，超过了强大的64位MIPS 20Kc处理器四倍以上。     

Tensilica授权香港应科院使用Xtensa可配置处理器

Tensilica日前宣布,香港应用科技研究院选择Tensilica Xtensa可配置处理器,用于视频处理研究。香港政府成立应科院,从事杰出的研发工作,积极的把科技成果转移给产业界,     

北京新岸线科技借力Xtensa可配置处理器，开发手机电视基带DSP

中国北京2006年10月19日讯．Tensilica公司今日宣布，北京新岸线软件科技有限公司（NuFrom）正采用Tensilica公司Xtensa可配置处理器内核进行一款复杂SoC设计。     

Tensilica Xtensa LX处理器在EEMBC网络2．0基准测试中拔得头筹

全球唯一的为SOC设计提供专用可配置处理器的设计自动化公司Tensilica，Inc．目前宣布，它获得了目前嵌入式微处理器基准协会(EEMBC)的网络2．0基准测试套件中任何处理器从未得过的最高得分。Tensilica的Xtensao LX处理器是第一个完成复杂的全套基准测试且可授权的处理器内核。     

Tensilica推出创新的Xtensa VI可配置且可扩展处理器内核

Tensilica（泰思立达）公司日前发布Xtensa处理器家族的新成员一用于片上系统（SoC）设计的可配置且可扩展的处理器内核Xtensa VI。作为Tensilica公司主要产品Xtensa V处理器内核的换代产品，Xtensa VI着力在3个方面进行改进：首先是使用Tensilica认证的XPRES编译器从以C／C＋＋为基础的算法自动定制的能力；其次是实现比Xtensa V低约30％的功耗；最后是激活MMU的配置下的高级安全机制通过一个“不执行”位来增强保护功能以抵制恶意代码。     

通过FLIX指令结构提高可配置处理器计算性能

Xtensa LX处理器采用了Tensilica独创的可变长度指令扩展FLIX(Flexible Length Instruction eXtensions)体系结构,该体系结构是Xtensa指令集体系结构ISA的高效实现,它给设计人员以更多的选择去对系统设计的成本和性能进行折衷。FLIX技术为设计人员提供了灵活的方法,将单操作RISC指令、简单和复合操作TIE指令以及多操作FLIX指令自由地结合在一起。通过将多个操作封装在一个32位或者64位的宽指令字中,FLIX技术可以允许设计人员加速执行嵌入式应用程序中比较主要的“热点”代码,同时消除了超长指令字VLIW处理器体系结构中指令代码和系统性能方面的缺陷。     

ARC授权英飞凌ARC700可配置核用于有线接入

ARC公司宣布，英飞凌公司已经取得了采用ARCXY先进DSP技术的ARC700可配置处理器核授权，以用于其下一代有线接入产品。ARC700核系列采用0.13μm工艺技术，和最佳化的7层管线设计，可以提供高达405MHz的时钟频率。同时，该处理器核还具有一个高性能架构，该架构可以提供16位和32位的指令集、众多的流水线和优化的开发工具。英飞凌将利用该高性能核在单个芯片上，同时执行主机功能和应用处理。     

Tensilica为Xtensa可配置处理器和钻石标准系列处理器IP核提供集成的实时跟踪支持

Tensilica宣布,一项可选的全速非侵入式指令跟踪功能已被添加进其钻石标准系列和Xtensa可配置处理器IP核中.TRAX-PC处理器跟踪捕获单元与Nexus5001相兼容,适用于调试复杂的且具有挑战性的实时应用,例如引擎和发动机控制.在Xplorer集成设计环境(IDE)中已完全集成了片上TRAXE硬件的使用和软件控制,从而软件工程师能够方便的利用TRAX-PC处理器跟踪捕获宏单元进行程序开发和调试.     

可配置处理器应用日趋红火

可配置处理器在你的设计中可能是一个经济实惠的元件,但也可能是一个演进中的抽象概念。     

宽带通信系统与可配置平台

宽带通信已进入重大变革时期。随着信道密度 和每个信道处理性能的增加,使得大多数产 品的结构显得过时。演变中的市场和多种标准, 要求设备生产商增加系统软件的可编程性。网络 处理器和新的数字信号处理器(DSP)已开始瞄 准已有通信链路中的局部解决方案,但主要的瓶 颈依然存在。最新出现的解决方案是可配置平台, 它能提供多处理、指令级并行性和适应特定范围 要求的灵活性。 迅速变化的标准和市场条件,连同需要在整 个通信架构中保持稳定的设备环境,促使人们对 宽带通信领域采用宽范围可…     

一个可扩充、可配置的软件设计

随着对软件功能需求的日益增长，如何利用最低成本扩充现有软件的功能，是我们非常关注的一个问题。编写可扩充、可配王的软件正是解决这个问题的一种方法。他能够大大提高现有软件的复用度，简化软件的功能扩充。但这种编写软件的方法同时也增加了软件系统的复杂性，所以并不是所有的软件都需要具有这样的功能。作者根据实际开发中的经验，指出XML与组件化程序设计为编写可扩充、可配王的软件提供了基本的技术支持，并利用这两项技术，介绍了设计与编写一个综合网络管理软件的基本步骤。为今后开发可扩充、可配置的软件提供了参考。     

Communication processors

A review is given of the use of small digital computers for the processing of data received over communication lines. A detailed discussion is presented of the hardware and software requirements of front-end processors, network processors, remote data concentrators, and message switching systems. Finally, the desirable features common to all communications processors are analyzed. Examples of actual applications are given, so that a realistic basis can be established for the determination of the features which should be included in the design of new communication processors.     

用户可定制的处理器

随着130nm和90nm工艺的成熟,每平方毫米的硅片面积上可以集成大约100K～200K的逻辑门,一颗面积大约50mm2的低成本芯片可以容纳5M～10M逻辑门.越来越多的SoC设计者正在试图将整个系统集成在一颗芯片上,但是他们也面临着严峻的挑战,因为传统的基于RTL的SoC硬件设计方法的缺点正日益显现出来.     

Telecommunications processors

Telecommunications controllers worldwide are becoming increasingly stored-program oriented. Electromechanical and electronic wired logic controllers lack the flexibility, maintainability, and (ultimately) the economy of stored program processors. While similar to commercial computers, most stored program telecommunications processors have features unique either in nature or degree of application. There also exists a remarkable variety of overall architectural features which are useful in telecommunications applications, and a similar variety of administrations and manufacturers willing to espouse them. Pertinent stored program processor architectural features are discussed as a dass, then extant and proposed processors are described and placed in perspective, Finally, likely future trends are discussed.     

Changing processors

The author reports on the theory and practice behind an innovative 32 bit RISC processor core, whose architecture can be customised to provide the optimum design solution for processor-based application-specific integrated circuits. In its basic configuration, the ARC processor, the Tangent-A4, is a four-stage pipeline device, with instructions, data and address formats all 32 bit. It also boasts separate instruction and data buses (Harvard architecture), data and instruction caches, and a unique host interface (parallel, JTAG or user defined), giving external devices access to the internal registers and memory     

Multimedia processors

This paper describes large-scale-integration programmable processors designed for multimedia processing such as real-time compression and decompression of audio and video as well as the generation of computer graphics. As the target of these processors is to handle audio and video in real time, the processing capability must be increased tenfold compared to that of conventional microprocessors, which were designed to handle mainly texts, figures, tables, and photographs. To clarify the advantages of a high-speed multimedia processing capability, we define these chips as multimedia processors. General-purpose microprocessors for workstations and personal computers (PCs) use special built-in hardware for multimedia processing, so the multimedia processors described include these modified general-purpose microprocessors. After reviewing the history of programmable processors, we classify multimedia processors into five categories depending on their basic architecture. The categories are reduced instruction set computer (RISC) microprocessors for workstations, complex instruction set computer microprocessors for PCs, embedded RISCs, low-power digital signal processors (DSPs), which are mainly used for mobile communications devices, and media processors that support PCs for multimedia applications. These five classes are then grouped into two: microprocessors with a multimedia instruction set and highly parallel DSPs. An architectural comparison between these two groups on the basis of Moving Picture Experts Group decoding applications is made, and the advantages and disadvantages of each class are clarified. Future processors, including “system on a chip,” and their applications are also discussed     

A Configurable and Extensible Transport Protocol

The ability to configure transport protocols from collections of smaller software modules allows the characteristics of the protocol to be customized for a specific application or network technology. This paper describes a configurable transport protocol system called CTP in which microprotocols implementing individual attributes of transport can be combined into a composite protocol that realizes the desired overall functionality. In addition to describing the overall architecture of CTP and its microprotocols, this paper also presents experiments on both local area and wide area platforms that illustrate the flexibility of CTP and how its ability to match more closely application needs can result in better application performance. The prototype implementation of CTP has been built using the C version of the Cactus microprotocol composition framework running on Linux.