Current progress in modeling self-heating effects in FD SOI devices and nanowire transistors

In this paper we summarize 6 years of work on modeling self-heating effects in nano-scale devices at Arizona State University (ASU). We first describe the key features of the electro-thermal Monte Carlo device simulator (the two-dimensional and the three-dimensional version of the tool) and then we present series of representative simulation results that clearly illustrate the importance of self-heating in larger nanoscale devices made in silicon on insulator technology (SOI). Our simulation results also show that in the smallest devices considered the heat is in the contacts, not in the active channel region of the device. Therefore, integrated circuits get hotter due to larger density of devices but the device performance is only slightly degraded at the smallest device size. This is because of two factors: pronounced velocity overshoot effect and smaller thermal resistance of the buried oxide layer. Efficient removal of heat from the metal contacts is still an unsolved problem and can lead to a variety of non-desirable effects, including electromigration. We propose ways how heat can be effectively removed from the device by using silicon on diamond and silicon on AlN technologies. We also study the interplay of Coulomb interactions due to the presence of a random trap at the source end of the channel and the self-heating effects. We illustrate the influence of a positive and a negative trap on the magnitude of the on-current and the role of the potential barrier at the source end of the channel.     

Analytical subthreshold current and subthreshold swing models of short-channel dual-metal-gate (DMG) fully-depleted recessed-source/drain (Re-S/D) SOI MOSFETs

In this paper, analytical subthreshold current and subthreshold swing models are derived for the short-channel dual-metal-gate (DMG) fully-depleted (FD) recessed-source/ drain (Re-S/D) SOI MOSFETs considering that diffusion is the dominant current flow mechanism in subthreshold regime of the device operation. The two-dimensional (2D) channel potential is derived in terms of back surface potential and other device parameters. The so called virtual cathode potential in term of the minimum of back surface potential is also derived from 2D channel potential. The virtual cathode potential based subthreshold current and surface potential based subthreshold swing model results are extensively analyzed for various device parameters like the oxide and silicon thicknesses, thickness of source/drain extension in the BOX, control to screen gate length ratio and channel length. The numerical simulation results obtained from ATLAS \(^{\text{ TM }}\) , a 2D numerical device simulator from SILVACO Inc have been used as a tool to verify the model results.     

A novel double-gate SOI MOSFET to improve the floating body effect by dual SiGe trench

In short-channel silicon-on-insulator metal-oxide-semiconductor transistors (SOI MOSFETs) the high electric field near the drain increases the floating-body effect. The aim of this article is to introduce a novel structure that reduces the electric field near the drain, so improving the floating-body effect. In the proposed structure, a dual trench is created in the buried oxide exactly under the junctions of drain/source and channel and is filled with an n-type SiGe material. The dual trench regions absorb the electric field lines and hence, the electric characteristic significantly improve. The proposed structure is named as dual SiGe trench double gate SOI MOSFET. In addition, we observe a considerable improvement in self-heating effects due to the higher thermal conductivity of SiGe in comparison with silicon dioxide.     

Modeling of FinFET: 3D MC Simulation Using FMM and Unintentional Doping Effects on Device Operation

Novel device concepts such as dual gate SOI, Ultra thin body SOI, FinFETs, etc., have emerged as a solution to the ultimate scaling limits of conventional bulk MOSFETs. These novel devices suppress some of the Short Channel Effects (SCE) efficiently, but at the same time more physics based modeling is required to investigate device operation. In this paper, we use semi-classical 3D Monte Carlo device simulator to investigate important issues in the operation of FinFETs. Fast Multipole Method (FMM) has been integrated with the EMC scheme to replace the time consuming Poisson equation solver. Effect of unintentional doping for different device dimensions has been investigated. Impurities at the source side of the channel have most significant impact on the device performance.     

Scalability and process induced variation analysis of polarity controlled silicon nanowire transistor

In this paper, we present scalability and process induced variation analysis of polarity gate silicon nanowire field-effect transistor. 3D simulation results show that the PGFET offers significant reduction in short channel effects and variability due to utilization of uniform lightly doped silicon nanowire (SiNW) as compare to highly doped silicon nanowire in junctionless transistors. The performance parameters were evaluated for different device geometries, such as variation in SiNW radius, equivalent oxide thickness, channel length and spacer length. Sensitivity analysis shows that the PGFET exhibits less dependence towards gate length in comparison to other device parameters. It is seen that ON to OFF current ratio variation with silicon nanowire thickness is lower for PGFET as compared to JLFET. The threshold voltage roll-off and sensitivity towards intrinsic delay in PGFET is much lower than its counterpart device.     

2D Modeling of nanoscale DG SOI MOSFETs in and near the subthreshold regime

We have developed a 2D model for double-gate SOI MOSFET based on a solution of the Laplacian for the device body utilizing conformal mapping techniques. The model yields explicit expressions for the subthreshold and near-threshold electrostatics of the device, including the perpendicular electrical field and the potential distributions along the silicon/insulator interfaces and at the center gate-to-gate axis. From these expressions, we derive information on the threshold conditions, the potential barrier topography, and the electron density distribution in the device under different biasing conditions. This model constitutes a framework for very precise, scalable, compact models of nanoscale MOSFETs.     

Superior hot carrier reliability of single halo (SH) silicon-on-insulator (SOI) nMOSFET in analog applications

In this paper, for the first time, we report a study on the hot carrier reliability performance of single halo (SH) thin film silicon-on-insulator (SOI) nMOSFETs for analog and mixed-signal applications. The SH structure has a high pocket impurity concentration near the source end of the channel and low impurity concentration in the rest of the channel. Besides excellent dc output characteristics and experimental characterization results on these devices show better V/sub th/-L roll-off, low DIBL, higher breakdown voltages, and kink-free operation. Further SH SOI MOSFETs have been shown to exhibit reduced parasitic bipolar junction transistor effect in comparison to the homogeneously doped channel (conventional) SOI MOSFETs. Small-signal characterization on these devices shows higher ac transconductance, higher output resistance, and better dynamic intrinsic gain (g/sub m/R/sub o/) in comparison with the conventional homogeneously doped SOI MOSFETs. Also, the low drain junction capacitance as a result of low impurity concentration near the drain region is beneficial for improved circuit performance. The experimental results show that SH SOI MOSFETs exhibit a lower hot carrier degradation in small-signal transconductance and dynamic output resistance in comparison with conventional homogeneously doped SOI MOSFETs. From 2-D device simulations, the lower hot carrier degradation mechanism in SH SOI MOSFETs is analyzed and compared with the conventional SOI MOSFETs.     

Effect of elastic processes and ballistic recovery in silicon nanowire transistors

Scaling of silicon devices is fast approaching the limit where a single gate may fail to retain effective control over the channel region. Of the alternative device structures under focus, silicon nanowire transistors (SNWT) show great promise in terms of scalability, performance, and ease of fabrication. Here we present the results of self-consistent, fully 3D quantum mechanical simulations of SNWTs to show the role of surface roughness (SR) and ionized dopant scattering on the transport of carriers. We find that the addition of SR, in conjunction with impurity scattering, causes additional quantum interference which increases the variation of the operational parameters of the SNWT. However, we also find that quantum interference and elastic processes can be overcome to obtain nearly ballistic behavior in devices with preferential dopant configurations.     

Emission and absorption of optical phonons in Multigate Silicon Nanowire MOSFETs

In this paper we study the influence of emission/absorption processes due to optical phonons on the electrical properties of multigate silicon nanowire transistors. We show that low-energy phonons reduce drain current through backscattering of carriers by emission/absorption processes while high-energy phonons redistribute the current energy spectrum along the nanowire channel through phonon emission without significantly reducing the drain current drive. The influence of emission/absorption is investigated in different multigate silicon FET structures with uniform channel, single impurity, random doping atom distribution and oxide tunnel barriers. A three-dimensional quantum mechanical device simulator based on the NEGF formalism in coupled mode-space approach is used to model electron transport in the presence of optical phonon scattering mechanism. Electron-phonon scattering is accounted for by adopting the self-consistent Born approximation and using the deformation potential theory.     

Analytical modeling of subthreshold swing in undoped trigate SOI MOSFETs

A new analytical model for the subthreshold swing of nanoscale undoped trigate silicon-on-insulator metal–oxide–semiconductor field-effect transistors (MOSFETs) is proposed, based on the channel potential distribution and physical conduction path concept. An analytical model for the potential distribution is obtained by solving the three-dimensional (3-D) Poisson’s equation, assuming a parabolic potential distribution between the lateral gates. In addition, mobile charges are considered in the model. The proposed analytical model is investigated and compared with results obtained from 3-D simulations using the ATLAS device simulator and experimental data. It is demonstrated that the analytical model predicts the subthreshold swing with good accuracy for different lengthes, thicknesses, and widths of channel.     

The importance of thermal conductivity modeling for simulations of self-heating effects in FD SOI devices

In this review paper we want to emphasize the importance of having accurate thermal conductivity models for modeling self-heating effects on the device level. For that purpose, we first consider thin silicon films and calculate (using Sondheimer’s approach) their thermal conductivity that incorporates boundary scattering. We then compare the obtained thermal conductivity data with experimental measurements to prove the excellent model agreement with the experimental trends. The parameterized thermal conductivity data are then used in the higher level modeling of self-heating effects in fully-depleted (FD) SOI devices from different technology generations. We find that temperature and thickness dependent modeling of the thermal conductivity is essential for the 25 nanometers technology node. We have also taken into account the anisotropy of the thermal conductivity and modeled devices with (100) and (110) crystallographic orientation. We found out that from thermal point of view the (110) device behaves better, but the (100) device has higher on-current.     

A study of threshold voltage fluctuations of nanoscale double gate metal-oxide-semiconductor field effect transistors using quantum correction simulation

In this paper, we computationally investigate fluctuations of the threshold voltage introduced by random dopants in nanoscale double gate metal-oxide-semiconductor field effect transistors (DG MOSFETs). To calculate variance of the threshold voltage of nanoscale DG MOSFETs, a quantum correction model is numerically solved with the perturbation and the monotone iterative techniques. Fluctuations of the threshold voltage resulting from the random dopant, the gate oxide thickness, the channel film thickness, the gate channel length, and the device width are calculated. Quantum mechanical and classical results have similar prediction on fluctuations of the threshold voltage with respect to different designing parameters including dimension of device geometry as well as the channel doping. Fluctuation increases when the channel doping, the channel film thickness, and/or the gate oxide thickness increase. On the other hand, it decreases when the channel length and/or the device width increase. Calculations of the quantum correction model are quantitatively higher than that of the classical estimation according to different quantum confinement effects in nanoscale DG MOSFETs. Due to good channel controllability, DG MOSFETs possess relatively lower fluctuation, compared with the fluctuation of single gate MOSFETs (less than a half of the fluctuation[-11pc] of SG MOSFETs). To reduce fluctuations of the threshold voltage, epitaxial layers on both sides of channel with different epitaxial doping are introduced. For a certain thickness of epitaxial layers, the fluctuation of the threshold voltage decreases when epitaxial doping decreases. In contrast to conventional quantum Monte Carlo approach and small signal analysis of the Schrödinger-Poisson equations, this computationally efficient approach shows acceptable accuracy and is ready for industrial technology computer-aided design application.     

The role of the source and drain contacts on self-heating effect in nanowire transistors

We find that self-heating effects are not pronounced in silicon nanowire transistors with channel length 10 nm even in the presence of the wrap-around oxide. We observe a maximum current degradation of 6% for V _G =V _D =1.0 V in a structure in which the metal gates are far away from the channel. The overall small current degradation is attributed to the significant velocity overshoot effect in these structures. The lattice temperature profile shows moderate temperature rise and velocity of the carriers is slightly deteriorated due to self-heating effects when compared to isothermal simulations.     

Modeling gate-all-around Si/SiGe MOSFETs and circuits for digital applications

Apart from excellent electrostatic capability and immunity to short-channel effects, the performance of gate-all-around (GAA) nanowire (NW) metal-oxide-semiconductor field-effect transistors (MOSFETs) can be further enhanced by incorporating strain. Owing to the technological importance of strained GAA (S-GAA) NW MOSFETs in modern electronics, we have proposed an analytical model of the threshold voltage and drain current for S-GAA NW MOSFETs taking into account the appreciable contributions of source (S) and drain (D) series resistances in the nanometer regime, along with quantum mechanical effect. We have focused on the elliptical cross section of the device as is necessary to consider the fabrication imperfections which give rise to such cross section, rather than an ideal circular structure. Incorporating S/D series resistance in the model of drain current demands for algorithms based on multi-iterative technique, which has been proposed in this paper for analyzing the impact of strain, NW width, aspect ratio and so on, on the performance of S-GAA NW devices with emphasis on CMOS digital circuits. Based on our proposed methodology, we have also investigated the scope of using high-k dielectric materials and metal gate in S-GAA NW structures.     

Physics-based drain current modeling of gate-all-around junctionless nanowire twin-gate transistor (JN-TGT) for digital applications

Vertically stacked dielectric separated independently controlled gates can be used to realize dual-threshold voltage on a single silicon channel MOS device. This approach significantly reduces the effective layout area and is similar to merging two transistors in series. This multiple independent gate device enables the design of new class of compact logic gates with low power and reduced area. In this paper, we present the junctionless concept based twin gate transistor for digital applications. To analyse the appropriate behaviour of device, this paper presents the modeling, simulation and digital overview of novel gate-all-around junctionless nanowire twin-gate transistor for advanced ultra large scale integration technology. This low power single MOS device gives the full functionality of “AND” gate and can be extended to full functionality of 2-input digital “NAND” gate. To predict accurate behaviour, a physics based analytical drain current model has been developed which also includes the impact of gate depleted source/drain regions. The developed model is verified using ATLAS 3D device simulator. This single channel device can function as “NAND” gate even at low operating voltage.     

Comprehensive approach to modeling threshold voltage of nanoscale strained silicon SOI MOSFETs

A comprehensive approach for modeling the threshold voltage of nanoscale strained silicon-on-insulator (SSOI) and strained Si-on-SiGe-on-insulator (SSGOI) MOSFETs is presented. The model includes the effect of strain in terms of Ge mole fraction and various other device parameters—channel length, channel doping, strained silicon film thickness, gate oxide thickness and gate work function. The accuracy of the proposed threshold voltage model is verified using two-dimensional numerical simulations. We have also demonstrated that our model can accurately predict the DIBL effects.     

Ballistic Transport in SiGe and Strained-Si MOSFETs

We investigate the performance of bulk silicon and strained-silicon nanoscale MOSFETs in the ballistic regime, with the purpose of identifying possible advantages of silicon-germanium technology in devices approaching the ballistic regime. Investigation is performed with a 2D program that solves in a self-consistent way the Poisson equation, the Schrödinger equation with density functional theory, and the continuity equation for ballistic electrons. In the ballistic regime, when mobility has no physical meaning, strained-silicon FETs seem only to provide smaller short channel effects, but no improvement as far as transconductance and drive current are concerned.     

Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review

This paper examines the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed high-performing ULSI applications. The review assesses recent proposals to circumvent the SCE in SOI MOSFETs and a short evaluation of strengths and weaknesses specific to each attempt is presented. A new device structure called the dual-material gate (DMG) SOI MOSFET is discussed and its efficacy in suppressing SCEs such as drain-induced barrier lowering (DIBL), channel length modulation and hot-carrier effects, all of which affect the reliability of ultra-small geometry MOSFETs, is assessed.     

GaN-based double-gate (DG) sub-10-nm MOSFETs: effects of gate work function

Double-gate (DG) metal–oxide–semiconductor field-effect transistors (MOSFETs) with GaN channel material are very promising for use in future high-performance low-power nanoscale device applications. In this work, GaN-based sub-10-nm DG-MOSFETs with different gate work function, \(\varPhi \), were designed and their performance evaluated. Short-channel effects (SCEs) were significantly reduced by introduction of gates made of dual metals. Use of gold at the source side, having higher \(\varPhi \) (\(\varPhi _{\mathrm{Au}}=5.11\,\hbox {eV}\)) compared with aluminum (\(\varPhi _{\mathrm{Al}}=4.53\,\hbox {eV}\)), at the drain side enhanced the gate control over the channel and screened the effect of the drain on the channel. Dual-metal (DM) DG-MOSFETs showed better results in the nanoscale regime and were more robust to SCEs. Therefore, GaN-based sub-10-nm DM DG-MOSFETs are suitable candidates for use in future complementary metal–oxide–semiconductor (CMOS) technology.