Threshold voltage-minimum gate length trade-off in buried channelPMOS devices for scaled supply voltage CMOS technologies

The trade-off between threshold voltage (V_th) and the minimum gate length (L_min) is discussed for optimizing the performance of buried channel PMOS transistors for low voltage/low power high-speed digital CMOS circuits. In a low supply voltage CMOS technology it is desirable to scale V_th and L_min for improved circuit performance. However, these two parameters cannot be scaled independently due to the channel punch-through effect. Statistical process/device modeling, split lot experiments, circuit simulations, and measurements are performed to optimize the PMOS transistor current drive and CMOS circuit speed. We show that trading PMOS transistor V_th for a smaller L_min results in faster circuits for low supply voltage (3.3 to 1.8 V) n⁺-polysilicon gate CMOS technology, Circuit simulation and measurements are performed in this study. Approximate empirical expressions are given for the optimum buried channel PMOS transistor V _th for minimizing CMOS circuit speed for cases involving: (1) constant capacitive load and (2) load capacitance proportional to MOS gate capacitance. The results of the numerical exercise are applied to the centering of device parameters of a 0.5 μm 3.3 V CMOS technology that (a) matches the speed of our 0.5 μm 5 V CMOS technology, and (b) achieves good performance down to 1.8 V power supply. For this process the optimum PMOS transistor V_th (absolute value) is approximately 0.85-0.90 V     

An α-immune, 2-V supply voltage SRAM using a polysilicon PMOSload cell

The key technology for achieving the low-voltage operation is shown to be a polysilicon PMOS load (PPL) cell. The polysilicon PMOS device is successfully stacked on the bulk MOSFET, using 0.5-μm CMOS technology. The investigation emphasizes the soft error rate (SER) and the stability of the cell. The SER of the PPL cell at a supply voltage of 2 V is comparable to that of the conventional high-resistivity polysilicon load cell at a supply voltage of 5 V. The cell stability is also improved using a PPL cell, so that the low-voltage operation is assured     

Advanced TFT SRAM cell technology using a phase-shift lithography

An advanced TFT memory cell technology has been developed for making high-density and high-speed SRAM cells. The cell is fabricated using a phase-shift lithography that enables patterns with spaces of less than 0.25 μm to be made using the conventional stepper. Cell area is also reduced by using a small cell-ratio and a parallel layout for the transistor. Despite the small cell-ratio, stable operation is assured by using advanced polysilicon PMOS TFT's for load devices. The effect of the Si₃N₄ multilayer gate insulator on the on-current and the influence of the channel implantation are also investigated. To obtain stable operation and extremely low stand-by power dissipation, a self-aligned offset structure for the polysilicon PMOS TFT is proposed and demonstrated. A leakage current of only 2 fA/cell and an on-/off-current ratio of 4.6×10⁶ are achieved with this polysilicon PMOS TFT in a memory cell, which is demonstrated in a experimental 1-Mbit CMOS SRAM chip that has an access time of only 7 ns     

A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current senseamplifiers

A 4-Mb CMOS SRAM with 3.84 μm² TFT load cells is fabricated using 0.25-μm CMOS technology and achieves an address access time of 6 ns at a supply voltage of 2.7 V. The use of a current sense amplifier that is insensitive to its offset voltage enables the fast access time. A boosted cell array architecture allows low voltage operation of fast SRAM's using TFT load cells     

A 9-ns 1-Mbit CMOS SRAM

A 1-Mbit CMOS static RAM (SRAM) with a typical address access time of 9 ns has been developed. A high-speed sense amplifier circuit, consisting of a three-stage PMOS cross-coupled sense amplifier with a CMOS preamplifier, is the key to the fast access time. A parallel-word-access redundancy architecture, which causes no access time penalty, was also incorporated. A polysilicon PMOS load memory cell, which had a large on-current-to-off-current ratio, gave a much lower soft-error rate than a conventional high-resistance polysilicon load cell. The 1-Mbit SRAM, fabricated using a half-micrometer, triple-poly, and double-metal CMOS technology, operated at a single supply voltage of 5 V. An on-chip power supply converter was incorporated in the SRAM to supply a partial internal supply voltage of 4 V to the high-performance half-micrometer MOS transistors.<>     

基于标准CMOS工艺的新型pH值传感器

基于0.6μmCMOS工艺设计了一种新型的pH值传感器。多晶硅和双层金属电极形成复合的悬浮栅结构,Si3N4钝化层作为敏感层。传感单元为W/L=500μm/20μm的PMOS管,其阈值电压随溶液pH值线性变化,并通过恒定PMOS管源漏电压和源漏电流控制电路转换成PMOS管源电压线性输出。PMOS管源电压线性输出范围达到4.6V,很好满足在不同pH值溶液中测试的要求。采用波长396nm紫外灯管照射来消除浮栅上电荷,增大阈值电压并有效调整溶液栅电压线性区工作范围。紫外照射后溶液栅电压可偏置在0V,减少溶液中噪声影响。CMOSpH值传感器的平均灵敏度为35.8mV/pH。     

一种面向单片DC/DC的低压高效片上电流检测技术

本文提出并实现了一种面向电流模式单片开关DC/DC转换器的低压高效片上电流采样电路.该电路利用功率管等效电阻电流检测技术和无需OP放大器的源极输入差分电压放大技术,使电路的应用范围可低达2.3V;-3dB带宽12MHz;在最大负载电流情况下的静态电流峰值仅19μA,比常规采用功率管镜像电流检测技术的静态电流峰值低1.5个量级左右.转换器基于0.5μm 2P3M Mixed Signal CMOS工艺设计制作.测试结果表明,电流检测电路的最大检测电流1.1A,转换器的输入最低电压2.3V,重负载转换效率高于93%.     

A 23-ns 4-Mb CMOS SRAM with 0.2-μA standby current

A 4-Mb CMOS SRAM having 0.2-μA standby current at a supply voltage of 3 V has been developed. Current-mirror/PMOS cross-coupled cascade sense-amplifier circuits have achieved the fast address access time of 23 ns. A new noise-immune data-latch circuit has attained power-reduction characteristics at a low operating cycle time without access delay. A 0.5-μm CMOS, four-level poly, two-level metal technology with a polysilicon PMOS load memory cell, yielded a small cell area of 17 μm² and the very small standby current. A quadruple-array, word-decoder architecture allowed a small chip area of 122 mm²     

A 1 ns, 1 W, 2.5 V, 32 Kb NTL-CMOS SRAM macro using a memory cellwith PMOS access transistors

While an ECL-CMOS SRAM can achieve both ultra high speed and high density, it consumes a lot of power and cannot be applied to low power supply voltage applications. This paper describes an NTL (Non Threshold Logic)-CMOS SRAM macro that consists of a PMOS access transistor CMOS memory cell, an NTL decoder with an on-chip voltage generator, and an automatic bit line signal voltage swing controller. A 32 Kb SRAM macro, which achieves a 1 ns access time at 2.5 V power supply and consumes a mere 1 W, has been developed on a 0.4 μm BiCMOS technology     

Threshold voltage-related soft error degradation in a TFT SRAM cell

This is the first report of abnormal behavior in the soft error rate (SER) dependence on supply voltage (Vcc) for a bottom-gated polysilicon PMOS thin-film transistor (TFT) static random access memory (SRAM). We found that the TFT SER does not continuously improve (as is expected and desirable) with increasing Vcc when Vcc exceeds -Vth (threshold voltage) of the TFT within a range of about 0-2 V. This was confirmed with samples of TFT with Vth intentionally varied from 0 to -5 V (by adjusting channel doping). A possible explanation of this Vcc independence is proposed in the form of a SPICE simulation with as little as a 0.1-V TFT transient Vth shift due to the TFT's floating body. The accelerated SER was measured by using an Americium alpha particle source.     

A 46-ns 1-Mbit CMOS SRAM

A 1-Mb (128 K×8-bit) CMOS static RAM (SRAM) with high-resistivity load cell has been developed with 0.8-μm CMOS process technology. Standby power is 25 μW, active power 80 mW at 1-MHz WRITE operation, and access time 46 ns. The SRAM uses a PMOS bit-line DC load to reduce power dissipation in the WRITE cycle, and has a four-block access mode to reduce the testing time. A small 4.8×8.5-μm² cell has been realized by triple-polysilicon layers. The grounded second polysilicon layer increases cell capacitance and suppresses α-particle-induced soft errors. The chip size is 7.6×12.4 mm²     

0.5-μm 2 M-transistor BiPNMOS channelless gate array

A channelless gate array has been realized using 0.5-μm BiCMOS technology integrating more than two million transistors on a 14-mm×14.4-mm chip. A small-size PMOS transistor and a small-size inverter are added to the conventional BiNMOS gate to form the BiPNMOS gate. The gate is suitable for 3.3-V supply and achieves 230-ps gate delay for a two-input NAND with full-swing output. Added small-size MOS transistors in the BiPNMOS basic cell can also be used for memory macros effectively. A test chip with four memory macros-a high-speed RAM, a high-density RAM, a ROM, and a CAM macro-was fabricated. The high-speed memory macros utilize bipolar transistors in bipolar middle buffers and in sense amplifiers. The high-speed RAM macro achieves an access time of 2.7 ns at 16-kb capacity. The high-density RAM macro is rather slow but the memory cell occupies only a half of the BiPNMOS basic cell using a single-port memory cell     

Self-start-up fully integrated DC-DC step-up converter using body biasing technique for energy harvesting applications

An ultra-low power, self-start-up switched-capacitor Two Branch Charge Pump (TBCP) circuit for low power, low voltage, and battery-less implantable applications is proposed. In order to make feasible the low voltage operation, the proposed charge pump along with Non-Overlapped Clock generator (NOC) are designed working in sub-threshold region by using body biasing technique. A four-stage TBCP circuit is implemented with both NMOS and PMOS transistors to provide a direct load flow. This leads to a significant drop in reverse charge sharing and switching loss and accordingly improves pumping efficiency. A post-layout simulation of designed four-stage TBCP has been performed by using an auxiliary body biasing technique. Consequently, a low start-up voltage of 300 mV with a pumping efficiency of 95% for 1 pF load capacitance is achieved. The output voltage can rise up-to 1.88 V within 40 μs with 0.2% output voltage ripple in case of using 400 mV power supply. The designed circuit is implemented by 180-nm standard CMOS technology with an effective chip area of 130.5 μm × 141.8 μm while the whole circuit consumes just 3.2 μW.     

A 64-bit carry look ahead adder using pass transistor BiCMOS gates

This paper describes a 64-bit two-stage carry look ahead adder utilizing pass transistor BiCMOS gate. The new pass transistor BiCMOS gate has a smaller intrinsic delay time than conventional BiCMOS gates. Furthermore, this gate has a rail-to-rail output voltage. Therefore the next gate does not have a large degradation of its driving capability. The exclusive OR and NOR gate using the pass transistor BiCMOS gate shows a speed advantage over CMOS gates under a wide variance in load capacitance. The pass transistor BiCMOS gates were applied to full adders, carry path circuits, and carry select circuits. In consequence, a 64-bit two-stage carry look ahead adder was fabricated using a 0.5 μm BiCMOS process with single polysilicon and double-metal interconnections. A critical path delay time of 3.5 ns was observed at a supply voltage of 3.3 V. This is 25% better than the result of the adder circuit using CMOS technology. Even at the supply voltage of 2.0 V, this adder is faster than the CMOS adder     

Reliability analysis of spin transfer torque based look up tables under process variations and NBTI aging

Spin transfer torque (STT) switching realized using a magnetic tunnel junction (MTJ) device has shown great potential for low power and non-volatile storage. A prime application of MTJs is in building non-volatile look up tables (LUT) used in reconfigurable logic. Such LUTs use a hybrid integration of CMOS transistors and MTJ devices. This paper discusses the reliability of STT based LUTs under transistor and MTJ variations in nano-scale. The sources of process variations include both the CMOS device related variations and the MTJ variations. A key part of the STT based LUTs is the sense amplifier needed for reading out the MTJ state. We compare the voltage and current based sensing schemes in terms of the power, performance, and reliability metrics. Based on our simulation results in a 16 nm bulk CMOS, for the same total device area, the voltage sensing scheme offers 17% to 28% lower failure rates under combined intra-die transistor and MTJ variations, comparable delay, and 56% lower active power compared to the current sensing scheme. Moreover, we compare the reliability of the two sensing schemes under negative bias temperature instability (NBTI) of PMOS transistors. Our results indicate that the failures rates increase over time by transistor aging for both designs, and the voltage sensing scheme maintains its improved failure rate over to the current sensing scheme.     

A 25-ns 4-Mbit CMOS SRAM with dynamic bit-line loads

A 25-ns 4-Mbit CMOS SRAM with 512 K word*8-bit organization has been developed. The RAM was fabricated using a 0.5- mu m double-poly and double-aluminum CMOS technology and was assembled in a 32-pin 400-mil DIP. A small cell size of 3.6*5.875 mu m/sup 2/ and a chip size of 7.46*17.41 mm/sup 2/ were obtained. A fast address access time of 25 ns with a single 3.3-V supply voltage has been achieved using the newly developed dynamic bit-line load (DBL) circuit scheme incorporated with an address transition detector (ATD), divided word-line structure (DWL), three-stage sense amplifier, and low-noise output circuit approach. A low operating current of 46 mA at 40 MHz and low standby currents of 70 mu A (TTL) and 5 mu A (CMOS) were also attained.<>     

Half-V/SUB DD/ bit-line sensing scheme in CMOS DRAMs

A sensing scheme in which the bit line is precharged to half V/SUB DD/ is introduced for CMOS DRAMs. The proposed circuitry uses a PMOS memory array and incorporates the following features: (1) a complementary sense amplifier consisting of NMOS and PMOS cross-coupled pairs; (2) clocked pulldown of the latching node; (3) complementary clocking of the PMOS pullup; (4) full-sized dummy cell generation of reference potential for sensing; (5) shorting transistor to equalize precharge potential of bit lines; and (6) depletion NMOS decoupling transistors for multiplexing bit lines. The study shows that the half-V/SUB DD/ bit-line sensing scheme has several unique advantages, especially for high-performance high-density CMOS DRAMs, which compared to the full-V/SUB DD/ bit-line sensing scheme used for NMOS memory arrays or the grounded bit-line sensing scheme for PMOS arrays in CMOS DRAMs.     

A Low Supply Voltage VCO Implemented by a Single Common-Source 90 nm CMOS Transistor

A novel voltage controlled oscillation (VCO) topology using 90-m CMOS technology is demonstrated. The common-source PMOS single transistor integrated with an inductor leads to negative resistance for the VCO that minimizes the transistor size and decreases the flicker noise sources. To our knowledge, the topology of the core VCO is the most compact configuration ever reported. The fabricated VCO consumes 6.26mW with a supply voltage of 1 V and has a 1.68times1.41 mm² chip area, including the ESD protection circuit. At 1.77 GHz, PMOS VCO features an output power in the range of -5.2 dBm, and exhibits a phase noise of -94 dBc/Hz at the offset frequency of 300 kHz and -107 dBc/Hz at 1MHz     

A 1-V 46-ns 16-Mb SOI-DRAM with body control technique

A low-voltage high-speed 16-Mb SOI-DRAM has been developed using a 0.5-μm CMOS/SIMOX technology. A newly introduced “FD-PD mode switching” transistor dynamically switches its operation mode between fully depleted (FD) and partially depleted (PD) according to the body bias voltage, thus it has both PD-mode large current drivability and FD-mode small leakage current. By the body bias control, the transistor operates as if it has an S-factor of 30 mV/decade. Enabling both high speed and low power at a low voltage, 30 mV is only one-half the theoretical value. By utilizing the transistor, we have developed body pulsed sense amplifier (BPS), body driven equalizer (BDEQ), body current clamper (BCC), and body pulsed transistor logic (BPTL) to achieve 46 ns access time at 1 V power supply with suppressed standby current     

1-V power supply high-speed digital circuit technology withmultithreshold-voltage CMOS

1-V power supply high-speed low-power digital circuit technology with 0.5-μm multithreshold-voltage CMOS (MTCMOS) is proposed. This technology features both low-threshold voltage and high-threshold voltage MOSFET's in a single LSI. The low-threshold voltage MOSFET's enhance speed performance at a low supply voltage of 1 V or less, while the high-threshold voltage MOSFET's suppress the stand-by leakage current during the sleep period. This technology has brought about logic gate characteristics of a 1.7-ns propagation delay time and 0.3-μW/MHz/gate power dissipation with a standard load. In addition, an MTCMOS standard cell library has been developed so that conventional CAD tools can be used to lay out low-voltage LSI's. To demonstrate MTCMOS's effectiveness, a PLL LSI based on standard cells was designed as a carrying vehicle. 18-MHz operation at 1 V was achieved using a 0.5-μm CMOS process