Optimal design of the multiple-apertures-GaN-based vertical HEMTs with $$\hbox {SiO}_{2}$$ current blocking layer

Gallium nitride (GaN) based vertical high electron mobility transistor (HEMT) is very crucial for high power applications. Combination of advantageous material properties of GaN for high speed applications and novel vertical structure makes this device very beneficial for high power application. To improve the device performance especially in high drain bias condition, a novel GaN based vertical HEMT with silicon dioxide \((\hbox {SiO}_{2})\) current blocking layer (CBL) was reported recently. In this paper, effects of the thickness of CBL layer and the aperture length on the electrical and breakdown characteristics of GaN vertical HEMTs with \(\hbox {SiO}_{2}\) CBL are simulated by using two-dimensional quantum-mechanically corrected device simulation. Intensive numerical study on the device enables us to optimize and conclude that devices with \(0.5\hbox {-}\upmu \hbox {m}\)-thick \(\hbox {SiO}_{2}\) layer and \(1\hbox {-}\upmu \hbox {m}\)-long aperture will be beneficial considerations to improve the device performance. Notably, using the multiple apertures can effectively reduce the on-state conducting resistance of the device. On increasing the number of apertures, the drain current is increased but the breakdown voltage is decreased. Therefore, device with four apertures is taken as an optimized result. The maximum drain current of 84 mA at \(\hbox {V}_\mathrm{G}= 1\,\hbox {V}\) and \(\hbox {V}_\mathrm{D}= 30\,\hbox {V}\), and the breakdown voltage of 480 V have been achieved for the optimized device.     

Ambipolar leakage suppression in electron–hole bilayer TFET: investigation and analysis

In this paper, we propose and simulate two new structures of electron–hole bilayer tunnel field-effect transistors (EHBTFET). The proposed devices are n-heterogate with \(\hbox {M}_{1}\) as overlap gate, \(\hbox {M}_{2}\) as underlap gate and employs a high-k dielectric pocket in the drain underlap. Proposed structure 1 employs symmetric underlaps (Lgs = Lgd = Lu). The leakage analysis of this structure shows that the lateral ambipolar leakage between channel and drain is reduced by approximately three orders, the OFF-state leakage is reduced by one order, and the \(I_{\mathrm{ON}}/I_{\mathrm{OFF}}\) ratio is increased by more than one order at \(V_\mathrm{{GS}}=V_{\mathrm{DS}} =1.0\) V as compared to the conventional Si EHBTFET. The performance is improved further by employing asymmetric underlaps (\(\hbox {Lgs}\ne \hbox {Lgd}\)) with double dielectric pockets at source and drain, called as proposed structure 2. The pocket dimensions have been optimized, and an average subthreshold swing of 17.7 mV/dec (25.5% improved) over five decades of current is achieved with an ON current of \(0.23~\upmu \hbox {A}/\upmu \hbox {m}\) (11% improved) in proposed structure 2 in comparison with the conventional EHBTFET. Further, the parasitic leakage paths between overlap/underlap interfaces are blocked and the OFF-state leakage is reduced by more than two orders. A high \(I_{\mathrm{ON}}/I_{\mathrm{OFF}}\,\hbox {ratio}~>10^{9}\) (two orders higher) is achieved at \(V_{\mathrm{DS}} =V_{\mathrm{GS}} =1.0~\hbox {V}\) in the proposed structure 2 in comparison with the conventional one.     

Analog and RF performance of doping-less tunnel FETs with $$\hbox {Si}_{0.55} \hbox {Ge}_{0.45}$$ source

This paper reports studies of a doping-less tunnel field-effect transistor (TFET) with a \(\hbox {Si}_{0.55} \hbox {Ge}_{0.45}\) source structure aimed at improving the performance of charge-plasma-based doping-less TFETs. The proposed device achieves an improved ON-state current (\(I_{{\mathrm{ON}}} \sim {4.88} \times {10}^{-5}\,{\mathrm{A}}/\upmu {\mathrm{m}}\)), an \(I_\mathrm{ON}/I_\mathrm{OFF}\) ratio of \({6.91} \times {10}^{12}\), an average subthreshold slope (\(\hbox {AV-SS}\)) of \(\sim \) \({64.79}\,{\mathrm{mV/dec}}\), and a point subthreshold slope (SS) of 14.95 mV/dec. This paper compares the analog and radio of frequency (RF) parameters of this device with those of a conventional doping-less TFET (DLTFET), including the transconductance (\(g_{{\mathrm{m}}}\)), transconductance-to-drain-current ratio \((g_\mathrm{m}/I_\mathrm{D})\), output conductance \((g_\mathrm{d})\), intrinsic gain (\(A_{{\mathrm{V}}}\)), early voltage (\(V_{{\mathrm{EA}}}\)), total gate capacitance (\( C_{{\mathrm{gg}}}\)), and unity-gain frequency (\(f_{{\mathrm{T}}}\)). Based on the simulated results, the \(\hbox {Si}_{0.55}\hbox {Ge}_{0.45}\)-source DLTFET is found to offer superior analog as well as RF performance.     

Analog performance investigation of dual electrode based doping-less tunnel FET

In this paper, we have proposed a device and named it dual electrode doping-less TFET (DEDLTFET), in which electrodes on top and bottom of source and drain are considered to enhance the ON state current and Analog performances. The charge plasma technique is used to generate electron’s and hole’s clouding depending upon their respective work functions at top and bottom of source/drain electrode. Band-to-band-tunneling rate is similar on both sides of source-channel junctions, which increases ON state current. The analog performance parameters of DEDLTFET are investigated and using device simulation the demonstrated characteristics are compared with doping-less (DLTFET) and the conventional doped double gate TFET (DGTFET), such as transconductance \((\hbox {g}_\mathrm{m})\), transconductance to drain current ratio \((\hbox {g}_\mathrm{m}/\hbox {I}_\mathrm{D})\), output-conductance (g\(_{d})\), output resistance \((\hbox {r}_\mathrm{d})\), early voltage \((\hbox {V}_\mathrm{EA})\), intrinsic gain \((\hbox {A}_\mathrm{V})\), total gate capacitance \((\hbox {C}_\mathrm{gg})\) and unity gain frequency \((\hbox {f}_\mathrm{T})\). From the simulation results, it is observed that DEDLTFET has significantly improved analog performance as compared to DGTFET and DLTFET.     

Design and structural optimization of junctionless FinFET with Gaussian-doped channel

A junctionless (JL) fin field-effect transistor (FinFET) structure with a Gaussian doping distribution, named the Gaussian-channel junctionless FinFET, is presented. The structure has a nonuniform doping distribution across the device layer and is designed with the aim of improving the mobility degradation caused by random dopant fluctuations in JL FinFET devices. The proposed structure shows better performance in terms of ON-current (\(I_{\mathrm{ON}}\)), OFF-current (\(I_{\mathrm{OFF}}\)), ON-to-OFF current ratio (\(I_{\mathrm{ON}}{/}I_{\mathrm{OFF}}\)), subthreshold swing, and drain-induced barrier lowering. In addition, we optimized the structure of the proposed design in terms of doping profile, spacer width, gate dielectric material, and spacer dielectric material.     

20-nm T-gate composite channel enhancement-mode metamorphic HEMT on GaAs substrates for future THz applications

In this paper, the RF and DC behaviours of a SiN-passivated 20-nm gate length metamorphic high electron mobility transistor (MHEMT) on GaAs substrate with \({\updelta }\)-doped sheets on either side of the composite channel are studied using the Synopsys TCAD tool. The 20-nm enhancement-mode MHEMT with \({\updelta }\)-doped sheets on either side of the \(\hbox {In}_{0.75}\hbox {Ga}_{0.25}\hbox {As}\)/InAs/ \(\hbox {In}_{0.75}\hbox {Ga}_{0.25}\hbox {As}\) multilayer channel shows a transconductance of 3000 mS/mm, cut-off frequency (\({f}_{\mathrm{T}}\)) of 760 GHz and a maximum-oscillation frequency (\({f}_{\mathrm{max}}\)) of 1270 GHz. The threshold voltage of the device is found to be 0.07 V. The room-temperature Hall mobilities of the two-dimensional sheet charge density (2DEG) are measured to be over \(12800\,\hbox {cm}^{2}\)/Vs with a sheet charge density larger than 4 \(\times \) \(10^{12}\,\hbox {cm}^{-2}\). These high-performance enhancement-mode MHEMTs are attractive candidates for future terahertz applications such as high-resolution radars for space research and also for low-noise wide-bandwidth amplifier for future communication systems.     

Heterogate junctionless tunnel field-effect transistor: future of low-power devices

Gate dielectric materials play a key role in device development and study for various applications. We illustrate herein the impact of hetero (high-k/low-k) gate dielectric materials on the ON-current (\(I_{\mathrm{ON}}\)) and OFF-current (\(I_{\mathrm{OFF}}\)) of the heterogate junctionless tunnel field-effect transistor (FET). The heterogate concept enables a wide range of gate materials for device study. This concept is derived from the well-known continuity of the displacement vector at the interface between low- and high-k gate dielectric materials. Application of high-k gate dielectric material improves the internal electric field in the device, resulting in lower tunneling width with high \(I_{\mathrm{ON}}\) and low \(I_{\mathrm{OFF}}\) current. The impact of work function variations and doping on device performance is also comprehensively investigated.     

Nanoscale circuit implementation using tri-metal gate engineered nanowire MOSFET with gate stack for analog/RF applications

In this work, the potential benefit of tri-metal gate engineered nanowire MOSFET with gate stack for analog/RF applications is developed and presented. A systematic, quantitative investigation of main figure of merit for the device is carried out to demonstrate its improved RF/analog performance. The results show an improvement in drain current, \(I_{\mathrm{on}} /I_{\mathrm{off}}\) ratio, transconductance, unity-gain frequency (\(f_{\mathrm{T}}\)), maximum oscillation frequency (\(f_{\mathrm{max}}\)) providing superior RF performance as compared to single and dual-metal gate stack nanowire MOSFET. The suitability of the device for analog/RF applications is also analyzed by implementing the device in a low-noise amplifier circuit, and the S-parameter values are estimated.     

Series and parallel resistance effects on the C–V and G–V characteristics of $$\mathrm{Al}/\mathrm{SiO}_{2}$$/Si structure

This paper investigates the electrical behavior of the C–V and G–V characteristics of \(\mathrm{Al}/\mathrm{SiO}_{2}/\mathrm{Si}\) structure. The modeling of capacitance and conductance has been developed from complex admittance treatment applied to the proposed equivalent circuit. Poisson transport equations have been used to determine the charge density, surface potential, total capacitance, and flatband and threshold voltages as a function of the gate voltage, frequency (\(\omega )\), and series \(({R}_{\mathrm{s}})\) and parallel \(({R}_{\mathrm{p}})\) resistances. Results showed a frequency dispersion of C–V and G–V curves in both accumulation and inversion regimes. With increasing frequency, the accumulation capacitance is decreased, whereas the conductance is strongly increased. The shape, dispersion, and degradation of C–V and G–V characteristics are more influenced when parallel and series resistances \((\mathrm{R}_{\mathrm{s}}\), \(\mathrm{R}_{\mathrm{p}})\) are dependent to substrate doping density. The variation of \(\mathrm{R}_{\mathrm{s}}\) and \(\mathrm{R}_{\mathrm{p}}\) values led to a reduction of flatband voltage from ?1.40 to ?1.26 V and increase of the threshold voltage negatively from ?0.28 to ?0.74 V. A good agreement has been observed between simulated and measured C–V and G–V curves obtained at high frequency.     

A novel symmetrical 4H–SiC MESFET: an effective way to improve the breakdown voltage

In this paper, a novel symmetrical structure (SS) of 4H–SiC metal semiconductor field effect transistor (MESFET) as an effective way to improve the breakdown voltage is presented. The key idea in this work is to improve the breakdown voltage, maximum output power density, and frequency parameters of the device using a symmetrical structure with recessed gate. The SS-MESFET modifies the electric field in the drift layer significantly. The influence of the SS-MESFET on the saturation current, breakdown voltage \((\hbox {V}_{\mathrm{BR}})\), and small-signal characteristics of the SS-MESFET are studied by numerical device simulation. Using two-dimensional device simulation, we demonstrate that the breakdown voltage \((\hbox {V}_{\mathrm{BR}})\) improved by factors 2.5 and 3.3 in comparison with an asymmetrical conventional MESFET structure (AC-MESFET) and a symmetrical conventional MESFET structure (SC-MESFET), respectively. Also, the maximum output power density \((\hbox {P}_{\mathrm{max}})\) improved about by 93 and 250 % in comparison with the AC-MESFET and SC-MESFET structures, respectively. So, the SS-MESFET shows the superior maximum available gain (MAG), unilateral power gain (U), and current gain \((\hbox {h}_{12})\) which is presenting the proposed structure is more suitable device for high power microwave applications.     

First-principle calculations of electronic and ferromagnetic properties of $$\hbox {Al}_{1-x}\hbox {V}_{x}\hbox {Sb}$$

We have used the first-principle calculations of density functional theory within full-potential linearized augmented plane-wave method to investigate the electronic and ferromagnetic properties of \(\hbox {Al}_{1-x}\hbox {V}_{x}\hbox {Sb}\) alloys. The electronic structures of \(\hbox {Al}_{0.25}\hbox {V}_{0.75}\hbox {Sb}, \hbox {Al}_{0.5}\hbox {V}_{0.5}\hbox {Sb}\) and \(\hbox {Al}_{0.75}\hbox {V}_{0.25}\hbox {Sb}\) exhibit a half-metallic ferromagnetic character with spin polarization of 100 %. The total magnetic moment per V atom for each compound is integral Bohr magneton of 2 \(\mu _{\mathrm{B}}\), confirming the half-metallic feature of \(\hbox {Al}_{1-x}\hbox {V}_{x}\hbox {Sb}\). Therefore, these materials are half-metallic ferromagnets useful for possible spintronics applications.     

Simulation-based performance analysis of an ultra-low specific on-resistance trench SOI LDMOS with a floating vertical field plate

An ultra-low specific on-resistance \((R_\mathrm{{on,sp}})\) trench SOI LDMOS with a floating vertical field plate structure (FVFPT SOI) is proposed in this paper. A floating vertical plate (FVFP) is introduced into the filled oxide trench of a conventional trench SOI LDMOS (CT SOI) to improve its electrical performance. We conduct related performance analysis to this device by simulation and investigate the effects of different parameters on its performance. The FVFP causes an assisted depletion effect especially for the trench surface regions. An ultra-low \(R_\mathrm{{on,sp}}\) is therefore obtained in the FVFP device due to higher drift region doping concentration \((N_\mathrm{{d}})\). A breakdown voltage (BV) of 188V and a \(R_\mathrm{{on,sp}}\) of \(0.9 \hbox { m}\Omega \, \hbox { cm}^{2}\) are realized on a 4.8-\({\upmu }\hbox {m}\)-long drift region, a 7.5-\({\upmu }\hbox {m}\)-thick top-silicon layer and a 0.5-\({\upmu }\hbox {m}\)-thick buried oxide (BOX) layer by our simulation. Eventually, the \(R_\mathrm{{on,sp}}\) for the FVFPT SOI can be reduced by more than 60%, while its BV is maintained the same class as the CT SOI, and the figure of merit (FOM) is enhanced by 155%. And a set of optimal parameters, including the structure parameters of plate and the property parameters of device, are obtained.     

A simulation study of voltage-assisted low-energy switching of a perpendicular anisotropy ferromagnet on a topological insulator

We present a novel memory device that consists of a thin ferromagnetic layer of Fe deposited on topological insulator thin film, \(\hbox {Bi}_{2}\hbox {Se}_{3}\). The ferromagnetic layer has perpendicular anisotropy, due to MgO deposited on its top surface. When current is passed on the surface of \(\hbox {Bi}_{2}\hbox {Se}_{3}\), the surface of the \(\hbox {Bi}_{2} \hbox {Se}_{3}\) becomes spin polarized and strong exchange interaction occurs between the d electrons in the ferromagnet and the electrons conducting the current on the surface of the \(\hbox {Bi}_{2}\hbox {Se}_{3}\). Part of the current is also shunted through the ferromagnet, which generates spin transfer torque in the ferromagnet. The exchange interaction torque along with voltage-controlled magnetic anisotropy allows ultralow-energy switching of the ferromagnet. We perform micromagnetic simulations and predict switching time of the order of 2.5 ns and switching energy of the order of 0.88fJ for a ferromagnetic bit with thermal stability of \(43\,k_\mathrm{{B}}T\). Such ultralow-energy and high-speed switching of a perpendicular anisotropy ferromagnet on a topological insulator could be utilized for energy-efficient memory design.     

Delta-doped tunnel FET (D-TFET) to improve current ratio ($$I_\mathrm{ON}/I_\mathrm{OFF}$$) and ON-current performance

A two dimensional (2D) analytical drain current model has been developed for a delta-doped tunnel field-effect transistor (D-TFET) that can address the ON-current issues of the conventional TFET. Insertion of a highly doped delta layer in the source region paves the way for improved tunneling volume and thus provides high drain current as compared with TFETs. The present model takes into account the effects of the distance between the delta-doping region and the source–channel interface on the subthreshold swing (SS), current ratio, and ON-current performance. The D-TFET is predicted to have a higher current ratio \(\left( {\frac{I_\mathrm{ON} }{I_\mathrm{OFF} }\cong 10^{11}} \right) \) compared with TFETs \(\left( {\frac{I_\mathrm{ON} }{I_\mathrm{OFF} }\cong 10^{10}} \right) \) with a reasonable SS \(\left( {{\sim }52\,\mathrm{mV/dec}} \right) \) and \(V_\mathrm{th}\) performance at an optimal position of 2 nm from the channel. The surface potential, electric field, and minimum tunneling distance have been derived using the solution of the 2D Poisson equation. The accuracy of the D-TFET model is validated using the technology computer aided design (TCAD) device simulator from Synopsys.     

Kinetic and thermodynamic heterogeneity: an intrinsic source of variability in Cu-based RRAM memories

The resistive random-access memory (RRAM) device concept is close to enabling the development of a new generation of non-volatile memories, provided that their reliability issues are properly understood. The design of a RRAM operating with extrinsic defects based on metallic inclusions, also called conductive bridge RAM, allows the use of a large spectrum of solid electrolytes. However, when scaled to device dimensions that meet the requirements of the latest technological nodes, the discrete nature of the atomic structure of the materials impacts the device operation. Using density functional theory simulations, we evaluated the migration kinetics of Cu conducting species in amorphous \(\hbox {AlO}_{\mathrm{x}}\) and \(\hbox {WO}_{\mathrm{x}}\) solid electrolyte materials, and established that atomic disorder leads to a large variability in terms of defect stability and kinetic barriers. This variability has a significant impact on the filament resistance and its dynamics, as evidenced during the formation step of the resistive filament. Also, the atomic configuration of the formed filament can age/relax to another metastable atomic configuration, and lead to a modulation of the resistivity of the filament. All these observations are qualitatively explained on the basis of the computed statistical distributions of the defect stability and on the kinetic barriers encountered in RRAM materials.     

A novel high-performance H-gate U-channel junctionless FET

A novel high-performance H-shape-gate U-shape-channel junctionless FET (HGUC JL FET) is proposed. Compared with the saddle junctionless FET, the proposed HGUC JL FET shows better subthreshold characteristics and higher on-current. Its electrical properties were extensively investigated by studying the influence of variation of design parameters such as the H-gate thickness, the source/drain extension region height, and the gate oxide thickness and material. Compared with conventional structures, the proposed HGUC JL FET shows better performance, especially on scaling down to several nanometers. The reverse leakage current is also effectively restrained and the \({I}_{\mathrm{on}}\)/\({I}_{\mathrm{off}}\) ratio greatly improved through design optimization.     

Theoretical study of structural,electronic and optical properties of novel ternary alloys $$\hbox {MgO}_{1-{x}}{\hbox {Se}}_{{x}}$$ ($$x =$$x= 0.25, 0.50 and 0.75)

We report on the investigation of the structural, electronic, and optical properties of binary compounds (MgO and MgSe) and their ternary \(\hbox {MgO}_{1-{x}}\hbox {Se}_{{x}}\) (\(x=0.25, 0.5, 0.75\)) alloys within the density functional theory based on the full-potential linearized augmented plane wave method as implemented in the WIEN2k code. We have used the revised Perdew–Burke–Ernzerhof generalized gradient approximation (GGA-PBEsol) to calculate the structural properties and analyze the effect of the Se composition on the lattice constant and the bulk modulus of \(\hbox {MgO}_{1-{x}}\hbox {Se}_{{x}}\). The calculated electronic properties by employing the GGA-PBEsol and TB-mBJ approaches show that \(\hbox {MgO}_{1-{x}}\hbox {Se}_{{x}}\) alloys have a direct band gap \(\Gamma \)–\(\Gamma \) for \(x = 0, 0.25, 0.5\) and 0.75, suggesting the possibility of their use in the long wavelength optoelectronic applications. The optical properties such as the real and imaginary parts of the dielectric function, the refractive index, and the reflectivity of \(\hbox {MgO}_{1-{x}}\hbox {Se}_{{x}}\) are computed by using the accurate TB-mBJ potential. The wide band gaps larger than 3.1 eV mean that \(\hbox {MgO}_{1-{x}}\hbox {Se}_{{x}}\) alloys can be used in the applications of the ultraviolet region of the spectrum. Our data for all studied bowing parameters of \(\hbox {MgO}_{1-{x}}\hbox {Se}_{x}\) may serve as references for future experimental studies.     

Composition dependence of fundamental properties of $$\hbox {Cd}_{\mathrm{1-x}}\hbox {Co}_\mathrm{x}$$Te magnetic semiconductor alloys

Ab initio calculations based on density functional theory have been performed using the full-potential augmented-plane-wave method so as to investigate the composition dependence of the electronic structure and fundamental properties of hypothetical zinc-blende \(\hbox {Cd}_{\mathrm{1-x}}\hbox {Co}_{\mathrm{x}}\hbox {Te}\) magnetic semiconductor alloys at low Co concentrations. To treat the exchange and correlation energies, the generalized gradient approximation (GGA) of Perdew–Burke–Ernzerhof has been used. In addition, the modified Becke–Johnson exchange potential with the GGA approach is used for the band structure providing high accuracy. It is found that the addition of a small amount of Co atoms in the \(\hbox {Cd}_{\mathrm{1-x}}\hbox {Co}_{\mathrm{x}}\hbox {Te}\) makes the latter less compressible, ferromagnetic and exhibiting a half metallic character. Besides, the composition dependence of the real and imaginary parts of the dielectric function has been examined and discussed. The information derived from the present study may be useful for spintronics technological applications.     

Transport studies of $$\hbox {CeO}_{2}$$ molecular device and adsorption behavior of CO on $$\hbox {CeO}_{2}$$ device: a first-principles investigation

Using density functional theory and the non-equilibrium Green’s function formalism, the transport and CO adsorption properties of \(\hbox {CeO}_{2}\) molecular device are studied. The band structure shows that \(\hbox {CeO}_{2}\) nanostructure exhibits semiconducting nature. The electron density is found to be more in oxygen sites rather than in cerium sites along \(\hbox {CeO}_{2}\) nanostructure. The density of states spectrum shows the variation in density of charge upon adsorption of CO on CeO\(_2\) device. The transmission spectrum provides the insights on the transition of charge in \(\hbox {CeO}_{2}\) molecular device upon adsorption of CO along the scattering region. I–V characteristics confirm the adsorption of CO with the variation of current along \(\hbox {CeO}_{2}\) molecular device. The findings show that \(\hbox {CeO}_{2}\) two probe molecular device can be efficiently used for CO detection in the atmosphere.     

Analysis and modeling of unipolar junction transistor with excellent performance: a novel DG MOSFET with $${N}^{+}{-}{P}^{-}$$ junction

We propose herein a new dual-gate metal–oxide–semiconductor field-effect transistor (MOSFET) with just a unipolar junction (UJ-DG MOSFET) on the source side. The UJ-DG MOSFET structure is constructed from an \({N}^{+}\) region on the source side with the rest consisting of a \({P}^{-}\) region over the gate and drain, forming an auxiliary gate over the drain region with appropriate length and work function (named A-gate), converting the drain to an \({N}^{+}\) region. The new structure behaves as a MOSFET, exhibiting better efficiency than the conventional double-gate MOSFET (C-DG MOSFET) thanks to the modified electric field. The amended electric field offers advantages including improved electrical characteristics, reliability, leakage current, \({I}_{\mathrm{ON}}/I_{\mathrm{OFF}}\) ratio, gate-induced drain leakage, and electron temperature. Two-dimensional analytical models of the surface potential and electric field over the channel and drain are applied to investigate the drain current in the UJ-DG MOSFET. To confirm their accuracy, the MOSFET characteristics obtained using the 2D Atlas simulator for the UJ-DG and C-DG are analyzed and compared.