High performance real-time neural scheduler for ATM switches

Input-buffered asynchronous transfer mode (ATM) packet switches are simpler than output-buffered switches. However, due to HOL blocking, their throughput is poor. Neural schedulers represent a promising solution for high throughput input-buffered switching, but their response time variance is too high for realistic hard real-time constraints. To overcome this problem, we formulate and evaluate a new neural scheduler with bounded response time     

输入缓冲结构ATM交换网络的窗口接入机理研究

本文了输入缓冲结构ＡＴＭ交换网络的窗口接入机理，首先分析了一种传统的相关窗口接入（ＤＷＡ）机理的最大吞吐率性能，然后，提出了一种独立的窗口接入（ＩＷＡ）机理，ＩＷＡ能彻底消除采用传统的ＤＷＡ机理时在输入缓冲器窗口中存在的队头阻塞现象，借助于概率母函数的方法分析了采用该ＩＷＡ机理的输入缓冲ＡＴＭ交换网络的时延和吞吐率性能，给出了求解平均信元时延和最大吞吐率的封闭显式，分析表明，ＩＷＡ机理的性能比传统     

Round-robin selection with adaptable-size frame in a combined input-crosspoint buffered switch

As an alternative to input-buffered switches, combined input-crosspoint buffered switches relax arbitration timing and provide high-performance switching for packet switches with high-speed ports. It has been shown that these switches, with one-cell crosspoint buffer and round-robin (RR) arbitration at input and output ports, provide 100% throughput under uniform traffic. However, under admissible traffic patterns with nonuniform distributions, only weight-based selection schemes are reported to provide high throughput. We propose an RR based arbitration scheme for a combined input-crosspoint buffered packet switch that provides nearly 100% throughput for several admissible traffic patterns, including uniform and unbalanced traffic, using one-cell crosspoint buffers. The presented scheme uses adaptable-size frames, so that the frame size adapts to the traffic pattern.     

A transceiver circuit for ATM networks

This paper presents a transceiver digital circuit. The circuit is responsible for the emission of packets to the asynchronous transfer mode (ATM) network as well as for the manipulation of received ATM packets belonging to virtual connections. It has been designed to support data communication services. The circuit, which can be used in terminals or in interworking units and switches, implements basic functions of the lower layers of the ATM protocol reference model. The transmission functionality includes cell buffering, header error control, cell assembling, rate coupling and information insertion. The receiver realizes information extraction, rate decoupling, cell buffering, header error detection and correction, connection identity fields extraction and identification, cell disassembling and classification, and idle cell discarding functions. The circuit has been implemented on applications specific integrated circuit (ASIC) chips.     

A new architecture of photonic ATM switches

A photonic asynchronous transfer mode (ATM) switch architecture for ATM operation at throughputs greater than 1 Tbit/s is proposed. The switch uses vertical-to-surface transmission electrophotonic devices (VSTEPs) for the optical buffer memory, and an optical-header-driven self-routing circuit in contrast with conventional photonic ATM switches using electrically controlled optical matrix switches. The optical buffer memory using massively parallel optical interconnections is an effective solution to achieve ultra-high throughput in the buffer. In the optical-header-driven self-routing circuit, a time difference method for a priority control is proposed. For the optical buffer memory, the write and read operations to and from the VSTEP memory for 1.6 Gbit/s, 8-bit optical signal are confirmed. The optical self-routing operation and priority control operation by the time difference method in the 4×4 self-routing circuit were performed by 1.6-Gbit/s 256-bit data with a 10-ns optical header pulse     

Multicast contention resolution with single-cycle windowing usingcontent addressable FIFO's

Asynchronous transfer mode (ATM) has been designated as the switching environment for future broadband integrated services digital networks (BISDN) networks and services. Although input-buffered space switches are more economical and simpler to implement than output-buffered space switches, they suffer from external blocking because of destination port contention. We review contention resolution methods used to avoid external blocking, and choose a solution based on ring reservation, resulting in an elegant and efficient mechanism requiring only nearest-neighbor communications. In addition to external blocking, space switches suffer from head-of-line (HOL) blocking, and our technique alleviates HOL blocking without arbitration time overhead. This method makes use of a novel content addressable first in/first out (CAFIFO) to achieve single-cycle windowing, and the CAFIFO design and operation are described in detail. High multicast throughput is achieved by employing call-splitting. Multiple latency priorities can also be supported. Simulation results, for both unicast and multicast switching, and both random and bursty traffic, highlight the versatility and excellent performance of the CAFIFO-based switch     

基于三角面元剖分的全波信号完整性建模方法

推导了一种采用三角面元剖分和RWG(Rao-Wilton-Glisson)基函数的部分元等效电路(PEEC)方法,在此方法中采用了离散复镜像(DCIM)来计算格林函数。对于有拐角的印刷电路板(PCB)走线,同传统PEEC的四边形剖分方法相比,采用RWG基函数定义的三角形剖分方法有更高的计算精度和计算效率;不同于一般的使用准静格林函数的PEEC方法,在高频条件下,采用离散复镜像的PEEC方法的计算结果依然准确,并可以兼容HSPICE仿真信号完整性(SI)问题。给出了联合使用PEEC和HSPICE仿真得到信号眼图的结果,将实际PCB板走线S参数的仿真结果和测量结果进行了对比。实验结果表明:RWG-DCIM-PEEC是一种有效的SI仿真与分析方法。     

模块化结构的ATM交换节点的性能分析

模块化结构是形成大容量ＡＴＭ交换节点的最有效手段，本文提出一种分析模块化结构的ＡＴＭ交换节点性能的新方法，该方法通过引入虚队列考虑了相邻模块间的相关性，与计算机模拟相比，分析结果在整个负载变化范围内都有很高的准确性，方法适用于任意大小模块并采用输出排队和以Ｂａｎｙａｎ网为互连网的ＡＴＭ交换节点的性能分析。     

Architecture design for ATM statistical multiplexers

Both high-speed packet switches and statistical multiplexers are critical elements in the ATM (asynchronous transfer mode) network. Many switch architectures have been proposed and some of them have been built, but relatively fewer statistical multiplexer architectures have been investigated to date. It has been considered that multiplexers are a special kind of switches which can be implemented with similar approaches. The main function of a statistical multiplexer, however, is to concentrate traffic from a number of input ports to a comparatively smaller number of output ports; ‘switching’ in the sense that a cell must be delivered to a specific output port is often not required. This implies that the channel grouping design principle, in which more than one path is available for each virtual circuit connection, can be applied in the multiplexer. We show that this technique reduces the required buffer memory and increases the system performance significantly. The performances of three general approaches for implementing an ATM statistical multiplexer are studied through simulations with various bursty traffic assumptions. Based on the best performing approach (sharing output channels and buffers), we propose two architecture designs to implement a scalable statistical multiplexer that is modularly decomposed into many smaller multiplexers by using a novel grouping network.     

Queueing performance of copy networks with dynamic cell splittingfor multicast ATM switching

This paper analyzes and compares the queueing performance of copy networks for multicast ATM switching. Both nonbuffered and input-buffered copy networks are studied. Particularly, the shared-input-buffering approach is investigated, and the performance improvement obtained by employing the buffer in the network is demonstrated. The effectiveness of the dynamic cell splitting scheme is presented as well     

A scalable ATM switching system architecture

The architecture of an asynchronous transfer mode (ATM) switching system for prototype applications is presented. The general concept to upgrade the existing ISDN switch with an ATM module is introduced, and the building blocks of this ATM module are described in detail. Switching of ATM cells is performed in a single application-specific integrated circuit (ASIC). ASICs can be cascaded to form large switching modules. Peripheral modules interface the ATM switch to external transmission systems and perform all ATM-related functions, including means for redundancy of the switching network. The redundancy scheme tolerates single failures without affecting the user information. A switching network architecture is shown to be capable of fulfilling varying demands in terms of the number of ports for ATM switches and cross connects, concentrators, and multiplexers     

PERFORMANCE ANALYSIS OF AN INPUT-BUFFERED ATM SWITCHING FABRIC WITH INDEPENDENT WINDOW-ACCESS SCHEME

In this paper, an Independent Window-Access(IWA) scheme is proposed, and the performance of an input-buffered ATM switching fabric with the IWA scheme is analysed by means of a probability generating function approach, the closed formulas of the average cell delay and the maximum throughput are given, and results show that the IWA scheme makes the switching fabric have better performances than traditional window-access scheme. The computer simulation results are in good agreement with these analytical results.     

Physical performance limits for shared buffer ATM switches

Performance studies, linking ATM switch capabilities to physical limitations imposed by integrated circuit technology, have been scarce. This paper explores trends in circuit capabilities, and makes projections toward the 0.25-μm technologies that will be available to all switch designers in the year 2000. The limits imposed by circuit technology are applied to shared buffer ATM switches. We determine requirements and physical limits for buffer capacity, buffer throughput, chip I/O throughput, and power dissipation. As a result, we are able to project chip counts, aggregate switch throughputs, and switch dimensions. As well, performance capabilities of single-chip shared buffer switches are estimated. A single-chip shared buffer switch implemented in 0.25-μm technology will be capable of an aggregate throughput of 1.3 Tb/s, will accomplish almost arbitrarily low cell loss rates for bursty traffic, and may be integrated together with translation tables supporting hundreds of connections per port     

Self-firing cell scheduler for input queueing ATM switches

The authors propose a simple cell scheduler for input queueing ATM switches. The proposed self-firing cell scheduler consists of N² processing elements connected by a two dimensional torus network, where each processing element can determine the diagonal by itself in a distributed manner. It allows a simple implementation for high speed ATM switches     

A 622-Mb/s 8×8 ATM switch chip set with shared multibufferarchitecture

An asynchronous transfer mode (ATM) switch chip set, which employs a shared multibuffer architecture, and its control method are described. This switch architecture features multiple-buffer memories located between two crosspoint switches. By controlling the input-side crosspoint switch so as to equalize the number of stored ATM cells in each buffer memory, these buffer memories can be treated as a single large shared buffer memory. Thus, buffers are used efficiently and the cell loss ratio is reduced to a minimum. Furthermore, no multiplexing or demultiplexing is required to store and restore the ATM cells by virtue of parallel access to the buffer memories via the crosspoint switches. Access time for the buffer memory is thus greatly reduced. This feature enables high-speed switch operation. A three-VLSI chip set using 0.8-μm BiCMOS process technology has been developed. Four aligner LSIs, nine bit-sliced buffer-switch LSIs, and one control LSI are combined to create a 622-Mb/s 8×8 ATM switching system that operates at 78 MHz. In the switch fabric, 155-Mb/s ATM cells can also be switched on the 622-Mb/s port using time-division multiplexing     

Realization of large capacity ATM switches

Large-capacity ATM switches, with switching capacity in excess of 40 Gb/s or 100 Gb/s, are becoming an essential part of network growth. To realize such switches requires technology know-how as well as implementation trade-off considerations. This article provides a system-level exploration of large-capacity ATM switches in terms of switch fabric scalability, cell buffer management, buffer design trade-off, call processing capabilities, and future trends in switch design     

RPA: a flexible scheduling algorithm for input buffered switches

This paper presents and evaluates a quasi-optimal scheduling algorithm for input buffered cell-based switches, named reservation with preemption and acknowledgment (RPA). RPA is based on reservation rounds where the switch input ports indicate their most urgent data transfer needs, possibly overwriting less urgent requests by other input ports, and an acknowledgment round to allow input ports to determine what data they can actually transfer toward the desired switch output port. RPA must be executed during every cell time to determine which cells can be transferred during the following cell time. RPA is shown to be as simple as the simplest proposals of input queuing scheduling, efficient in the sense that no admissible traffic pattern was found under which RPA shows throughput limitations, and flexible, allowing the support of packet-mode operations and different traffic classes with either strict priority discipline or bandwidth guarantee requirements. The effectiveness of RPA is assessed with detailed simulations in uniform as well as unbalanced traffic conditions and its performance is compared with output queuing switches and the optimal maximum weighted matching (MWM) algorithm for input-buffered switches. A bound on the performance difference between the heuristic weight matching adopted in RPA and MWM is analytically computed     

An ATM switch architecture for provision of integrated broadbandservices

The author gives some qualitative performance targets to be fulfilled for the service classes proposed by CCITT for the future broadband-ISDN (B-ISDN) and proposes a nonblocking, self-routing asynchronous transfer mode (ATM) switching architecture that is able to fulfil the different performance figures of each class. To exploit the service integration accomplished by ATM switches, the switching bandwidth is allocated at call level and cell level. This allocation gives the flexibility of letting lower-priority services use the reserved bandwidth left temporarily unused by higher-priority services. The architecture adopts mixed input-output queuing. Input queuing is particularly suited to the definition of internal frame structures, making it possible to guarantee the absence of cell loss due to congestion for specific services (such as circuit emulation). Output queuing makes it possible to implement in hardware a switching speedup that practically removes the performance degradation due to the head-of-line blocking phenomenon typical of input queuing     

Large-scale ATM multistage switching network with shared buffermemory switches

The configuration of an asynchronous transfer mode (ATM) switch architecture using a shared buffer memory switch (SBMS) is discussed. The scaling factors of the ATM switching network under a condition of mixed applications, including a conventional mix and telecommunication with video, are analyzed. The use of the SBMS as the unit switch for a multistage switching network is examined. A prototype system and its performance evaluation and experimental data are presented. The data indicate excellent performance under a burst cell arrival condition. The buffer size of the SBMS can be reduced in comparison with that of an individual (nonshared) buffer memory switch. A configuration for a large-scale ATM switching network with multistage switches is proposed