FPAA芯片AN10E40及其应用

可编程模拟阵列FPAA是一种可编程模拟器件 ,很适合中小型模拟电路的设计 ,文章从FPAA器件的工作原理出发 ,详细介绍了Anadigm公司的AN10E40可编程模拟芯片的主要构成及开发工具 ,最后给出了一个应用举例     

现场可编程模拟阵列AN10E40的应用开发

介绍了现场可编程模拟阵列AN10E40的基本结构、主要性能和开发过程。结合实例介绍了AnadigmDesigner软件的使用方法。     

Anadigm更新现场可编程模拟阵列

Anadigm公司推出了第二代现场可编程模拟阵列(FPAA) AN2 2 0 E0 4 ,属于其 Anadigmvortex产品范畴 ,该产品系列也结合了一套 EDA工具、可变模拟模块和可编程硅技术。与第一代 FPAA产品相比 ,它具有动态定义和实时控制性能 ,可对模拟功能进行升级和控制。AN2 2 0 E0 4应用于信号调节、过滤、数据获取和闭合环路控制时 ,可作为分立部件和模拟 ASIC/ASSP器件的替代方案。AN2 2 0 E0 4采用 44引脚 QFP封装 ,现已提供样品和量产业务。Anadigm更新现场可编程模拟阵列…     

FPAA的音频滤波器设计实例

基于开关电容的现场可编程模拟阵列(FPAA)是最近发展起来的新的模拟技术。以AN221E04芯片为切入点介绍了FPAA的硬件结构及其相应的EDA软件AnadigmDesigner2。给出一个应用实例并阐明了FPAA的一般设计方法。     

基于MCU与FPAA的均衡器系统硬件设计与测试

基于开关电容技术的FPAA(现场可编程模拟阵列)技术已取得了进一步提高,一些成熟的FPAA芯片相继推出.文中尝试使用FPAA芯片(AN221E04)实现一个全新概念的调节简便、成本低的音频均衡器设计.基于FPAA技术的巴特沃兹开关电容滤波器来实现音频均衡器滤波系统,并利用多个AN221E04芯片构建FPAA,与89S51 MCU(微控制器)及Serial EEPROM构建一个音效调节参数实时静态和动态可调的音频均衡器.     

模拟电路向FPGA学习

直到最近以前,模拟界仍然用试验电路板和全定制电路来进行设计.与数字门阵列相比,这种方法往往使原型设计周期要长达几周到几个月.这种局面现在开始发生变化,加州San Jose的International Microelectronic Products公司开发的EPAC(电可编程模拟电路)作为取代试验电路板的办法,向模拟电路设计师提供了与数字FPGA相当的设计手段.IMP50E10有丰富的模拟电路资源;只要把用户定义的配置数据存入芯片上的EEPROM配置在存储器里,就可以通过它们去控制优化的模拟开关,进而把芯片上的各种模拟电路互连起来.芯片上的模拟功能包括各种由用户编程决定的功能,如可编程增益的放大     

各国主要厂商集成电路型号命名意义(三)

‘士。里压3 Ingtrumontg,Ine. 德克萨斯铃件公司气美)A姚高级双极电路)SBP(双极微处理器)SMJ(Moe存贮器和徽处理器)SN(标准电路)已NJ(标准电路888B)TAO(CMOS逻辑阵列)TAL(小功率肖特基TTL逻辑 阵列)TAT(STL逻辑阵列)TL(线性电路)TLC(线性CM‘男电路)TIEP(阻抗变换放大器)T工日8(红外源电路)T工PPLA(双极场可编程逻辑阵)T工BPLA(双极可编程逻辑阵)TL 0728 E JG/883B词头编号温度范围封装屏蔽等级 SN 74 5188) 词头温度范围编号封装词头第一字母意义:T(模拟电路) U(数/模电路)词头第二字母愈义:无特殊意义词头第…     

基于FPGA的数字调制信号发生器的设计

以设计数字调制式信号发生器为目的,依据通信系统中模拟和数字调制方式的理论基础,采用现场可编程逻辑阵列技术（FPGA）,给出了一种具有数字调制功能的信号发生器的设计方法。该发生器具有ASK、PSK、FSK功能,各个模块采用VHDL语言设计,然后下栽到EPF10K10LC84—3芯片来完成硬件电路的连接与测试。     

65nm CMOS工艺中的高速多标准FPGA I/O接口设计

设计了一种现场可编程门阵列(FPGA)中使用的高速可配置的输入输出(I/O)接口电路。通过使用电平移位电路、互补自偏置差分放大电路(CSDA)等,该电路实现了包括低压差分信号(LVDS)在内的多种常见的接口协议标准。该电路同时具备可编程配置压摆率和可编程配置输出驱动电流的功能,同时为保证信号完整性,设计了数字阻抗匹配(DCI)模块。芯片使用SMIC 1P10M65nm CMOS工艺流片。测试结果表明,芯片核心电路在1.2V电压下能保证各种协议工作正常,输入输出信号延时、最大输出电流、最高工作速率等与仿真结果吻合,均达到设计指标要求。     

PGA—可编程门阵列电路

一、引言随着电子技术的迅猛发展和微机体系结构的改进,在电路技术上,继门阵列逻辑GAL、可编程逻辑电路PAL之后,最近又出现了速度更快、功耗更小、功能更强、灵活性更好的可编程门阵列PGA(program-mable gate array)。 PGA是一种可编程的新型电路,它介于可编程逻辑电路和门阵列之间,最显著特点是融合了两者的长处,既保留了可编程逻辑所具有的用户现场可编程能力,为设计者提供了在线实时模拟功能,又克服了门阵列的设计费用高和设计周期长的缺点,同时它还有与中低档CMOS门阵列不相上下的速度和集成度,从而大大提高了系统的性能、集成度和可靠性。二、结构与性能 (一)PGA的两种基本类型虽然不同型号的PGA各有其结构特色,但就基本结构来分析,大致可分为两种基本类型: 1.PAL结构的扩展型 PAL结构的特点是“与阵列”可编程,而“或阵列”固定,每个输出的乘积项数     

The Universal Circuit Simulator: A Mixed-Signal Approach to n-Port Network and Impedance Synthesis

A mixed-signal universal architecture able to emulate the behavior of an n-port analog circuit is presented. It exploits second-generation current conveyors as analog input/output blocks and a field programmable gate array circuit as digital processing element. A prototype is also discussed for the specific case of a two-port network synthesis and experimental results in agreement with expected ones are provided.     

Built-In-Self-Testing Techniques for Programmable Capacitor Arrays

This paper presents efficient built-in-self-testing (BIST) techniques for programmable capacitor arrays (PCAs) on field programmable analog array (FPAA) platforms. The proposed BIST circuits consist of switched-capacitor (SC) integrators and analog window comparators. Taking advantage of FPAA programmable resources, the proposed PCA BIST circuits can be implemented with very small hardware overhead. Also the impact of comparator threshold variations as well as other circuit parasitic effects on the efficiency of the proposed testing method is investigated. Effective circuit techniques along with new comparator designs are presented to minimize the adverse effect of comparator threshold variations. Finally, procedures for using the proposed BIST method to systematically test all PCAs on an FPAA platform are described and experimental results are presented.     

A field programmable analog array for CMOS continuous-time OTA-Cfilter applications

A programmable high-frequency operational transconductance amplifier (OTA) is proposed and analyzed. A general configurable analog block (CAB) is presented, which consists of the proposed programmable OTA, programmable capacitor and MOSFET switches. Using the CABs, the universal tunable and field programmable analog array (FPAA) can be constructed, which can realize many signal-processing functions, including filters. A tuning circuit is also discussed. The proposed OTA has been simulated and fabricated in CMOS technology. The results show that the OTA has the transconductance tunable/programmable in a wide range of 700 times and the -3-dB bandwidth larger than 20 MHz. A universal 5×8 CAB array has been fabricated. The chip has also been configured to realize OTA-C 60-kHz and 500-kHz bandpass filters based on ladder simulation and biquad cascade     

A mixed-signal array processor with early vision applications

Many early vision tasks require only 6 to 8 b of precision. For these applications, a special-purpose analog circuit is often a smaller, faster, and lower power solution than a general-purpose digital processor, but the analog chips lack the programmability of digital image processors. This paper presents a programmable mixed-signal array processor which combines the programmability of a digital processor with the small area and low power of an analog circuit. Each processor cell in the array utilizes a digitally programmable analog arithmetic unit with an accuracy of 1.3%. The analog arithmetic unit utilizes a unique circuit that combines a cyclic switched-capacitor analog-to-digital converter (ADC) and digital-to-analog converter (DAC) to perform addition, subtraction, multiplication, and division, Each processor cell, fabricated in a 0.8-μm triple-metal CMOS process, operates at a speed of 0.8 MIPS, consumes 1.8 mW of power at 5 V, and uses 700 μm by 270 μm of silicon area. An array of these processor cells performed an edge detection algorithm and a subpixel resolution algorithm     

基于ispPAC10在增益设置方面的应用

电路设计中要实现对微弱信号放大、高速信号采集、大功率输出等功能,必须采用模拟电路,但长期以来模拟电路的设计一直存在着处理精度低,设计、调试难度大等缺陷。基于此利用Lattice公司推出的在系统可编程模拟电路简称ispPAC进行了放大器的增益设计。它允许设计者使用EDA软件在计算机上设计修改模拟电路,并进行仿真,最后还可以通过编程电缆将设计方案下载到芯片中去。通过开发软件可以调整电路的增益、带宽和阈值等性能指标。在此主要介绍了利用ispPAC10实现模拟信号的增益调整方面的几种技术。     

A novel FPGA architecture supporting wide, shallow memories

This paper investigates an architecture designed to implement wide, shallow memories on a field programmable gate array (FPGA). In the proposed architecture, existing configuration memory normally used to control the connectivity pattern of the FPGA is made user accessible. Typically, not all the switch blocks in an FPGA are used to transport signals. By adding only a modest amount of circuitry, the configuration memory in these unused switch blocks (or unused paths within used switch blocks) can be used to implement wide, shallow buffers and other similar memory structures. The size of FPGA required to implement a benchmark circuit that makes use of the wide, shallow memories, is 20% smaller than a standard memory architecture. In addition, the benchmark circuit is on average 40% faster using the proposed architecture.     

基于FPGA的多功能雷达信号处理板硬件系统设计

为满足实时雷达信号处理需求,设计了一个多功能信号处理板。该处理板以一片高性能的现场可编程门阵列（FPGA）作为信号处理板的主要器件,使用存储器对高速海量数据进行外部存储,为了使计算机和FPGA进行更好的通信,进行了单片机的电路设计,使用模/数（A/D）和数/模（D/A）转换器进行模拟信号和数字信号的相互转变。     

基于CPLD的FPGA从并快速加载方案

提出了基于复杂可编程逻辑器件(CPLD)的现场可编程门阵列(FPGA)从并加载方案,及逻辑代码的实现过程,并给出仿真结果。该方案理论计算结果表明,当加载SPARTAN-6系列最高端的6SLX150T时,采用基于CPLD的从并加载方式,共需要加载时间为1.221 s,完全满足通信产品的快启动要求,具有较高的应用价值。