共查询到20条相似文献,搜索用时 15 毫秒
1.
Two new differential class-AB operational transconductance amplifiers (OTAs) for SC circuits that operate with a supply voltage of less than two transistor threshold voltages are introduced. They make use of a new class-AB pseudodifferential pair to generate signal currents much larger than quiescent currents. Both OTAs have been designed to operate with a supply voltage of V/sub DD/=1.1 V, using a 0.35 /spl mu/m CMOS technology. Simulation results for a load capacitance (C/sub L/) of 1 pF show 15 MHz gain-bandwidth product with a quiescent power consumption of 10 /spl mu/W. 相似文献
2.
R. Kuchibhotla A. Srinivasan J.C. Campbell C. Lei D.G. Deppe Y.S. He B.G. Streetman 《Photonics Technology Letters, IEEE》1991,3(4):354-356
For p-i-n photodiodes and avalanche photodiodes (APDs) in the low-gain regime, there is a performance tradeoff between the transit-time contribution to the bandwidth and the quantum efficiency. A new photodetector structure is demonstrated that alleviates limitations imposed by this tradeoff. This structure utilizes a thin ( approximately=900 AA) depleted absorbing layer to reduce the transit time and achieve avalanche gain at low bias voltage (V/sub b/ approximately=9 V). The external quantum efficiency has been enhanced ( eta /sub e/>49%) by incorporating the structure into a resonant cavity.<> 相似文献
3.
Novel class AB OTA topologies result from the combined use of local common-mode feedback and class AB input stages. They can operate at low supply voltage and feature very low static power consumption, bandwidth enhancement, and very high slew rate. Measurement results of a 0.5 /spl mu/m CMOS prototype show slew rate and unity-gain bandwidth enhancement factors of 180 and 4.5, respectively, compared to a conventional one-stage OTA. 相似文献
4.
This paper presents the results of a study of alternative adder architectures, a full-swing Bipolar Double Pass-Transistor adder, a new full-swing BiNMOS adder, a reduced-swing Bipolar Double Pass-Transistor adder and a reduced-swing Double Pass-Transistor BiNMOS adder, that outperform a standard CMOS adder up to three times in power-efficiency at supply voltages 1.5–3 V. The Bipolar Double Pass-Transistor adder is more power-efficient than a standard CMOS adder even at a fanout of 1. All remaining proposed adders have a lower crossover capacitance with a standard CMOS adder than the previously reported low-voltage adders. Circuits were designed and fabricated in 0.8 μm BiCMOS technology. 相似文献
5.
The letter describes a single stage operational transconductance amplifier (OTA) with cascoded output transistors, designed for micropower switched-capacitor filters. The device features high voltage gain (>90 dB) under capacitive load, large output swing, very low power consumption (5 ?W at 3 V supply voltage for 100 kHz bandwidth with 10 pF load) and reduced circuit area (<0.1 mm2). 相似文献
6.
Winstead C. Nguyen N. Gaudet V.C. Schlegel C. 《IEEE transactions on circuits and systems. I, Regular papers》2006,53(4):829-841
Iterative decoders, including Turbo decoders, provide near-optimal error protection for various communication channels and storage media. CMOS analog implementations of these decoders offer dramatic savings in complexity and power consumption, compared to digital architectures. Conventional CMOS analog decoders must have supply voltage greater than 1 V. A new low-voltage architecture is proposed which reduces the required supply voltage by at least 0.4 V. It is shown that the low-voltage architecture can be used to implement the general sum-product algorithm. The low-voltage analog architecture is then useful for implementing Turbo and low-density parity check decoders. The low-voltage architecture introduces new requirements for signal normalization, which are discussed. Measured results for two fabricated low-voltage analog decoders are also presented. 相似文献
7.
A new BiCMOS buffer circuit, for low-voltage, low-power environment, is presented. The circuit is based on the deep submicron technology and utilizes the parasitic bipolar transistors associated with the CMOS structure. The analysis, simulations and SPICE results confirm the functionality of the circuit and its speed and voltage swing superiority, compared with conventional BiCMOS circuits at low supply voltages 相似文献
8.
A novel dynamic biasing technique that can be used for the design of CMOS class AB current-mode circuits is presented. The approach takes advantage of the switched capacitor (SC) technique and enables extremely low voltage operations. An application of the proposed technique to the design of a basic input stage is given and simulations showing good agreement with the expected results are provided 相似文献
9.
The pass-transistor structure provides a powerful tool for the implementation of binary and multiple-valued logic (MVL). Circuit realisation of any general MVL function using literals, MAX and MIN is easy. However, the resulting circuits have certain limitations. A combination of pass transistors (PT) with switched-capacitor (SC) circuits is shown to provide useful improvements.<> 相似文献
10.
Low-voltage high-speed switched-capacitor (SC) circuit design without using voltage bootstrapper is presented. The basic building block used for low-voltage SC circuit design is the auto-zeroed integrator (AZI), which can work at both low voltage and high sampling frequency. With this method, two low-voltage SC systems were successfully designed and implemented in 1.2-/spl mu/m CMOS technology. The first one is a fully differential SC bandpass biquad working at 1.5 V and 5.0-MHz clock frequency. The measured Q value is 8.0 at the center frequency of 833 kHz. The second one is a fully differential fourth-order bandpass /spl Delta//spl Sigma/ modulator that also works at 1.5 V and 5.0 MHz. Its measured third-order intermodulation is less than -78 dBc due to the low distortion characteristic of AZI. The measured signal-to-noise ratio of the modulator is 61 dB within the narrow band of 25 kHz centered at 1.25 MHz. 相似文献
11.
A symmetric compensation technique that improves the phase response for fully differential folded-cascode operational transconductance amplifiers (OTA) is proposed. Theory and simulated results show that the magnitude response and settling time for symmetrically compensated OTAs are also improved in comparison with those of compensated and typical OTAs 相似文献
12.
A systematic analysis procedure to obtain closed-form expressions for the z-domain transfer functions of SC circuits with finite GB product op-amps is presented. This method allows exact frequential analysis of a general class of SC circuits, without imposing any restriction in the ratio between GB and clock frequencies. 相似文献
13.
An accurate high-frequency switched-current integrator based on low-voltage fully-differential folded-cascode current copiers is presented. A five-pole lowpass ladder filter has been integrated using a 1.2 μm n-well CMOS process without floating precision linear capacitors. Experimental results show an accurate filter response for sampling frequencies up to 5 MHz. Using a nominal 3.3 V power supply, the measured dynamic range is 66 dB and the power dissipation is 10 mW/pole 相似文献
14.
A fully differential bilinear SC integrator, which can be used for SC filter realisations, is proposed. It is parasitic-insensitive and particularly useful in SC filters simulating analogue ladder networks. The design of these filters is different from the commonly used ones, and leads to filters with better sensitivity properties than earlier versions. Realisation of a third-order highpass filter, bilinearly transformed from the continuous-time to the discrete-time domain, is shown as an example. 相似文献
15.
A tutorial of CMOS active resistor circuits will be presented in this paper. The main advantages of the proposed implementations
are the improved linearity, the small area consumption and the improved frequency response. In order to improve their linearity,
improved performances linearization techniques will be proposed, with additional care for compensating the errors introduced
by second-order effects. Design techniques for minimizing the silicon area consumption will be further presented and FGMOS
(Floating Gate MOS) transistors will be used for this purpose. The frequency response of the circuits is very good as a result
of biasing all MOS transistors in the saturation region and of a current-mode operation of an important part of their blocks.
Additionally, small changing in each design allows to obtain negative controllable equivalent resistance circuits. The circuits
are implemented in CMOS technology, SPICE simulations confirming the theoretical estimated results, showing small values of
the linearity error (under 0.15% for the best design) for an extended input range and for a supply voltage equal with ±3 V.
The proposed circuits respond to low-voltage low-power requirements, their design being adapted to the continuous degradation
of the model quality associated with the evolution toward latest nanotechnologies. 相似文献
16.
A novel fully differential class AB OTA in standard CMOS for application with the switched opamp technique is presented. It makes use of a current buffer loop in the input stage as a low voltage current mirror. A new common mode feedback error amplifier, especially suited for the class AB OTA, is also presented. It is based on a differential stage of which the concept is introduced here. A totally new way of switching the amplifiers is introduced as well. Simulations demonstrate the operation of these novel circuits down to a 900 mV supply voltage 相似文献
17.
线性可调全差分OTA的实现 总被引:1,自引:0,他引:1
为了解决CMOS OTA跨导增益不能线性调节的问题,本文采用AB电流镜对NMOS和PMOS差分对管实现的基本OTA进行电流偏置,从而实现了一个跨导增益可以宽幅线性调节的全差分CMOS OTA电路。提出的OTA能够通过调节外部电流Iadj实现线性调节跨导增益,其误差小于2%,外部电流Iadj的调节范围为-40 A~40 A。OTA的差分输入电压摆幅为200mVp-p,输出电流的非线性度小于1.2%。电路的性能通过PSPICE仿真得到了验证。 相似文献
18.
The adaptation of the NAP program to the frequency analysis of SC circuits is presented in the letter. According to this approach the equivalent circuit contains resistances and inductances or capacitances as the representations of the switched or unswitched capacitors in the frequency domain. 相似文献
19.
Noise analysis of high-gain, low-noise column readout circuits for CMOS image sensors 总被引:1,自引:0,他引:1
The temporal read noise on the signal path of a complementary metal-oxide semiconductor image sensor is analyzed to investigate the effectiveness of high-gain column amplifiers in enhancing sensor sensitivity. The signal path examined includes a pixel source follower, a switched-capacitor, noise-cancelling, high-gain amplifier, and a sample-and-hold circuit in each column. It is revealed that the total random readout noise consists of a component due to noise charge sampled and held at the charge summation node of the amplifier and transferred to the output, and a direct noise component sampled at the sample-and-hold stage at the output of the column amplifier. The analysis suggests that the direct noise components can be greatly reduced by increasing the column amplifier gain, indicating that an extremely low-noise readout circuit may be achievable through the development of a double-stage noise-cancelling architecture. 相似文献
20.
The world has migrated to portable applications ranging from smart phones to Lab on a Chip applications. However they come with a new set of challenges for analog IC designers. Low voltage operation, small area and low noise are the critical design criteria for portable devices. This paper presents a gm/ID based design methodology for low voltage current mode circuits using standard CMOS technology. A second generation current conveyor (CCII) and a current feedback operational amplifier (CFA) are designed using the discussed design procedure. Both circuits operate from a single 0.4 V supply. The CCII is used to implement an instrumentation amplifier. Multiple applications are implemented using the CFA. Post layout simulation using TSMC 90 nm and UMC 130 nm technology show that the presented design procedure is an attractive solution for low voltage CMOS current mode circuits. 相似文献