Uncooled multimirror broad-band infrared microbolometers

A new generation of microbolometers were designed, fabricated and tested for the NASA CERES (Clouds and the Earth's Radiant Energy System) instrument to measure the radiation flux at the Earth's surface and the radiant energy now within the atmosphere. These detectors are designed to measure the earth radiances in three spectral channels consisting of a short wave channel of 0.3 to 5 /spl mu/m, a wide-band channel of 0.3 to 100 /spl mu/m and a window channel from 8 to 12 /spl mu/m each housing a 1.5 mm x 1.5 mm microbolometers or alternatively 400 /spl mu/m x 400 mm microbolometers in a 1 /spl times/ 4 array of detectors in each of the three wavelength bands, thus yielding a total of 12 channels. The microbolometers were fabricated by radio frequency (RF) magnetron sputtering at ambient temperature, using polyimide sacrificial layers and standard micromachining techniques. A semiconducting YBaCuO thermometer was employed. A double micromirror structure with multiple resonance cavities was designed to achieve a relatively uniform absorption from 0.3 to 100 /spl mu/m wavelength. Surface micromachining techniques in conjunction with a polyimide sacrificial layer were utilized to create a gap underneath the detector and the Si/sub 3/N/sub 4/ bridge layer. The temperature coefficient of resistance was measured to be -2.8%/K. The voltage responsivities were over 10/sup 3/ V/W, detectivities above 10/sup 8/ cm Hz/sup 1/2//W, noise equivalent power less than 4 /spl times/ 10/sup -10/W/Hz/sup 1/2/ and thermal time constant less than 15 ms.     

A monolithic three-axis micro-g micromachined silicon capacitive accelerometer

A monolithic three-axis micro-g resolution silicon capacitive accelerometer system utilizing a combined surface and bulk micromachining technology is demonstrated. The accelerometer system consists of three individual single-axis accelerometers fabricated in a single substrate using a common fabrication process. All three devices have 475-/spl mu/m-thick silicon proof-mass, large area polysilicon sense/drive electrodes, and small sensing gap (<1.5 /spl mu/m) formed by a2004 sacrificial oxide layer. The fabricated accelerometer is 7/spl times/9 mm/sup 2/ in size, has 100 Hz bandwidth, >/spl sim/5 pF/g measured sensitivity and calculated sub-/spl mu/g//spl radic/Hz mechanical noise floor for all three axes. The total measured noise floor of the hybrid accelerometer assembled with a CMOS interface circuit is 1.60 /spl mu/g//spl radic/Hz (>1.5 kHz) and 1.08 /spl mu/g//spl radic/Hz (>600 Hz) for in-plane and out-of-plane devices, respectively.     

An in-plane high-sensitivity, low-noise micro-g silicon accelerometer with CMOS readout circuitry

A high-sensitivity, low-noise in-plane (lateral) capacitive silicon microaccelerometer utilizing a combined surface and bulk micromachining technology is reported. The accelerometer utilizes a 0.5-mm-thick, 2.4/spl times/1.0 mm/sup 2/ proof-mass and high aspect-ratio vertical polysilicon sensing electrodes fabricated using a trench refill process. The electrodes are separated from the proof-mass by a 1.1-/spl mu/m sensing gap formed using a sacrificial oxide layer. The measured device sensitivity is 5.6 pF/g. A CMOS readout circuit utilizing a switched-capacitor front-end /spl Sigma/-/spl Delta/ modulator operating at 1 MHz with chopper stabilization and correlated double sampling technique, can resolve a capacitance of 10 aF over a dynamic range of 120 dB in a 1 Hz BW. The measured input referred noise floor of the accelerometer-CMOS interface circuit is 1.6/spl mu/g//spl radic/Hz in atmosphere.     

Polymer-based cantilevers with integrated electrodes

An innovative release method of polymer cantilevers with embedded integrated metal electrodes is presented. The fabrication is based on the lithographic patterning of the electrode layout on a wafer surface, covered by two layers of SU-8 polymer: a 10-/spl mu/m-thick photo-structured layer for the cantilever, and a 200-/spl mu/m-thick layer for the chip body. The releasing method is based on dry etching of a 2-/spl mu/m-thick sacrificial polysilicon layer. Devices with complex electrode layout embedded in free-standing 500-/spl mu/m-long and 100-/spl mu/m-wide SU-8 cantilever were fabricated and tested. We have optimized major fabrication steps such as the optimization of the SU-8 chip geometry for reduced residual stress and for enhanced underetching, and by defining multiple metal layers [titanium (Ti), aluminum (Al), bismuth (Bi)] for improved adhesion between metallic electrodes and polymer. The process was validated for a miniature 2/spl times/2 /spl mu/m/sup 2/ Hall-sensor integrated at the apex of a polymer microcantilever for scanning magnetic field sensing. The cantilever has a spring constant of /spl cong/1 N/m and a resonance frequency of /spl cong/17 kHz. Galvanometric characterization of the Hall sensor showed an input/output resistance of 200/spl Omega/, a device sensitivity of 0.05 V/AT and a minimum detectable magnetic flux density of 9 /spl mu/T/Hz/sup 1/2/ at frequencies above 1 kHz at room temperature. Quantitative magnetic field measurements of a microcoil were performed. The generic method allows for a stable integration of electrodes into polymers MEMS and it can readily be used for other types of microsensors where conducting metal electrodes are integrated in cantilevers for advanced scanning probe sensing applications.     

A wafer-scale membrane transfer Process for the fabrication of optical quality, large continuous membranes

This paper describes a new fabrication technique developed for the construction of large area mirror membranes via the transfer of wafer-scale continuous membranes from one substrate to another. Using this technique, wafer-scale silicon mirror membranes have been successfully transferred without the use of sacrificial layers such as adhesives or polymers. This transfer technique has also been applied to the fabrication and transfer of 1 /spl mu/m thick corrugated membrane actuators. These membrane actuators consist of several concentric-ring-type corrugations constructed within a polysilicon membrane. A typical polysilicon actuator membrane with an electrode gap of 1.5 /spl mu/m, fabricated using the wafer-scale transfer technique, shows a vertical deflection of 0.4 /spl mu/m at 55 V. The mirror membranes are constructed from single-crystal silicon, 10 cm in diameter, and have been successfully transferred in their entirety. Using a white-light interferometer, the measured average peak-to-valley surface figure error for the transferred single-crystal silicon mirror membranes is approximately 9 nm as measured over a 1 mm/sup 2/ membrane area. The wafer-scale membrane transfer technique demonstrated in this paper has the following benefits over previously reported transfer techniques: 1) No postassembly release process to remove sacrificial polymers is required. 2) The bonded interface is completely isolated from any acid, etchant, or solvent during the transfer process, ensuring a clean and uniform membrane surface. 3) Our technique is capable of transferring large, continuous membranes onto substrates.     

Design, fabrication, and measurement of high-sensitivity piezoelectric microelectromechanical systems accelerometers

Microelectromechanical systems (MEMS) accelerometers based on piezoelectric lead zirconate titanate (PZT) thick films with trampoline or annular diaphragm structures were designed, fabricated by bulk micromachining, and tested. The designs provide good sensitivity along one axis, with low transverse sensitivity and good temperature stability. The thick PZT films (1.5-7 /spl mu/m) were deposited from an acetylacetonate modified sol-gel solution, using multiple spin coating, pyrolysis, and crystallization steps. The resulting films show good dielectric and piezoelectric properties, with P/sub r/ values >20 /spl mu/C/cm/sup 2/, /spl epsiv//sub r/>800, tan/spl delta/<3%, and |e/sub 31,f/| values >6.5 C/m/sup 2/. The proof mass fabrication, as well as the accelerometer beam definition step, was accomplished via deep reactive ion etching (DRIE) of the Si substrate. Measured sensitivities range from 0.77 to 7.6 pC/g for resonant frequencies ranging from 35.3 to 3.7 kHz. These accelerometers are being incorporated into packages including application specific integration circuit (ASIC) electronics and an RF telemetry system to facilitate wireless monitoring of industrial equipment.     

Fabrication and measured performance of a first-generation microthermoelectric cooler

The measured performance of a column-type microthermoelectric cooler, fabricated using vapor-deposited thermoelectric films and patterned using photolithography processes, is reported. The columns, made of p-type Sb/sub 2/Te/sub 3/ and n-type Bi/sub 2/Te/sub 3/ with an average thickness of 4.5 /spl mu/m, are connected using Cr/Au/Ti/Pt layers at the hot junctions, and Cr/Au layers at the cold junctions. The measured Seebeck coefficient and electrical resistivity of the thermoelectric films, which were deposited with a substrate temperature of 130/spl deg/C, are -74 /spl mu/V/K and 3.6/spl times/10/sup -5/ /spl Omega/-m (n-type, power factor of 0.15 mW/K/sup 2/-m), and 97 /spl mu/V/K and 3.1/spl times/10/sup -5/ /spl Omega/-m (p-type, power factor of 0.30 mW/K/sup 2/-m). The cooling performance of devices with 60 thermoelectric pairs and a column width of 40 /spl mu/m is evaluated under a minimal cooling load (thermobuoyant surface convection and surface radiation). The average cooling achieved is about 1 K. Fabrication challenges include the reduction of the column width, implementation of higher substrate temperatures for optimum thermoelectric properties, and improvements of the top connector patterning and deposition.     

A low-temperature thin-film electroplated metal vacuum package

This paper presents a packaging technology that employs an electroplated nickel film to vacuum seal a MEMS structure at the wafer level. The package is fabricated in a low-temperature (<250/spl deg/C) 3-mask process by electroplating a 40-/spl mu/m-thick nickel film over an 8-/spl mu/m sacrificial photoresist that is removed prior to package sealing. A large fluidic access port enables an 800/spl times/800 /spl mu/m package to be released in less than three hours. MEMS device release is performed after the formation of the first level package. The maximum fabrication temperature of 250/spl deg/C represents the lowest temperature ever reported for thin film packages (previous low /spl sim/400/spl deg/C). Implementation of electrical feedthroughs in this process requires no planarization. Several mechanisms, based upon localized melting and Pb/Sn solder bumping, for sealing low fluidic resistance feedthroughs have been investigated. This package has been fabricated with an integrated Pirani gauge to further characterize the different sealing technologies. These gauges have been used to establish the hermeticity of the different sealing technologies and have measured a sealing pressure of /spl sim/1.5 torr. Short-term (/spl sim/several weeks) reliability data is also presented.     

Encapsulated submillimeter piezoresistive accelerometers

While micromachined accelerometers are widely available and used in various applications, some biomedical applications require extremely small dimensions (相似文献   

Polycrystalline silicon-germanium films for integrated microsystems

Two approaches were demonstrated for fabricating microstructures after completion of CMOS circuits with aluminum metallization. The first approach employed n-type poly-Ge deposited at 400/spl deg/C as a structural material with an SiO/sub 2/ sacrificial layer and an HF release. The CMOS circuits were protected from the release etchant with an amorphous Si layer. Clamped-clamped lateral resonator test structures had quality factors in vacuum as high as /spl sim/30000. Following a 500/spl deg/C, 30 s RTA the poly-Ge stress was 200 MPa (tensile) and the resistivity was 5.3 m/spl Omega/-cm. In the second integration approach, p-type poly-Si/sub 0.35/Ge/sub 0.65/ deposited at 450/spl deg/C was the structural material with poly-Ge as the sacrificial material and H/sub 2/O/sub 2/ as the release etchant. The H/sub 2/O/sub 2/ did not significantly etch the p-type poly-SiGe structural layer and no protection of the underlying CMOS layers was needed. For the first time, the fabrication of LPCVD surface microstructures directly on top of standard electronics was demonstrated, providing dramatic reductions in both MEMS-CMOS interconnect parasitics and device area. A folded flexure lateral resonator had a quality factor in vacuum as high as /spl sim/15000. No stress or dopant-activation anneal was needed, since the in situ boron-doped poly-SiGe was found to have an as-deposited stress of only -10 MPa (compressive) and a resistivity of only 1.8 m/spl Omega/-cm.     

Two-axis single-crystal silicon micromirror arrays

This work presents the design, fabrication, and testing of a two-axis 320 pixel micromirror array. The mirror platform is constructed entirely of single-crystal silicon (SCS) minimizing residual and thermal stresses. The 14-/spl mu/m-thick rectangular (750/spl times/800 /spl mu/m/sup 2/) silicon platform is coated with a 0.1-/spl mu/m-thick metallic (Au) reflector. The mirrors are actuated electrostatically with shaped parallel plate electrodes with 86 /spl mu/m gaps. Large area 320-mirror arrays with fabrication yields of 90% per array have been fabricated using a combination of bulk micromachining of SOI wafers, anodic bonding, deep reactive ion etching, and surface micromachining. Several type of micromirror devices have been fabricated with rectangular and triangular electrodes. Triangular electrode devices displayed stable operation within a (/spl plusmn/5/spl deg/, /spl plusmn/5/spl deg/) (mechanical) angular range with voltage drives as low as 60 V.     

Micromachined jets for liquid impingement cooling of VLSI chips

Two-phase microjet impingement cooling is a potential solution for removing heat from high-power VLSI chips. Arrays of microjets promise to achieve more uniform chip temperatures and very high heat transfer coefficients. This paper presents the design and fabrication of single-jets and multijet arrays with circular orifice diameters ranging from 40 to 76 /spl mu/m, as well as integrated heater and temperature sensor test devices. The performance of the microjet heat sinks is studied using the integrated heater device as well as an industry standard 1 cm/sup 2/ thermal test chip. For single-phase, the silicon temperature distribution data are consistent with a model accounting for silicon conduction and fluid advection using convection coefficients in the range from 0.072 to 4.4 W/cm/sup 2/K. For two-phase, the experimental results show a heat removal of up to 90 W on a 1 cm/sup 2/ heated area using a four-jet array with 76 /spl mu/m diameter orifices at a flowrate of 8 ml/min with a temperature rise of 100/spl deg/C. The data indicate convection coefficients are not significantly different from coefficients for pool boiling, which motivates future work on optimizing flowrates and flow regimes. These microjet heat sinks are intended for eventual integration into a closed-loop electroosmotically pumped cooling system.     

Design and fabrication of a micromachined planar patch-clamp substrate with integrated microfluidics for single-cell measurements

We have designed, fabricated, tested, and integrated microfabricated planar patch-clamp substrates and poly(dimethylsiloxane) (PDMS) microfluidic components. Substrates with cell-patch-site aperture diameters ranging from 300nm to 12 /spl mu/m were produced using standard MEMS-fabrication techniques. The resistance of the cell-patch sites and substrate capacitance were measured using impedance spectroscopy. The resistance of the microfabricated apertures ranged from 200 k/spl Omega/ to 47 M/spl Omega/ for apertures ranging from 12 /spl mu/m to 750 nm, respectively. The substrate capacitance was 17.2 pF per mm/sup 2/ of fluid contact area for substrates with a 2-/spl mu/m-thick layer of silicon dioxide. In addition, the ability of the planar patch-clamp substrates to form high-resistance seals in excess of 1 G/spl Omega/ has been confirmed using Chinese hamster ovary cells (CHO-K1). Testing shows that the microfluidic components are appropriate for driving human embryonic kidney cells (HEK 293) to patch apertures, for trapping cells on patch apertures, and for exchanging the extracellular fluid environment.     

A self-retracting fully compliant bistable micromechanism

A new class of fully compliant bistable mechanisms with the added benefit of integrated self-retraction has been developed (hereafter identified as Self-Retracting Fully compliant Bistable Mechanism or SRFBM). A technique using tensural pivots to manage compressive loading in compliant mechanisms is introduced and implemented in the SRFBM. The elimination of traditional kinematic joints and their associated clearance allows a total displacement between stable positions of 8.5 /spl mu/m, and the mechanism size is less than 300 /spl mu/m square when using 2.0 /spl mu/m minimum line widths. Maximum actuation force is approximately 500 /spl mu/N. The SRFBM's small linear displacement and reasonable actuation force facilitate integration with efficient thermal actuators. Furthermore, fully compliant mechanisms allow greater freedom in fabrication as only one mechanical layer is needed. Systems with on-chip actuation have been fabricated and tested, demonstrating bistability and on-chip actuation, which requires approximately 150 mW. A single fatigue test has been completed, during which the SRFBM endured approximately 2 million duty cycles without failure.     

Thermoelastic damping in fine-grained polysilicon flexural beam resonators

The design and fabrication of polysilicon flexural beam resonators with very high mechanical quality factors (Q) is essential for many MEMS applications. Based on an extension of the well-established theory of thermoelastic damping in homogeneous beams, we present closed-form expressions to estimate an upper bound on the attainable quality factors of polycrystalline beam resonators with thickness (h) much larger than the average grain size (d). Associated with each of these length scales is an independent damping mechanism; we refer to them as Zener and intracrystalline thermoelastic damping, respectively. For representative polysilicon beam resonators (h = 2 /spl mu/m; d = 0.1 /spl mu/m) at 300 K, the predicted critical frequencies for these two mechanisms are /spl sim/7 MHz and /spl sim/14 GHz, respectively. The model is consistent with data from the literature in the sense that the measured values approach, but do not exceed, the calculated thermoelastic limit. From the viewpoint of the maximum attainable Q, our model suggests that single-crystal silicon, rather than fine-grained polysilicon, is the material of choice for the fabrication of flexural beam resonators for applications in the gigahertz frequency range.     

Characterization of selective polysilicon deposition for MEMS resonator tuning

Variations in micromachining processes cause submicron differences in the size of MEMS devices, which leads to frequency scatter in resonators. A new method of compensating for fabrication process variations is to add material to MEMS structures by the selective deposition of polysilicon. It is performed by electrically heating the MEMS in a 25/spl deg/C silane environment to activate the local decomposition of the gas. On a (1.0/spl times/1.5/spl times/100) /spl mu/m/sup 3/, clamped-clamped, polysilicon beam, at a power dissipation of 2.38 mW (peak temperature of 699/spl deg/C), a new layer of polysilicon (up to 1 /spl mu/m thick) was deposited in 10 min. The deposition rate was three times faster than conventional LPCVD rates for polysilicon. When selective polysilicon deposition (SPD) was applied to the frequency tuning of specially-designed, comb-drive resonators, a correlation was found between the change in resonant frequency and the length of the newly deposited material (the hotspot) on the resonator's suspension beams. A second correlation linked the length of the hotspot to the magnitude of the power fluctuation during the deposition trial. The mechanisms for changing resonant frequency by the SPD process include increasing mass and stiffness and altering residual stress. The effects of localized heating are presented. The experiments and simulations in this work yield guidelines for tuning resonators to a target frequency.     

A micromachining process for die-scale pattern transfer in ceramics and its application to bulk piezoelectric actuators

This paper reports on a batch mode planar pattern transfer process for bulk ceramics, glass, and other hard, brittle, nonconductive materials suitable for micromachined transducers and packages. The process is named LEEDUS, as it combines lithography, electroplating, batch mode micro electro-discharge machining (/spl mu/EDM) and batch mode micro ultrasonic machining (/spl mu/USM). An electroplating mold is first created on a silicon or metal wafer using standard lithography, then using the electroplated pattern as an electrode to /spl mu/EDM a hard metal (stainless steel or WC/Co) tool, which is finally used in the /spl mu/USM of the ceramic substrate. A related process (SEDUS) uses serial /spl mu/EDM and omits lithography for rapid prototyping of simple patterns. Feature sizes of 25 /spl mu/m within a 4.5/spl times/4.5 mm/sup 2/ die have been micromachined on glass-mica (Macor) ceramic plates with 34 /spl mu/m depth. The ultrasonic step achieves 18 /spl mu/m/min. machining rate, with a tool wear ratio of less than 6% for the stainless steel microtool. Other process characteristics are also described. As a demonstration, octagonal and circular spiral shaped in-plane actuators were fabricated from bulk lead zirconate titanate (PZT) plate using the LEEDUS/SEDUS process. A device of 20 /spl mu/m thickness and 450 /spl mu/m/spl times/420 /spl mu/m footprint produces a displacement of /spl ap/2/spl mu/m at 40 V.     

Arrays of monocrystalline silicon micromirrors fabricated using CMOS compatible transfer bonding

In this paper, we present CMOS compatible fabrication of monocrystalline silicon micromirror arrays using membrane transfer bonding. To fabricate the micromirrors, a thin monocrystalline silicon device layer is transferred from a standard silicon-on-insulator (SOI) wafer to a target wafer (e.g., a CMOS wafer) using low-temperature adhesive wafer bonding. In this way, very flat, uniform and low-stress micromirror membranes made of monocrystalline silicon can be directly fabricated on top of CMOS circuits. The mirror fabrication does not contain any bond alignment between the wafers, thus, the mirror dimensions and alignment accuracies are only limited by the photolithographic steps. Micromirror arrays with 4/spl times/4 pixels and a pitch size of 16 /spl mu/m/spl times/16 /spl mu/m have been fabricated. The monocrystalline silicon micromirrors are 0.34 /spl mu/m thick and have feature sizes as small as 0.6 /spl mu/m. The distance between the addressing electrodes and the mirror membranes is 0.8 /spl mu/m. Torsional micromirror arrays are used as spatial light modulators, and have potential applications in projection display systems, pattern generators for maskless lithography systems, optical spectroscopy, and optical communication systems. In principle, the membrane transfer bonding technique can be applied for integration of CMOS circuits with any type of transducer that consists of membranes and that benefits from the use of high temperature annealed or monocrystalline materials. These types of devices include thermal infrared detectors, RF-MEMS devices, tuneable vertical cavity surface emitting lasers (VCSEL) and other optical transducers.     

Novel fabrication method for surface micromachined thin single-crystal silicon cantilever beams

This paper describes a novel technique for the fabrication of surface micromachined thin silicon cantilever beams using merged epitaxial lateral overgrowth (MELO) of silicon and chemical-mechanical polishing (CMP). The objective is to demonstrate the feasibility of using this novel technique for the fabrication of arrays of ultrathin, low-stress, single-crystal silicon cantilever beams for use in ultrahigh sensitivity surface-stress or resonant-frequency-based chemical or biological detection schemes. The process flow used in this work is described in detail and the issues that were faced during the fabrication are discussed. Cantilever beams with thickness of 0.3-0.5 /spl mu/m that were 10-25-/spl mu/m wide and 75-130-/spl mu/m long were fabricated. Mechanical characterization of the cantilever beams were performed by measuring their spring constant using the "added mass" method, which also demonstrated the use of these initial structures to detect masses as low as 10-100 pg. Further work is underway to scale the thickness of these beams down to the sub-100-nm regime.     

Electrochemical etching of n-type 6H-SiC without UV illumination

Deep etching of n-type 6H-SiC using a two-step etching process has been studied. First, anodization of 6H-SiC in an HF electrolyte (2 wt.%) without ultraviolet light is applied to form a deep porous layer with the desired dimensions. Then, a thermal oxidation process is used to oxidize this porous layer. The oxidized layer is then removed in a concentrated HF solution. In the experiments, the etching parameters electrolyte concentration and current density are optimized in order to obtain a uniform pore size and hence, a smooth etched surface. After adjusting these parameters, the porous layer formation experiments are carried out at 20/spl deg/C in a 2 wt.% HF electrolyte using a current density of 50 mA/cm/sup 2/. The corresponding porous layer formation rate is about 1.1 /spl mu/m/min. To demonstrate the capabilities of this SiC bulk micromachining process, deep circular cavities are fabricated in n-type 6H-SiC substrates.