Genetic optimization of GRNN for pattern recognition without feature extraction

This paper describes an approach for pattern recognition using genetic algorithm and general regression neural network (GRNN). The designed system can be used for both 3D object recognition from 2D poses of the object and handwritten digit recognition applications. The system does not require any preprocessing and feature extraction stage before the recognition. In GRNN, placement of centers has significant effect on the performance of the network. The centers and widths of the hidden layer neuron basis functions are coded in a chromosome and these two critical parameters are determined by the optimization using genetic algorithms. Experimental results show that the optimized GRNN provides higher recognition ability compared with that of unoptimized GRNN.     

Feedforward Neural Network Implementation in FPGA Using Layer Multiplexing for Effective Resource Utilization

This paper presents a hardware implementation of multilayer feedforward neural networks (NN) using reconfigurable field-programmable gate arrays (FPGAs). Despite improvements in FPGA densities, the numerous multipliers in an NN limit the size of the network that can be implemented using a single FPGA, thus making NN applications not viable commercially. The proposed implementation is aimed at reducing resource requirement, without much compromise on the speed, so that a larger NN can be realized on a single chip at a lower cost. The sequential processing of the layers in an NN has been exploited in this paper to implement large NNs using a method of layer multiplexing. Instead of realizing a complete network, only the single largest layer is implemented. The same layer behaves as different layers with the help of a control block. The control block ensures proper functioning by assigning the appropriate inputs, weights, biases, and excitation function of the layer that is currently being computed. Multilayer networks have been implemented using Xilinx FPGA "XCV400hq240." The concept used is shown to be very effective in reducing resource requirements at the cost of a moderate overhead on speed. This implementation is proposed to make NN applications viable in terms of cost and speed for online applications. An NN-based flux estimator is implemented in FPGA and the results obtained are presented     

基于FPGA的串行多节点数据采集传输系统的应用研究

多节点分布式传感器的数据采集与传输系统有着广泛的应用,其物理层实现主要分为串行及并行两种方式。针对特定的应用场景,选用串行传输的实现方式,设计以FPGA芯片、RS485芯片及AD芯片为核心的硬件平台,使用verilog语言设计FPGA的RTL（Register Transfer Level）逻辑代码,并在Modelsim中完成了功能仿真验证。最终实现了物理层为串行传输、传输层为总线模型的数据采集传输系统,该系统RTL代码设计简单,维护性强,可靠性高,占用芯片资源少,具有一定的工程应用价值。     

基于FPGA的Systolic乘法技术研究

Systolic乘法是一种基于SIMD-MC2模型的矩阵乘算法,无法直接应用在单独的嵌入式系统中,所以提出一种采用FPGA技术实现Systolic乘法的方法。该方法将FPGA的硬件并行特性与巧妙的并行算法结合起来,利用FPGA灵活可编程的特点,在FPGA内部设计了一种基于MC2模型的节点阵列来实现Systolic乘法。实际应用中,可以灵活地修改节点单元的数量和节点的功能来满足不同规模的运算矩阵需求并充分利用FPGA的资源。仿真结果验证了该方法的正确性。实际测试结果表明:该方法具有较快的速度和较高的实时性。     

一种基于FPGA的多路串口控制器设计

针对单片机片上串口资源有限,难以满足一些实际应用需求的问题,提出一种将多个文件数据通过与之相对应的串口同时发送的实现方案.详细描述了设计方案,将多个文件数据经过上位机软件处理,利用FPGA灵活性的优势,读取CompactFlash上的经处理过的数据,并通过相应串口同时发送.实验结果显示,该方案实现简单,每个文件对应的串口发送数据准确,系统运行稳定可靠,解决了单片机串口资源有限的问题,为一些类似应用提供了参考.     

SM4算法门限掩码方案设计与实现

侧信道分析已严重威胁到密码算法应用安全,为提高SM4算法抵御侧信道分析的能力,提出一种门限掩码方案。首先,完成对SM4算法S盒的复合域分解;其次,基于二共享设计门限掩码方案,使用随机数将S盒输入进行二共享拆分,通过复合域运算和S盒门限掩码进行电路重构,并基于S盒复用降低硬件开销;最后进行线性层操作后将两个输出结果通过异或完成去掩码操作。对SM4算法门限掩码方案的FPGA实现仿真结果和安全性测试结果表明,本掩码方案能够有效抵抗CPA攻击,实现面积相对较低。     

Grayscale image formats for edge detection and for its FPGA implementation

The aim of this paper is analysis of image formats used for FPGA implementation of edge detection methods. All cameras used in FPGA applications give Raw RGB output video format, some cameras provide also YUV, YCbCr, RGB565/555 or compressed JPEG formats. If the FPGA circuit has limited number of configurable logic blocks (CLB) the JPEG format seems to be good solution how to increase the size of the processed image. On the other hand, using an image with lossy compression can more or less affect the overall result of image processing. The first goal of this paper is to show whether lossy image compression can affect the quality of edge detection. The results presented in this article show that lossy image compression can impair the efficiency of edge detection by up to six percent. Many researchers have proposed FPGA implementation of some edge detection methods. Usually their first step is RGB to grayscale conversion because they use edge detection methods for grayscale images. The second goal of this paper is to show that a performance of FPGA implementation can be improved if YUV, YCbCr or Raw RGB camera output formats are used instead of RGB format.     

基于FPGA的事件抽取模型与加速器的设计实现

Event extraction technology is important to achieve the quickly extraction of specific information, and it can be widely used in information retrieval, sentiment analysis and other scenarios. Chinese event extraction is more difficult than English event extraction due to the characteristics of Chinese language. Based on the state of the art English event extraction neural network model, a CEE DGCNN (Chinese Event Extraction based on multi layer Dilate Gated Convolutional Neural Network) is proposed, which is suitable for hardware implementation. CEE DGCNN achieves 71.71% F1 score of trigger classification on the ACE2005 Chinese corpus. The accelerator of CEE DGCNN is designed and implemented, and the model size is further optimized by quantization. The accelerator can achieve 97 GOP/s on the Xilinx XCKU115 FPGA, which is 67 times faster than CPU.     

基于MVC模式的医疗事故争议处理系统

Model-View-Controller(MVC)是一种基于Web应用的由多个视图共享一个模型的软件设计模式,能很好实现数据层与表示层的分离,真实反映出管理信息之间的内在关系。为了更好地对医疗事故争议进行有效管理,该文设计了一种基于MVC模式的医疗事故争议系统,该系统应用于绍兴市人民医院,证明其具有良好的实用价值。     

Generic model implementation of deep neural network activation functions using GWO-optimized SCPWL model on FPGA

The implementation of non-linear Activation Functions (AFs) within the Artificial Neural Network (ANN) on the Field Programmable Gate Array (FPGA) is substantial due to the various applications it performs. Accuracy, speed and complexity are the most crucial factors considered in this implementation. Building non-linear AFs in a reconfigurable ANN requires either sequential operations and/or additional complexity. In this paper, a generic model for three types of non-linear AFs (Logistic sigmoid (LogSig), Tan sigmoid (TanSig) and Radial Basis Function (RBF)) has been designed based on Simplicial Canonical Piecewise Linear (SCPWL) model that is optimized using Grey Wolf Optimizer (GWO(Algorithm. The designed model has been achieved by nine segments of the SCPWL model. The input of the AFs is ranging from (−8 to 8). Matlab has been deployed to design, optimize, simulate and validate this model. The maximum errors were 5.2e−3, 15.4e−3 and 7e−3 for LogSig, TanSig and RBF respectively. And, the Mean Square Error (MSE) were 1.81e−6, 1.22e−5 and 1.42e−5 for LogSig, TanSig and RBF respectively. The Matlab/HDL Coder has been used to generate the VHDL codes. The Xilinx Arty A7 (Xc7a35ticsg324-1L) FPGA kit is used to validate the designed model on Vivado Design Suite software. It has been noticed that it takes 581 Look-Up Tables (LUTs), nine DSP slices and a delay of (35.346 ns) to implement the nine SCPWL segments for any linear and non-linear AF. For validation, a complete ANN has been built with three hidden layers, each layer contain with one of the proposed AF models.     

Scalable mpNoC for massively parallel systems – Design and implementation on FPGA

The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device. These parallel systems require a cost-effective yet high-performance interconnection scheme to provide the needed communications between processors. The massively parallel Network on Chip (mpNoC) was proposed to address the demand for parallel irregular communications for massively parallel processing System on Chip (mppSoC). Targeting FPGA-based design, an efficient mpNoC low level RTL implementation is proposed taking into account design constraints. The proposed network is designed as an FPGA based Intellectual Property (IP) able to be configured in different communication modes. It can communicate between processors and also perform parallel I/O data transfer which is clearly a key issue in an SIMD system. The mpNoC RTL implementation presents good performances in terms of area, throughput and power consumption which are important metrics targeting an on chip implementation. mpNoC is a flexible architecture that is suitable for use in FPGA-based parallel systems. This paper introduces the basic mppSoC architecture. It mainly focuses on the mpNoC flexible IP based design and its implementation on FPGA. The integration of mpNoC in mppSoC is also described. Implementation results on a Stratix II FPGA device are given for three data-parallel applications ran on mppSoC. The obtained good performances justify the effectiveness of the proposed parallel network. It is shown that the mpNoC is a lightweight parallel network making it suitable for both small as well as large FPGA-based parallel systems.     

Low power and high-speed FPGA implementation for 4D memristor chaotic system for image encryption

In this paper, we proposed a novel low power and high-speed FPGA implementation of the 4D memristor chaotic system with cubic nonlinearity based on Xilinx System Generator (XSG) model. Firstly, a pseudo-random number generator based on the proposed XSG FPGA implementation of the proposed 4D memristor chaotic system which implemented into Xilinx Spartan-6 X6SLX45 board with 32 fixed-point format. The aim of the FPGA implementation is increasing the frequency of the memristor chaotic random number generators. The FPGA implementation of the memristor chaotic system results show that the new design approach achieves a maximum frequency of 393 MHz and dissipates 117 m watt. The standard fifteen randomization tests are used to measure the quality of the proposed pseudo-random number generator based on the 4D memristor chaotic system and it gives an excellent randomization analysis. Also, the gray image encryption scheme based on the 4D memristor chaotic system has been introduced. The proposed cryptosystem has a large keyspace, very low correlation values, high entropy which is much closer to the ideal entropy value, a high number of pixels change rate and high unified average changing intensity values. The results and security analysis of the proposed encryption scheme demonstrate that the investigated encryption approach can protect high speed and high security against various attack.

     

Speaker identification based on the frame linear predictive coding spectrum technique

In this paper, a frame linear predictive coding spectrum (FLPCS) technique for speaker identification is presented. Traditionally, linear predictive coding (LPC) was applied in many speech recognition applications, nevertheless, the modification of LPC termed FLPCS is proposed in this study for speaker identification. The analysis procedure consists of feature extraction and voice classification. In the stage of feature extraction, the representative characteristics were extracted using the FLPCS technique. Through the approach, the size of the feature vector of a speaker can be reduced within an acceptable recognition rate. In the stage of classification, general regression neural network (GRNN) and Gaussian mixture model (GMM) were applied because of their rapid response and simplicity in implementation. In the experimental investigation, performances of different order FLPCS coefficients which were induced from the LPC spectrum were compared with one another. Further, the capability analysis on GRNN and GMM was also described. The experimental results showed GMM can achieve a better recognition rate with feature extraction using the FLPCS method. It is also suggested the GMM can complete training and identification in a very short time.     

一种实时控制总线及其实现方法

对于小规模通讯系统,目前国内没有形成一个完整的体系结构和通讯规范,因此建立一种完善的实时总线体系结构及其通讯标准就成为一个重要的研究课题;通过分析令牌总线控制思想,给出了以FPGA技术为基础构建一种实时控制总线体系结构的方法;设计了一种适合小型通讯系统的实用型硬件结构,详细介绍了这种结构下数据链路层协议的实现方法;结果证明利用该方法可以构建一种低成本工业测控网,并使该测控网满足了小规模通讯系统实时性要求.     

设计模式在电子商城中的研究与应用

以电子商城的开发为案例探讨了设计模式,并在表示层、业务层、数据访问层三个层次结构上分层使用设计模式。在系统开发中运用了多种重要的核心模式,比如MVC模式、观测者模式、策略模式、代理模式、DAO模式、外观模式、单例模式、简单工厂模式,并给出模式的实现。相对于传统的应用系统,该系统合理使用设计模式使得其结构严密、层次分明,具有更好的可重用性和可维护性。     

A reconfigurable platform for evaluating the performance of QoS networks

Nowadays, high performance System and Local Area Networks (SAN/LAN) have to serve heterogeneous traffic consisting of information flows with different bandwidth and latency requirements. This makes it necessary to provide Quality of Service (QoS) and optimize the design of network components.In this paper we present a hardware tool designed to analyze the performance of QoS networks, under given traffic conditions and server models. In particular, a reprogrammable multimedia traffic Generator/Monitor platform has been built. This permits prototyping the communication system of a high speed LAN/SAN on a single FPGA device. Hence, it can be used at design to produce more efficient devices. To illustrate the applicability of the platform we have used the Simple Multimedia Router (SMMR), an existing proposal to provide QoS.The modular structure of the tool and the fact that it has been implemented on an FPGA using a high level hardware programming language makes it flexible, scalable and easy to reconfigure. Besides, the architecture and implementation can be adapted to be used in more recent QoS NoC environments.     

Remote dynamic partial reconfiguration: A threat to Internet-of-Things and embedded security applications

The advent of the Internet of Things has motivated the use of Field Programmable Gate Array (FPGA) devices with Dynamic Partial Reconfiguration (DPR) capabilities for dynamic non-invasive modifications to circuits implemented on the FPGA. In particular, the ability to perform DPR over the network is essential in the context of a growing number of Internet of Things (IoT)-based and embedded security applications. However, the use of remote DPR brings with it a number of security threats that could lead to potentially catastrophic consequences in practical scenarios. In this paper, we demonstrate four examples where the remote DPR capability of the FPGA may be exploited by an adversary to launch Hardware Trojan Horse (HTH) attacks on commonly used security applications. We substantiate the threat by demonstrating remotely-launched attacks on Xilinx FPGA-based hardware implementations of a cryptographic algorithm, a true random number generator, and two processor based security applications - namely, a software implementation of a cryptographic algorithm and a cash dispensing scheme. The attacks are launched by on-the-fly transfer of malicious FPGA configuration bitstreams over an Ethernet connection to perform DPR and leak sensitive information. Finally, we comment on plausible countermeasures to prevent such attacks.     

FPGA implementation of highly scalable AES algorithm using modified mix column with gate replacement technique for security application in TCP/IP

Field Programmable Gate Arrays (FPGA) offers a faster, increasingly adjustable arrangement. Earlier Data Encryption Standard (DES) algorithms have been developed, however it could not keep up with advancement in a technology and it is no longer appropriate for security. With this motivation, this work developed an efficient FPGA implementation of Advanced Encryption Standard (AES) targets to investigate a huge number of security processes followed in the TCP/IP protocol suite and to suggest a novel new architecture for the existing version. The first contribution of the studies turned into to provide the safety for packages of the utility layer protocols. The AES cryptographic encryption, decryption and key management set of rules to for the safety of transmission control protocol/internet protocol (TCP/IP) protocol suite turned into carried out. AES is one of the maximum famous cryptographic algorithms used for records safety. The cost and consumption of power in the AES can be decreased substantially by way of optimizing the structure of AES. This research article projects an implementation based on modification in Mix column in AES techniques which gives a compact structure with efficient mix column Boolean expression the usage of resource sharing architecture and gate replacement method. The ON-chip power utilization and area overhead of the proposed hardware implementation outperforms the preceding work performed in this area. The proposed architecture have been carried out on the most latest virtex 6 lower power Field programmable gate array (FPGA), whereas overhead and on-chip utilization of power are compared with the previous works and it is proved that proposed method has lower area utilization and ON-Chip utilization of power.     

多位平面并行的EZW零树编码电路研究

零树编码技术已经被MPEG-4国际标准所采用，多位平面并行的EZW零树编码电路方案为实时应用中的零树编码提供了一条高效的技术途径，它具体包括一种简单、巧妙的预处理器，对不同位平面之间存在的关联加以分离，保证多位平面并行零树编码的实现。另外，在每个位平面中，此方案利用符号分配与跳过处理的执行特点，将编码操作分解成两步，分别结合到两次正、反向的树深度扫描之中，避免了不规则的扫描、处理。此设计在FPGA电路上进行了验证，它可以实时编码CIF格式视频图像，需要2500个左右的逻辑单元。