L波段高增益低噪声放大器的设计

低噪声放大器(LNA)是接收机的重要组成部分,它的性能的好坏直接影响着接收机的灵敏度,增益和噪声系数是LNA的两个最重要的指标,所设计的低噪声放大器中心频段为1650MHz时,工作带宽为200M,噪声系数为1.3dB,增益大于35dB,带内平坦度小于±0.5dB,达到应用要求。     

宽带光纤拉曼放大器的增益平坦化实验研究

本文采用波长为 1 455nm的大功率光纤拉曼激光器(FRL)作为泵浦源,啁啾布拉格光纤光栅作为增益平坦滤波器,用两种不同的光源组合作为信号源(宽带ASE光源) 波分复用模拟器(WDM-emulator)以及四通道外腔可谐调式激光器(ECL) 滤波器型波分复用器(FWDM))对光纤拉曼放大器的增益平坦化特性进行实验研究,获得了平坦增益带宽为55nm(1 519～1 574nm),平均开关增益大小为15.2dB,增益不平坦度为±0.8dBd的宽带光纤拉曼放大器.通过实验研究表明,该方案为带宽低于60nm的光纤拉曼放大器的增益平坦化设计提供了一种新的选择.     

高精度射频宽带放大器设计方法研究

本文重点论述了高精度射频宽频带放大器的设计原理和方法.包括射频宽带放大器的电路设计方案分析;射频宽带放大器的详细设计;射频宽带放大器的输入阻抗;以及降低噪声;提高增益等性能的方法设计等.采用高精度、高阻抗的集成运算放大器AD8009射频宽带放大器电路,进行了射频宽带放大器电路设计制作实验调试,对宽带放大器带宽、增益提高方法进行了详细的实验研究.通过大量的实验测试证明:本文所论述的射频宽带放大器设计方法合理正确,放大器的性能指标达到输出阻抗R≤50Ω,输入阻抗R≤50Ω;准确度优于0.1%;电压增益大于20dB,输出电压≥200mV.输出信号波形无明显失真;放大器的下限截止频率≤0.3 MHz,上限截至频率≥50 MHz,并在1 MHz~20 MHz频带内增益起伏≤1dB.     

2GHz宽阻带低噪声放大器的协同设计

去除了低噪声放大器(LNA)与带通滤波器之间的50 Ω的匹配界面.用带通滤波器代替低噪声放大器的输出匹配网络,将二者进行协同设计.采用的滤波器具有宽阻带.能够直接滤除二次谐波.仿真结果表明,协同设计后,LNA的稳定性得到了有效的改善,在整个频段内达到了绝对稳定;在中心频率2 GHz处,增益为14.593 dB,噪声系数为2.668 dB;谐波抑制效果也很明显,二次谐波处S21为-71.140 dB.     

双程泵浦分立式拉曼放大特性的研究

采用后向泵浦的方案,对新型双程放大分立式光纤拉曼放大器(D-DFRA)的增益特性进行了理论计算,并在双程泵浦放大条件下对增益和噪声特性及受激布里渊散射(SBS)效应进行了实验测量,计算与测量结果较好符合.本文的研究表明:对分立式拉曼放大器通过反射机制实现泵浦光的双程泵浦,可在泵浦功率不变和保持较好噪声特性的同时,大大提升放大器的增益和功率转换效率.增益的提升上限取决于系统受激布里渊散射的阈值,在双程泵浦下增益的上限可得到提高.     

毫米波单片集成低噪声放大器电路

基于0.25μm PHEMT(赝配高电子迁移率场效应晶体管)工艺,给出了一款毫米波MMIC(单片集成电路)低噪声放大器.放大器设计中采用了三级级联增加栅宽的电路结构,通过前级源极反馈电感的恰当选取获得了较好的输入驻波比和较低的噪声;采用直流偏置上加电阻电容网络,用来消除低频增益和振荡;三级电路通过电阻共用一组正负电源,使用方便,且电路性能较好:输入输出驻波比小于2.0,增益大于15dB,噪声系数小于3.0dB.1dB压缩点输出功率大于15dBm,芯片尺寸为1mm×2mm×0.1mm.这是国内报导的面积最小、性能最好的毫米波低噪声放大器.     

BD031 MEMS信号处理电路的研制及测试

本文报道了一个为电容式微加速度计传感器信号处理而设计的全集成化的BD031 CMOS MEM信号处理电路.电路设计采用了对信号的差分电容采样方式和过采样技术、前置采样放大器高增益和低噪声设计措施、可调节选通带宽的的低通滤波器及为提高电容噪声性能的带有虚开关结构的开关电容滤波器设计技术、可微调节增益(常规情况下恒定增益为2)的输出缓冲放大器、可调节振荡频率(正常情况下为800KHz)的本地CMOS时钟产生振荡器及为上述模拟电路提供基准电压和基准电流的基准电压源等设计技术、以及可以进行输入失调调节和对差分电容变化量△C的自测试电路.电路使用单一5伏电源,采用1.2微米、双多晶硅、双铝、N-阱CMOS工艺加工,芯片面积为2.82×3.61平方毫米.芯片性能测试表明其差分小电容变化量△C传感范围达到0.06pF-5pF、带宽为300Hz-5KHz.     

分布式光纤拉曼放大器研制的进展

对分布式光纤拉曼放大器研究的历史、基本原理、优化设计以及现状和进展进行了讨论.对S波段的色散补偿型分布式光纤拉曼放大器以及采用光纤拉曼激光器作为抽运源,在前向抽运和后向抽运条件下,对5kmDCF-50kmG652光纤色散补偿型分布式光纤拉曼放大器增益光谱和噪声谱进行了研究.设计和制作了光纤光栅的增益平坦滤波器,取得了较好的增益平坦效果.FRA-1型分布式光纤拉曼放大器在校园网进行了应用试验,取得了较好的试验效果.     

GSM-R光纤直放站低噪声放大器模块的设计

对满足铁路专用数字移动通信系统(GSM-R)标准的光纤直放站低噪声放大器模块进行了设计、制造和测试.放大器模块由四级放大电路构成,可提供高的增益和线性度.输入级采用双平衡放大结构,不仅能改善放大器级间匹配性,而且由于具有冗余备份功能,可提高模块的可靠性.采用数模混合自动增益控制技术保证低噪声放大器的输出功率稳定和高动态范围.测试结果表明,该模块最大增益达到60dB,增益调节范围大于30dB,互调衰减小于-60dBc,噪声系数小于1.0dB,体现了优异的线性度和噪声性能.该模块完全达到GSM-R高铁直放站的设计要求,目前已通过南京泰通科技的实际应用测试,并开始试应用于铁路系统中.     

BD031 MEMS信号处理电路的研制及测试

本文报道了一个为电容式微加速度计传感器信号处理而设计的全集成化的BD031 CMOS MEM信号处理电路.电路设计采用了对信号的差分电容采样方式和过采样技术、前置采样放大器高增益和低噪声设计措施、可调节选通带宽的的低通滤波器及为提高电容噪声性能的带有虚开关结构的开关电容滤波器设计技术、可微调节增益(常规情况下恒定增益为2)的输出缓冲放大器、可调节振荡频率(正常情况下为800KHz)的本地CMOS时钟产生振荡器及为上述模拟电路提供基准电压和基准电流的基准电压源等设计技术、以及可以进行输入失调调节和对差分电容变化量△C的自测试电路.电路使用单一5伏电源,采用1.2微米、双多晶硅、双铝、N-阱CMOS工艺加工,芯片面积为2.82×3.61平方毫米.芯片性能测试表明其差分小电容变化量△C传感范围达到0.06pF-5pF、带宽为300Hz-5KHz.     

A High Quality Controlled Current Source

A technique for realizing a high-quality controlled current source is described. A monolithic operational amplifier is used as the main building block, and a modified current mirror is used to recover the signal current from the power supply leads of the amplifier. The proposed mirror exhibits low input resistance, which reduces errors due to the noninfinite power-supply rejection characteristics of the amplifier, and a current-splitting network allows the realization of output impedances in the range of tens of megohms using standard components. The entire circuit operates in a class-AB mode for high drive capability with low values of quiescent current. A simple application is included to show that a voltage amplifier can readily be constructed which exhibits a 3-dB gain-bandwidth product forty times larger than the gain-bandwidth product of the operational amplifier used. Detailed experimental results are included to verify predicted frequency response and gain characteristics.     

Design methodology of Miller frequency compensation with current buffer/amplifier

Current buffers/amplifiers are used in series to the Miller compensation capacitor with the aim of eliminating the positive zero introduced by the forward path. They are increasingly adopted because of their low-voltage features, high-speed performance and, recently, for their suitability to be used with large capacitive loads (when a current gain is introduced). The authors propose a novel and simple design approach for the frequency compensation of a two-stage amplifier exploiting a current buffer/amplifier. The procedure has been profitably applied to a class-AB two-stage CMOS operational transconductance amplifier, having a 100 pF load. In particular, three compensation networks were designed using a 1.3 pF, 0.6 pF and 250 fF compensation capacitor alternatively. Moreover, the adopted compensation topology provides an improvement in terms of power supply rejection ratio, which was also analytically demonstrated. Simulations that are in very good agreement with theoretical results are also given.     

A High Gain,Noise Cancelling 3.1-10.6 GHz CMOS LNA for UWB Application

With the rapid development of ultra-wideband communications, the design requirements of CMOS radio frequency integrated circuits have become increasingly high. Ultra-wideband (UWB) low noise amplifiers are a key component of the receiver front end. The paper designs a high power gain (S₂₁) and low noise figure (NF) common gate (CG) CMOS UWB low noise amplifier (LNA) with an operating frequency range between 3.1 GHz and 10.6 GHz. The circuit is designed by TSMC 0.13 μm RF CMOS technology. In order to achieve high gain and flat gain as well as low noise figure, the circuit uses many technologies. To improve the input impedance matching at low frequencies, the circuit uses the proposed T-match input network. To decrease the total dissipation, the circuit employs current reused technique. The circuit uses he noise cancelling technique to decreases the NF. The simulation results show a flat S₂₁>20.81 dB, the reverse isolation (S₁₂) less than -48.929 dB, NF less than 2.617 dB, the minimum noise figure (NF_min)=1.721 dB, the input return loss (S11) and output return loss (S₂₂) are both less than -14.933 dB over the frequency range of 3.1 GHz to 10.6 GHz. The proposed UWB LNA consumes 1.548 mW without buffer from a 1.2 V power supply.     

Development of Low Power Cryogenic Readout Integrated Circuits Using Fully-Depleted-Silicon-on-Insulator CMOS Technology for Far-Infrared Image Sensors

We are developing low power cryogenic readout integrated circuits (ROICs) for large format far-infrared image sensors using fully-depleted-silicon-on-insulator (FD-SOI) CMOS technology. We have evaluated the characteristics of MOS FETs fabricated by the FD-SOI CMOS technology and have found that both p-ch and n-ch FETs show good static performance below the liquid helium temperature, where n-ch FETs fabricated by conventional bulk-CMOS technology usually suffer from anomalous behaviors such as kink and hysteresis. We have also designed and fabricated an operational amplifier (OP-AMP) and have successfully demonstrated that the OP-AMP works at the liquid helium temperature with an open loop gain of 7000 and a power consumption of 1.3 μW. The noise is dominated by mainly 1/f and has a value of at?1?Hz.     

Current-Mode Capacitive Sensor Interface Circuit With Single-Ended to Differential Output Capability

This paper presents a current-mode interface circuit for capacitive sensors, with the main features being its ability to produce a differential output from a single-ended sensor (using a fixed reference capacitor) and its simplicity in realization. These advantages make it a potential candidate for applications where differential sensors are not available and where a simple design is required. The principle is, however, easily applicable to differential sensors as well. The interface concept can be realized in different ways; however, to present a proof of concept on silicon, a prototype has been fabricated and tested in a commercially available 0.8-mum CMOS process. The circuit has been designed using common analog building blocks such as a fully differential operational transconductance amplifier (OTA), a high-output-resistance wide-swing current source, and a single clock phase. The estimated linearity error was 0.2% relative to full-scale swing with a simple two-point calibration. The circuit consumes 145 muA from a 5-V power supply.     

Design of Chopper-Stabilized Amplifiers With Reduced Offset for Sensor Applications

Offset error mechanisms in a single-ended chopper-stabilized amplifier are investigated. The error models and their prediction equations are given. This work also presents a new analytical approach for estimating the switch error in a four-transistor chopping network. A new resistance balancing circuit technique is also introduced, which permits further reduction of dc offsets in conventional chopping operational amplifier (op-amp) or chopping differential difference amplifier (DDA). The HSPICE simulation results have validated the proposed technique and identified dominant error sources using Level-49 BSIM3 model in a standard 0.6-$mu{hbox{m}}$ CMOS technology. Applying the technique to the fabricated DDA chips at a noninverting gain of ten and a single 3-V supply, the measured results have shown that 40% of the ten samples display no more than 3- and 5-$mu{hbox{V}}$ offsets at the chopping frequency of 10 and 64 kHz, respectively. The proposed technique offers a potential advantage for improving the yield of low-offset amplifiers in sensory systems.      

Diagnostics of Integrated Operational Amplifiers Mounted on Circuit Boards

Methods of estimating the soundness of operational amplifier microcircuits mounted on the circuit boards of radioelectronic apparatus are described. It is shown that it is possible to measure the gain independently of the components connected on the board with the amplifier.     

CMOS chopper amplifier for chemical sensor

A highly sensitive CMOS chopper amplifier for an oxygen probe is described. It is integrated in a 2-μm double-poly p-well CMOS process. The chip uses only a single 5-V voltage source, and no external components are needed. It is realized by using the current mode chopper technique to overcome the low frequency noise and drift problems. The clock feedthrough generated by the chopper circuit is reduced by using the switched-capacitor-filter technique. The switched-capacitor technique is also used to implement the function of demodulation. The simulated current is converted into an output voltage with a slope of approximately 100 mV/nA. The current signal from 0.2 to 8 nA can be measured with a nonlinearity of 3.5%. Experimental results are given showing the performance of this amplifier     

采用预充开关运放的低功耗12位40MS/s流水线模数转换器

设计了一个采用新型预充快速开启开关运放的低功耗12位40MS/s流水线模数转换器(ADC)。该转换器通过采用新型预充开关运放技术、采样保持电路消去结构、动态比较器和优化采样电容,大大降低了电路的功耗。电路设计采用1.8V 1P6M 0.18μmCMOS工艺,仿真结果表明,在40MS/s采样速率下,输入信号为19MHz时,无杂散动态范围(SFDR)为90.15dB,信噪失真比(SNDR)为72.98dB,功耗为27.9mW。     

A Delay Generation Technique for Narrow Time Interval Measurement

A new architecture for the on-chip measurement of short-time intervals is proposed in this paper. The measurement method is similar to a typical low-voltage measurement setup where the input signals are first amplified and then measured to relax the dynamic range of the succeeding analog-to-digital converter. In the proposed method, narrow time intervals are first amplified by a time amplifier (TAMP) and then measured by a time-to-digital converter. A delay-locked-loop (DLL) circuit is utilized to design a feedback time amplifier in which the gain is readily programmed by input data to any integer value within a range specified by the number of delay cells in the DLL. The TAMP's gain remains rather unchanged under process and temperature variations due to the inherent negative feedback of the DLL system. The circuit is implemented using complementary metal--oxide semiconductor (CMOS) 0.18- $muhbox{m}$ technology occupying less than 0.63 $hbox{mm}^{2}$ of the silicon area. The simulation results show that the proposed scheme can successfully be employed to measure time intervals in the range of a few tens of picoseconds with acceptable accuracy.