Efficient amplification using the /sup 4/F/sub 3/2//spl rarr//sup 4/I/sub 9/2/ transition in Nd-doped silica fiber

Amplification characteristics of the three-level /sup 4/F/sub 3/2//spl rarr//sup 4/I/sub 9/2/ transition in Nd-doped silica glass fiber are investigated under strong signal saturation and high pump power (150 mW). Aluminum codoped Nd-silica fibers exhibit strong superfluorescent behavior in the four-level /sup 4/F/sub 3/2//spl rarr//sup 4/I/sub 11/2/ transition which limits the optical conversion efficiency into the three-level transition. Ge-doped silica fibers do not exhibit this limitation and can efficiently amplify in the three-level transition with current laser-diode pump technology.     

A novel high-/spl kappa/ SONOS memory using TaN/Al/sub 2/O/sub 3//Ta/sub 2/O/sub 5//HfO/sub 2//Si structure for fast speed and long retention operation

A novel high-/spl kappa/ silicon-oxide-nitride-oxide-silicon (SONOS)-type memory using TaN/Al/sub 2/O/sub 3//Ta/sub 2/O/sub 5//HfO/sub 2//Si (MATHS) structure is reported for the first time. Such MATHS devices can keep the advantages of our previously reported TaN/HfO/sub 2//Ta/sub 2/O/sub 5//HfO/sub 2//Si device structure to obtain a better tradeoff between long retention and fast programming as compared to traditional SONOS devices. While at the same time by replacing hafnium oxide (HfO/sub 2/) with aluminum oxide (Al/sub 2/O/sub 3/) for the top blocking layer, better blocking efficiency can be achieved due to Al/sub 2/O/sub 3/'s much larger barrier height, resulting in greatly improved memory window and faster programming. The fabricated devices exhibit a fast program and erase speed, excellent ten-year retention and superior endurance up to 10/sup 5/ stress cycles at a tunnel oxide of only 9.5 /spl Aring/ equivalent oxide thickness.     

TeO/sub 2/-based glasses containing Nb/sub 2/O/sub 5/, TiO/sub 2/, and WO/sub 3/ for discrete Raman fiber amplification

We describe a highly stable glass family based on the combination of TeO/sub 2/ with heavy metal-oxides of Nb, Ti, W. We show that these glasses have large Raman gain, a broad Raman spectrum, and large negative dispersion. They are, thus, potentially useful in a variety of specialty fiber applications, such as discrete Raman amplification.     

Metal-insulator-metal RF bypass capacitor using niobium oxide (Nb/sub 2/O/sub 5/) with HfO/sub 2//Al/sub 2/O/sub 3/ barriers

A high capacitance density (C/sub density/) metal-insulator-metal (MIM) capacitor with niobium pentoxide (Nb/sub 2/O/sub 5/) whose k value is higher than 40, is developed for integrated RF bypass or decoupling capacitor application. Nb/sub 2/O/sub 5/ MIM with HfO/sub 2//Al/sub 2/O/sub 3/ barriers delivers a high C/sub density/ of >17 fF//spl mu/m/sup 2/ with excellent RF properties, while maintaining comparable leakage current and reliability properties with other high-k dielectrics. The capacitance from the dielectric is shown to be stable up to 20 GHz, and resonant frequency of 4.2 GHz and Q of 50 (at 1 GHz) is demonstrated when the capacitor is integrated using Cu-BEOL process.     

A novel strained Si/sub 0.7/Ge/sub 0.3/ surface-channel pMOSFET with an ALD TiN/Al/sub 2/O/sub 3//HfAlO/sub x//Al/sub 2/O/sub 3/ gate stack

Proof-of-concept pMOSFETs with a strained-Si/sub 0.7/Ge/sub 0.3/ surface-channel deposited by selective epitaxy and a TiN/Al/sub 2/O/sub 3//HfAlO/sub x//Al/sub 2/O/sub 3/ gate stack grown by atomic layer chemical vapor deposition (ALD) techniques were fabricated. The Si/sub 0.7/Ge/sub 0.3/ pMOSFETs exhibited more than 30% higher current drive and peak transconductance than reference Si pMOSFETs with the same gate stack. The effective mobility for the Si reference coincided with the universal hole mobility curve for Si. The presence of a relatively low density of interface states, determined as 3.3 /spl times/ 10/sup 11/ cm/sup -2/ eV/sup -1/, yielded a subthreshold slope of 75 mV/dec. for the Si reference. For the Si/sub 0.7/Ge/sub 0.3/ pMOSFETs, these values were 1.6 /spl times/ 10/sup 12/ cm/sup -2/ eV/sup -1/ and 110 mV/dec., respectively.     

Characteristics of Al/sub 2/O/sub 3//AllnN /GaN MOSHEMT

InAlN/GaN is a new heterostructure system for HEMTs with thin barrier layers and high channel current densities well above 1 A/mm. To improve the leakage characteristics of such thin-barrier devices, AlInN/GaN MOSHEMT devices with a 11 nm InAlN barrier and an additional 5 nm Al₂O₃ barrier (deposited by ALD) were fabricated and evaluated. Gate leakage in reverse direction could be reduced by one order of magnitude and the forward gate voltage swing increased to 4 V without gate breakdown. Compared to HEMT devices of similar geometry, no degradation of the current gain cutoff frequency was observed. The results showed that InAlN/GaN FETs with high channel current densities can be realised with low gate leakage characteristics and high structural aspect ratio by insertion of a thin Al₂O ₃ gate dielectric layer     

Characteristics of MOSFET Prepared on Si/MgO /spl dot/ Al/sub 2/O/sub 3//SiO/sub 2//Si Structure

A new silicon on insulator (SOI) wafer with epitaxial-Si/ epitaxial-MgO/spl dot/Al/sub 2/O/sub 3/ (0.1 /spl mu/m)/SiO/sub 2/(0.5 /spl mu/m)/     

High-performance Pt/SrBi/sub 2/Ta/sub 2/O/sub 9//HfO/sub 2//Si structure for nondestructive readout memory

Metal-ferroelectric-insulator-semiconductor (MFIS) capacitors with 390-nm-thick SrBi/sub 2/Ta/sub 2/O/sub 9/ (SBT) ferroelectric film and 8-nm-thick hafnium oxide (HfO/sub 2/) layer on silicon substrate have been fabricated and characterized. It is demonstrated for the first time that the MFIS stack exhibits a large memory window of around 1.08 V at an operation voltage of 3.5 V. Moreover, the MFIS memory structure suffers only 18% degradation in the memory window after 10/sup 9/ switching cycles. The excellent performance is attributed to the formation of well-crystallized SBT perovskite thin film on top of the HfO/sub 2/ buffer layer, as evidenced by the distinctive sharp peaks in X-ray diffraction (XRD) spectra. In addition to its relatively high /spl kappa/ value, HfO/sub 2/ also serves as a good seed layer for SBT crystallization, making the proposed Pt/SrBi/sub 2/Ta/sub 2/O/sub 9//HfO/sub 2//Si structure ideally suitable for low-voltage and high-performance ferroelectric memories.     

Characteristics of Al/sub 2/O/sub 3//TiO/sub 2/ nanolaminates and AlTiO thin films on Si

This letter reports a metal-insulator-semiconductor structure based on Al/sub 2/O/sub 3//TiO/sub 2/ nanolaminates and AlTiO films evaporated on an unheated p-Si substrate. The structure exhibits a low hysteresis in the capacitance-voltage characteristics, a larger dielectric constant leading to a quantum mechanically corrected effective oxide thickness of 1.35-2.1 nm, good stability of the electrical characteristics to thermal processes, a large breakdown electric field of 7.5 MV/cm, and a leakage current density below 5/spl times/10/sup -7/ A/cm/sup 2/ at an electric field of 2 MV/cm.     

Low-frequency noise in submicrometer MOSFETs with HfO/sub 2/, HfO/sub 2//Al/sub 2/O/sub 3/ and HfAlO/sub x/ gate stacks

Low-frequency noise measurements were performed on p- and n-channel MOSFETs with HfO/sub 2/, HfAlO/sub x/ and HfO/sub 2//Al/sub 2/O/sub 3/ as the gate dielectric materials. The gate length varied from 0.135 to 0.36 /spl mu/m with 10.02 /spl mu/m gate width. The equivalent oxide thicknesses were: HfO/sub 2/ 23 /spl Aring/, HfAlO/sub x/ 28.5 /spl Aring/ and HfO/sub 2//Al/sub 2/O/sub 3/ 33 /spl Aring/. In addition to the core structures with only about 10 /spl Aring/ of oxide between the high-K dielectric and silicon substrate, there were "double-gate oxide" structures where an interfacial oxide layer of 40 /spl Aring/ was grown between the high-K dielectric and Si. DC analysis showed low gate leakage currents in the order of 10/sup -12/ A(2-5 /spl times/ 10/sup -5/ A/cm/sup 2/) for the devices and, in general, yielded higher threshold voltages and lower mobility values when compared to the corresponding SiO/sub 2/ devices. The unified number-mobility fluctuation model was used to account for the observed 1/f noise and to extract the oxide trap density, which ranged from 1.8 /spl times/ 10/sup 17/ cm/sup -3/ eV/sup -1/ to 1, 3 /spl times/ 10/sup 19/ cm/sup -3/ eV/sup -1/ somewhat higher compared to conventional SiO/sub 2/ MOSFETs with the similar device dimensions. There was no evidence of single electron switching events or random telegraph signals. The aim of this paper is to present a general discussion on low-frequency noise characteristics of the three different high-K/gate stacks, relative comparison among them and to the Si-SiO/sub 2/ system.     

Low-frequency noise in submicrometer MOSFETs with HfO/sub 2/, HfO/sub 2//Al/sub 2/O/sub 3/ and HfAlO/sub x/ gate stacks

Low-frequency noise measurements were performed on p- and n-channel MOSFETs with HfO/sub 2/, HfAlO/sub x/ and HfO/sub 2//Al/sub 2/O/sub 3/ as the gate dielectric materials. The gate length varied from 0.135 to 0.36 /spl mu/m with 10.02 /spl mu/m gate width. The equivalent oxide thicknesses were: HfO/sub 2/ 23 /spl Aring/, HfAlO/sub x/ 28.5 /spl Aring/ and HfO/sub 2//Al/sub 2/O/sub 3/ 33 /spl Aring/. In addition to the core structures with only about 10 /spl Aring/ of oxide between the high-/spl kappa/ dielectric and silicon substrate, there were "double-gate oxide" structures where an interfacial oxide layer of 40 /spl Aring/ was grown between the high-/spl kappa/ dielectric and Si. DC analysis showed low gate leakage currents in the order of 10/sup -12/A(2-5/spl times/10/sup -5/ A/cm/sup 2/) for the devices and, in general, yielded higher threshold voltages and lower mobility values when compared to the corresponding SiO/sub 2/ devices. The unified number-mobility fluctuation model was used to account for the observed 1/f noise and to extract the oxide trap density, which ranged from 1.8/spl times/10/sup 17/ cm/sup -3/eV/sup -1/ to 1.3/spl times/10/sup 19/ cm/sup -3/eV/sup -1/, somewhat higher compared to conventional SiO/sub 2/ MOSFETs with the similar device dimensions. There was no evidence of single electron switching events or random telegraph signals. The aim of this paper is to present a general discussion on low-frequency noise characteristics of the three different high-/spl kappa//gate stacks, relative comparison among them and to the Si--SiO/sub 2/ system.     

Ultrawide-band La-codoped Bi/sub 2/O/sub 3/-based EDFA for L-band DWDM systems

The demonstration of a 253-cm-long lanthanum-codoped Bi/sub 2/O/sub 3/-based erbium-doped fiber which provides gain of greater than 20 dB and noise figure less than 6.7 dB to 142 dense wavelength-division-multiplexing channels simultaneously over an extended wavelength range of 58 nm from 1554 to 1612 nm is reported. The 3-dB (gain of 17-20 dB) bandwidth of the erbium-doped fiber amplifier is 54 nm when it is pumped with 350 mW of 1480-nm light. The power conversion efficiency of the fiber is about 54%.     

Improving channel carrier mobility and immunity to charge trapping of high-K NMOSFET by using stacked Y/sub 2/O/sub 3//HfO/sub 2/ gate dielectric

A stacked Y/sub 2/O/sub 3//HfO/sub 2/ multimetal gate dielectric with improved electron mobility and charge trapping characteristics is reported. Laminated hafnium and yttrium were sputtered on silicon followed by post-deposition anneal (PDA) in N/sub 2/ ambient. The new dielectric shows a similar scalability to HfO/sub 2/ reference. Analysis on flatband voltage shift indicates positive fixed charge induced by Y/sub 2/O/sub 3/. Excellent transistor characteristics have been demonstrated. Stacked Y/sub 2/O/sub 3//HfO/sub 2/, compared to HfO/sub 2/ reference with similar equivalent oxide thickness (EOT), shows 49% enhancement in transconductance and 65% increase in the peak electron mobility. These improvements may be attributed to better charge trapping characteristics of the multimetal dielectric.     

Ultrathin stacked Si/sub 3/N/sub 4//SiO/sub 2/ gate dielectrics prepared by rapid thermal processing

Ultrathin (58 AA equivalent oxide thickness) stacked Si/sub 3/N/sub 4//SiO/sub 2/ (NO) films with the bottom oxide prepared by rapid thermal oxidation (RTO) in O/sub 2/ and the top nitride deposited by rapid thermal processing chemical vapour deposition (RP-CVD) were fabricated and studied. Results show that the charge trapping and leakage current of the stacked films are comparable to those of pure SiO/sub 2/ and low-field breakdown events are significantly reduced. By scaling down the top nitride thickness the commonly observed flat-band voltage instability of MNOS devices was minimised, but the low-defect property was still preserved.<>     

La/sub 2/O/sub 3//Si/sub 0.3/Ge/sub 0.7/ p-MOSFETs with high hole mobility and good device characteristics

We have studied high-k La/sub 2/O/sub 3/ p-MOSFETs on Si/sub 0.3/Ge/sub 0.7/ substrate. Nearly identical gate oxide current, capacitance density, and time-dependent dielectric breakdown (TDDB) are obtained for La/sub 2/O/sub 3//Si and La/sub 2/O/sub 3//Si/sub 0.3/Ge/sub 0.7/ devices, indicating excellent Si/sub 0.3/Ge/sub 0.7/ quality without any side effects. The measured hole mobility in nitrided La/sub 2/O/sub 3//Si p-MOSFETs is 31 cm/sup 2//V-s and comparable with published data in nitrided HfO/sub 2//Si p-MOSFETs. In sharp contrast, a higher mobility of 55 cm/sup 2//V-s is measured in La/sub 2/O/sub 3//Si/sub 0.3/Ge/sub 0.7/ p-MOSFET, an improvement by 1.8 times compared with La/sub 2/O/sub 3//Si control devices. The high mobility in Si/sub 0.3/Ge/sub 0.7/ p-MOSFETs gives another step for integrating high-k gate dielectrics into the VLSI process.     

ZnO transparent thin-film transistors with HfO/sub 2//Ta/sub 2/O/sub 5/ stacking gate dielectrics

The performance improvement of ZnO thin-film transistors (TFTs) using HfO₂/Ta₂O₅ stacked gate dielectrics was demonstrated. The ZnO TFTs exhibited transistor behaviour over the range 0-10 V; the field effect mobility, subthreshold slope and on/off ratio were measured to be 1.3 cm² V^-1 s^-1, 0.5 V/decade and ~10⁶, respectively.     

Properties of Si/sub 3/N/sub 4//Si/sub x/Ge/sub 1-x/ metal-insulator-semiconductor capacitors

The density of fast interface states was studied in Si/sub 3/N/sub 4//Si/sub 0.8/Ge/sub 0.2/ metal-insulator-semiconductor (MIS) capacitors. The interface state density does not appear to be strongly affected by the presence of a thin Si interlayer between the nitride and SiGe alloy. This is in contrast to the results when SiO/sub 2/ is used as the insulator material in similar structures.<>     

Limitation of DC currents by YBa/sub 2/Cu/sub 3/O/sub 7-/spl delta//-Au superconducting films

The limitation of dc fault currents is one of the issues for the development of dc networks or links. This paper shows for the first time the high potential of YBa/sub 2/Cu/sub 3/O/sub 7-/spl delta//-Au bilayers for the design of dc current limiters. Such devices are based on the transition into the normal state of the superconducting YBa/sub 2/Cu/sub 3/O/sub 7-/spl delta// films above a current I/sup */>I/sub c/, where I/sub c/ is the critical current at the onset of dissipation. The study of the transition under current pulses shows that a thermally driven transition into the normal state can occur after a delay t/sub trans/. This duration is defined by the amplitude of the current pulse. For I/sup *//spl ap/3I/sub c/, this delay is less than 10 /spl mu/s. The abrupt transition into the normal state allows an efficient current limitation. A recovery of the superconducting state can also occur under current. This property can be extremely interesting for autonomous operation of a current limiter in an electrical network in case of transient over-currents coming from the starting of high-power devices.     

SiO/sub 2//AlGaN/InGaN/GaN MOSDHFETs

The characteristics of a novel nitride based field-effect transistor combining SiO/sub 2/ gate isolation and an AlGaN/InGaN/GaN double heterostructure design (MOSDHFET) are reported. The double heterostructure design with InGaN channel layer significantly improves confinement of the two-dimensional (2-D) electron gas and compensates strain modulation in AlGaN barrier resulting from the gate voltage modulations. These decrease the total trapped charge and hence the current collapse. The combination of the SiO/sub 2/ gate isolation and improved carrier confinement/strain management results in current collapse free MOSDHFET devices with gate leakage currents about four orders of magnitude lower than those of conventional Schottky gate HFETs.