共查询到19条相似文献,搜索用时 578 毫秒
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本文设计的硬件电路可以对温度进行实时监测并在温度异常时发出警报。该电路采用以AT89C51为核心的主控芯片,并且包含了传感器数据采集模块、温度显示模块、报警模块以及复位模块等电路。其中,温度显示模块通过LCD1602液晶显示器对温度进行实时显示;传感器数据采集电路采用DS18B20单总线型温度传感器。该系统电路设计简单,工作性能稳定,硬件成本低廉,灵敏度高。 相似文献
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基于WIFI的无线视频监控硬件电路设计 总被引:1,自引:0,他引:1
本设计基于WiFi无线摄像头的设计.它以STM32芯片为核心,采用以OV2640作为图像传感器的数字摄像头,通过WiFi模块将采集到的图像数据上传至手机上位机,在上位机上进行图像的显示.系统主要包括MCU模块的设计、OV2640摄像头电路的设计、WIFI接口电路的设计、电源部分设计、程序下载电路设计等. 相似文献
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《电子技术与软件工程》2015,(1)
无线蓝牙智能追踪小车是在控制系统的作用下,手机APP软件作为客户端,手机蓝牙作为指令发送方,蓝牙模块作为接收方,然后接收方通过串口仿真协议与控制系统进行通信,从而完成指令的无线传输控制小车前后左右运动。智能追踪是通过红外光电传感器采集信号,反馈给控制系统从而控制电机转动速度实现智能追踪。本设计中,采用STC12C5A60S2单片机作为主控芯片,五对红外光电传感器构成追踪检测电路,蓝牙模块采用HC-06,电机驱动电路及其他外围电路。设计实现了手机无线遥控小车以及沿黑色轨迹行走的智能追踪小车。 相似文献
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本文设计一种基于 SOC 芯片的通用处理模块,采用 SOC 内嵌的两个 RAM 分别实现不同 CPU 功能的方式实现通用处理模块的功能。模块实现了信号处理、信息处理、链路处理和话音处理等通用模块需要的功能,完成了 ADC 电路、DAC 电路、时钟电路、电源电路、话音电路等功能电路的设计和测试,为后续设备的小型化和通用化提供了扎实的研究基础和硬件支撑。 相似文献
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Joonhee Kang Gupta D. Kaplan S.B. 《Applied Superconductivity, IEEE Transactions on》2002,12(3):1848-1851
A 1-b slice of a rapid single-flux quantum (RSFQ) digitizer with interchip communications on a multichip module (MCM) has been successfully designed, fabricated using 3-μm Nb technology, and tested. We placed a flash comparator followed by an enable switch and an MCM transmitter circuit on one side of the chip, and an MCM receiver circuit followed by a memory buffer on the other side. The 5 × 5 mm chip was flip-chip mounted on a 10 × 10 mm carrier chip by a solder bump technique. During circuit operation, the comparator output signal and the clock signal left the chip, moved to the carrier chip, and returned back to the chip into the memory buffer. We operated the circuit with a beat frequency technique where the data input frequency was slightly off from the clock frequency by the beat frequency of 10 kHz. The circuit operated correctly up to 10 GHz. The critical circuit operation margin was observed to be the bias current to the SQUID in the MCM receiver circuit and was about ±6% at 10 GHz 相似文献
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设计一种简易的时钟电路,电路由单片机最小系统、电平转换模块、按键输入模块,时钟模块、液晶显示模块组成.电路以STC89C52单片机为控制核心,控制串行实时时钟芯片M41ST85W进行时钟读、写、报警操作. 相似文献
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Yamashina M. Enomoto T. Kunio T. Tamitani I. Harasaki H. Endo Y. Nishitani T. Satoh M. Kikuchi K. 《Solid-State Circuits, IEEE Journal of》1988,23(4):907-915
A video signal processor (VSP) LSI circuit with a three pipelined architecture has been developed for pattern matching, which is fundamental for the motion compensation necessary for teleconferencing systems. A high-speed arithmetic logic unit with absolute-value calculation capability and a minimum/maximum value detector, which are essential to pattern matching, have been integrated on the VSP LSI. The chip was fabricated with a 2.5-μm CMOS and double-layer metallization technology. The number of MOSFETs integrated on the 9.91×9.50-mm 2 chip is about 48000. It operates at a 14.3-MHz clock frequency with a single 5-V power supply and typically consumes 240 mW. An experimental video signal processing system, using a single VSP LSI chip, is discussed 相似文献
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为了满足数据采集及信号处理系统中对数据实时性的要求,采用TMS320VC5509为中心处理器,并对A/D转换、电源及复位电路、时钟电路、JTAG仿真电路等外围硬件进行了设计,使其能够在高速采样信号下,及时对数据进行处理,达到系统对处理速度的要求,实现了一种基于DSP的高速数据采集系统设计。 相似文献
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A fully integrated 2-D linear filter including a line buffer for a 7×7 kernel is presented. To run the filter in real time at video clock frequencies, an array of pipelined carry-save adders was used as a very fast arithmetic unit. The filter chip contains 292451 transistors on a silicon area of 135 mm2. The maximum clock frequency under worst-case conditions for technology and temperature was simulated to be 20 MHz. The main blocks are designed as independent parameterizable modules. The line buffer and the arithmetic unit are available as macros in a standard cell library for semicustom design. With these macros a semicustom chip for image enhancement in a X-ray system was produced. This chip works with a system frequency of 13 MHz. The line buffer module is used in another full-custom image processing chip-a two-dimensional rank order filter with a kernel size of also 7×7. This chip contains more than 300000 transistors on a silicon area of 103 mm2. In this case the module containing the 1-D FIR (finite impulse response) filters is replaced by additional pixel delays and a sorter module. Simulations have shown that the chip could work with clock frequencies up to 20 MHz 相似文献
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从硬件和软件两个角度出发,介绍基于DSP的多元数据同步采集与存储系统的组成、工作模式以及功能的测试。系统主要由上位机和数字采集与存储单元组成,其中数字采集与存储单元的硬件部分包括电源模块,值班电路模块,数据采集模块,数据存储模块,时钟同步模块。系统采用DSP作为中央处理芯片,利用经过同步后的秒脉冲作为触发信号,实现同步数据采集。以CF卡作为存储介质,实现数据自容式存储。软件部分实现自检、同步、数据采集存储功能。经过测试,系统工作稳定,功能正常,同步精度在100ns以内。 相似文献