基于Verilog HDL描述的802.11a基带芯片的测试方案

从提高测试效率和代码覆盖率的角度,提出一种利用VerilogHDL语言中的task来复用测试代码,进行分层分模块验证的测试方案。用该方案测试802.11a基带芯片,可对设计模块进行功能仿真,找出设计中的错误,以保证802.11a基带芯片在功能上的正确性和可行性。     

二进制代码的漏洞挖掘技术研究

基于网络信息安全漏洞问题越来越受重视,针对漏洞研究中测试代码覆盖率和漏洞挖掘效率问题,设计并实现了基于混合符号执行的Fuzzing测试系统;该系统采用了指令动态追踪、混合符号执行、约束求解、测试用例生成及动态测试5个模块,通过对系统各个环节优化处理提高效率,并实验验证系统代码覆盖率较传统Fuzzing测试工具也有较大提高,得出了该系统能适用于大型应用软件测试的结论。     

基于运行监测的图形用户界面自动化测试模型

为提高GUI自动化测试的覆盖率、故障定位的速率和精度,以及检测由于时空变化导致的空间错误引起的故障,建立基于运行监测的GUI自动化测试模型。模型将GUI分为窗口框架层、界面元素层、功能结构层和运行记录层四层。窗口框架层描述GUI所有窗口,界面元素层描述用户输入,功能结构层提出功能覆盖准则,运行记录层通过插桩记录代码动态监测软件每一次执行时路径和各个窗口的运行状态,从而提高测试的覆盖率,并根据运行记录中窗口的总执行次数和正确的执行次数为可靠性计算提供依据。由于监测代码的运行情况,因此故障能够定位到代码级,提高故障定位的精度和速率。最后以记事本程序为例验证了模型的有效性。     

多路系统Cache一致性验证中的错误追踪定位技术

以某国产多路系统的验证为例,基于事务级验证TBV技术,提出并实现了一种可以应用于模拟验证的自动错误追踪定位技术,通过在验证环境中对处理器的特定功能流程、相关各种请求响应、访存地址和数据流等信息进行事务级建模,记录并生成了验证环境运行产生的事务级信息库,基于上述信息实现了错误的自动追踪定位,显著缩短了错误定位时间,提升了多路系统模拟验证的查错效率。同时,基于事务级的模型,也使得验证人员可以在比设计部件更高的层次描述复杂流程的Cache一致性覆盖点,这种事务级维度的覆盖率描述弥补了原有代码覆盖率和功能覆盖率局限于模块和部件级的不足,是对全面性和充分性验证的有益补充。     

SoC功能验证的特点和方法

简要分析了传统集成电路（ASIC）验证方法的特点以及将这些方法应用于系统级芯片（SoC）验证时所面临的问题。在此基础上，论述说明了模块级验证是提高SoC验证效率的基础；而基于随机测试激励的验证方法能够提升SoC的功能验证的覆盖率。另外，还介绍了用于SoC功能验证的关键方法，包括断言和RTL形式验证，Farm，随机化测试激励和功能覆盖等。     

嵌入式软件语句覆盖率测试插桩技术

针对基于宿主机的嵌入式软件测试,提出一种单元测试中通用的语句覆盖率测试方法,通过插桩技术,采用向源代码插桩实现语句覆盖率测试。设计了测试代码的实现算法,通过测试代码可以自动完成向被测代码插桩。这些方法被成功地应用到笔者所在项目组开发的嵌入式软件仿真测试平台ARMtest上。利用这些方法,在嵌入式硬件系统未完成开发之前,可通过宿主机环境和仿真环境及时发现嵌入式软件开发初期的一些不足并加以完善。     

基于边界扫描技术的嵌入式处理器测试方法研究

现代先进微处理器有非常高的集成度和复杂度,而且芯片管脚数相对较少,必须要有一定的自测试设计和其它的可测试性设计来简化测试代码,提高故障覆盖率。该文提出了嵌入式处理器80386EX芯片内部功能的测试方案,设计了符合JTAG规范的测试系统结构,实现了芯片的内部功能部件的测试。接着,通过实验证明了文章所提方法的可行性。最后讨论了下一步的研究工作。     

基于IEEE1149标准的电子装备可测试性设计技术研究

针对新型电子装备功能与结构复杂、测试诊断难度大的问题,基于IEEE1149标准,提出了电子装备可测试性设计方法,系统地分析了模块级产品可测试性设计的内容,提出了器件与测试接口设计要求,阐述了测试扫描链路设计方法,并进一步研究了测试信号完整性设计技术,并结合电子装备计算机体系结构,设计了系统级测试性设计框架;通过实际验证,该项技术对于边界扫描器件互连测试覆盖率达100%,可以提高装备测试性设计水平,满足了电子装备测试诊断的需求.     

基于随机测试的SoC系统级功能验证方法的研究

为了克服 RTL 级验证方法的局限性,提出了采用随机测试向量在 SoC 的系统级进行功能验证的方法。该方法采用高级建模语言来构建系统级的测试平台,采用多种随机化机制来生成测试向量。测试结果表明,该方法不仅能够获得较好的功能覆盖率,而且能够尽可能早地发现 SoC 设计中的功能性错误。     

基于约束的处理器接口随机测试模型

提出了一种处理器接口测试模型，并给出了具体实现方案。该测试模型将仿真测试的方法应用于处理器接口测试，在激励生成中采用基于约束的随机测试生成方法。结果表明，基于约束的处理器接口随机测试模型的覆盖率达到83.68％，能够快速有效地完成处理器接口部件的功能验证。     

Can fault‐exposure‐potential estimates improve the fault detection abilities of test suites?

Code‐coverage‐based test data adequacy criteria typically treat all coverable code elements (such as statements, basic blocks or outcomes of decisions) as equal. In practice, however, the probability that a test case can expose a fault in a code element varies: some faults are more easily revealed than others. Thus, several researchers have suggested that if one could estimate the probability that a fault in a code element will cause a failure, one could use this estimate to determine the number of executions of a code element that are required to achieve a certain level of confidence in that element's correctness. This estimate, in turn, could be used to improve the fault‐detection effectiveness of test suites and help testers distribute testing resources more effectively. This conjecture is intriguing; however, like many such conjectures it has never been directly examined empirically. If empirical evidence were to support this conjecture, it would motivate further research into methodologies for obtaining fault‐exposure‐potential estimates and incorporating them into test data adequacy criteria. This paper reports the results of experiments conducted to investigate the effects of incorporating an estimate of fault‐exposure probability into the statement coverage test data adequacy criterion. The results of these experiments, however, ran contrary to the conjectures of previous researchers. Although incorporation of the estimates did produce statistically significant increases in the fault‐detection effectiveness of test suites, these increases were quite small, suggesting that the approach might not be able to produce the gains hoped for and might not be worth the cost of its employment. Copyright © 2002 John Wiley & Sons, Ltd.     

Measuring and specifying combinatorial coverage of test input configurations

A key issue in testing is how many tests are needed for a required level of coverage or fault detection. Estimates are often based on error rates in initial testing, or on code coverage. For example, tests may be run until a desired level of statement or branch coverage is achieved. Combinatorial methods present an opportunity for a different approach to estimating required test set size, using characteristics of the test set. This paper describes methods for estimating the coverage of, and ability to detect, t-way interaction faults of a test set based on a covering array. We also develop a connection between (static) combinatorial coverage and (dynamic) code coverage, such that if a specific condition is satisfied, 100 % branch coverage is assured. Using these results, we propose practical recommendations for using combinatorial coverage in specifying test requirements, and for improving estimates of the fault detection capacity of a test set.     

基于通信多端口有限状态机的协议互操作性测试生成研究

协议测试是一种保证网络通信协议实现质量的重要技术，互操作性测试是一类常用的协议测试技术．文章提出了一种基于通信多端口有限状态机模型的协议互操作忡测试生成方法．首先采用已有的基于可达性分析的方法生成集中式测试序列；然后采用单一错误模型对其进行系统的错误覆盖分析，为达到更高的错误覆盖度，进一步提出一种增强的测试生成算法；最后讨论了互操作性测试巾的控制观察问题，选择适当的分布式测试架构，并进而生成分布式同步测试序列．实验结果表明：与原有方法相比，该方法可以有效地提高测试集的错误覆盖，并具备一定的可行性和有效性．     

Mixed hierarchical-functional fault models for targeting sequential cores

Current work presents a set of fault models allowing high coverage for sequential cores in systems-on-a-chip. We propose a novel approach combining a hierarchical fault model for functional blocks, a functional fault model for multiplexers and a mixed hierarchical-functional fault model for comparison operators, respectively. The fault models are integrated into a fast high-level decision diagram based test path activation tool. According to the experiments, the proposed method significantly outperforms state-of-the-art test pattern generation tools. The main new contribution of this paper is a formal definition of high-level decision diagram representations and the combination of the three fault models in order to target high gate-level stuck-at fault coverage for sequential cores.     

基于Robot Framework的MVC GUI模块自动化测试框架

基于Robot Framework提出了一种面向MVC GUI模块的自动化测试框架。该框架将GUI自动化测试分为四大方面：用户界面功能测试、信息设置功能测试、信息查询功能测试和特殊项测试。整个框架将上层 GUI和底层Database进行结合测试,使GUI自动化测试范围得以全面覆盖;并根据不同系统环境,编写Python脚本,灵活调用底层数据;而选用黑盒与白盒有机结合的测试方式,使测试者可以迅速锁定代码缺陷,保证了开发程序的正确性和完整性。同时,就OpenWRT LuCI模块作为具体实例,验证了本框架的适用性。     

A model-driven framework to enhance the consistency of logical integrity constraints: Introducing integrity regression testing

Although the importance of models continuously grows in software development, common development approaches are less able to integrate the automatic management of model integrity into the development process. These critically important constraints may ensure the coherence of models in the evolution process to prevent manipulations that could violate defined constraints on a model. This paper proposes an integrity framework in the context of model-driven architecture to achieve sufficient structural code coverage at a higher program representation level than machine code. Our framework offers to propagate the modifications from a platform-independent specification to the corresponding test template model while keeping the consistency and integrity constraints after system evolution. To examine the efficiency of the proposed framework, a quantitative analysis plan is evaluated based on two experimental case studies. In addition, we propose coverage criteria for integrity regression testing (IRT), derived from logic coverage criteria that apply different conceptual levels of testing for the formulation of integrity requirements. The defined criteria for IRT reduce the inherent complexity and cost of verifying complex design changes in regression testing while keeping the fault detection capability with respect to the changes. The framework aims to keep pace with IRT in a formal way. The framework can solve a number of restricted outlooks in model integrity and some limiting factors of incremental maintenance and retesting. The framework satisfies several valuable quality attributes in software testing, such as safety percentage, precision, abstract fault detection performance measurable coverage level, and generality.     

A time/structure based software reliability model

The past 20 years have seen the formulation of numerous analytical software reliability models for estimating the reliability growth of a software product. The predictions obtained by applying these models tend to be optimistic due to the inaccuracies in the operational profile, and saturation effect of testing. Incorporating knowledge gained about some structural attribute of the code, such as test coverage, into the time-domain models can help alleviate this optimistic trend. In this paper we present an enhanced non-homogeneous Poisson process (ENHPP) model which incorporates explicitly the time-varying test-coverage function in its analytical formulation, and provides for defective fault detection and test coverage during the testing and operational phases. It also allows for a time varying fault detection rate. The ENHPP model offers a unifying framework for all the previously reported finite failure NHPP models via test coverage. We also propose the log-logistic coverage function which can capture an increasing/decreasing failure detection rate per fault, which cannot be accounted for by the previously reported finite failure NHPP models. We present a methodology based on the ENHPP model for reliability prediction earlier in the testing phase. Expressions for predictions in the operational phase of the software, software availability, and optimal software release times subject to various constraints such as cost, reliability, and availability are developed based on the ENHPP model. We also validate the ENHPP model based on four different coverage functions using five failure data sets. This revised version was published online in June 2006 with corrections to the Cover Date.     

边界扫描技术的功能测试应用

随着芯片集成度的提高和表面贴装技术(SMT)的广泛使用,传统的针床在线测试已不再适合使用,而边界扫描技术在芯片级、板级、系统级测试得到广泛使用将是一种必然趋势。与传统边界扫描技术生成测试矢量进行结构化的静态测试不同,功能测试程序可采用高级语言开发,易于开发和维护。本文介绍了使用边界扫描技术对DDR模块进行动态的功能测试,该功能测试程序可快速准确测试出高速DDR模块数据线、地址线及存储单元是否能正常工作,并输出测试诊断信息。在此基础上,本文对该测试程序进行了改进。     

嵌入式软件覆盖测试工具的研究

随着嵌入式系统的复杂性不断提高,嵌入式软件测试变得越来越重要;通过对ARM系统软件进行深入的研究,提出了一种应用于ARM嵌入式软件系统的覆盖测试工具的设计原理、系统模型及组成模块,分别就各个模块的具体设计进行了详细说明,着重探讨了词法语法分析和插装方式,提出了一种新的词法语法分析和插装方式;该工具能够实现ARM系列嵌入式软件的自动测试,测试了代码执行的覆盖情况,检查出代码死区,从而提高了测试效率,使嵌入式软件质量得到保证.     

Robustness testing of Java server applications

This paper presents a new compile-time analysis that enables a testing methodology for white-box coverage testing of error recovery code (i.e., exception handlers) of server applications written in Java, using compiler-directed fault injection. The analysis allows compiler-generated instrumentation to guide the fault injection and to record the recovery code exercised. (An injected fault is experienced as a Java exception.) The analysis 1) identifies the exception-flow "def-uses" to be tested in this manner, 2) determines the kind of fault to be requested at a program point, and 3) finds appropriate locations for code instrumentation. The analysis incorporates refinements that establish sufficient context sensitivity to ensure relatively precise def-use links and to eliminate some spurious def-uses due to demonstrably infeasible control flow. A runtime test harness calculates test coverage of these links using an exception def-catch metric. Experiments with the methodology demonstrate the utility of the increased precision in obtaining good test coverage on a set of moderately sized server benchmarks.