Improved Electrical Properties of Ge p-MOSFET With $ hbox{HfO}_{2}$ Gate Dielectric by Using $hbox{TaO}_{x} hbox{N}_{y}$ Interlayer

The electrical characteristics of germanium p-metal-oxide-semiconductor (p-MOS) capacitor and p-MOS field-effect transistor (FET) with a stack gate dielectric of HfO₂/TaOxNy are investigated. Experimental results show that MOS devices exhibit much lower gate leakage current than MOS devices with only HfO₂ as gate dielectric, good interface properties, good transistor characteristics, and about 1.7-fold hole-mobility enhancement as compared with conventional Si p-MOSFETs. These demonstrate that forming an ultrathin passivation layer of TaOxNy on germanium surface prior to deposition of high-k dielectrics can effectively suppress the growth of unstable GeOx, thus reducing interface states and increasing carrier mobility in the inversion channel of Ge-based transistors.     

Investigation of the Correlation Between Temperature and Enhancement of Electron Tunneling Current Through $hbox{HfO}_{bf 2}$ Gate Stacks

A model is established to describe the temperature dependence of the electron tunneling current through HfO₂ gate stacks based on analyzing the coupling between the longitudinal and transverse components of electron thermal energy caused by the difference of the effective electron mass between the HfO₂ gate stacks and silicon. By analyzing the three-dimensional Schrodinger equation for a MOS structure with HfO₂ gate stacks, a reduction in the barrier height is resulted from the large effective electron mass mismatch between the gate oxide and the gate (substrate). The calculated electron tunneling currents agree well with the experimental data over a wide temperature range. This coupling model can explain the temperature dependence of the electron tunneling current through HfO₂ gate stacks very well. The numerical results also demonstrate that the temperature dependence of the electron tunneling current strongly depends on the effective electron mass of HfO₂. This temperature sensitivity of the electron tunneling current can be proposed as a novel method to determine the effective electron mass of the gate oxide.     

Carrier Transportation Mechanism of the $hbox{TaN}/ hbox{HfO}_{2}/hbox{IL}/hbox{Si}$ Structure With Silicon Surface Fluorine Implantation

In this paper, the current transportation mechanism of HfO₂ gate dielectrics with a TaN metal gate and silicon surface fluorine implantation is investigated. Based on the experimental results of the temperature dependence of gate leakage current and Fowler-Nordheim tunneling characteristics at 77 K, we have extracted the current transport mechanisms and energy band diagrams for TaN/HfO₂/IL/Si structures with fluorine incorporation, respectively. In particular, we have obtained the following physical quantities: 1) fluorinated and as-deposited interfacial layer (IL)/Si barrier heights (or conduction band offsets) at 3.2 and 2.7 eV; 2) TaN/fluorinated and as-deposited HfO₂ barrier heights at 2.6 and 1.9 eV; and 3) effective trapping levels at 1.25 eV (under both gate and substrate injections) below the HfOF conduction band and at 1.04 eV (under gate injection) and 1.11 eV (under substrate injection) below the HfO₂ conduction band, which contributes to Frenkel-Poole conduction.     

AlGaN/GaN MOS-HEMT With $hbox{HfO}_{2}$ Dielectric and $hbox{Al}_{2}hbox{O}_{3}$ Interfacial Passivation Layer Grown by Atomic Layer Deposition

We have developed a novel AlGaN/GaN metal-oxide-semiconductor high-electron mobility transistor using a stack gate HfO₂/Al₂O₃ structure grown by atomic layer deposition. The stack gate consists of a thin HfO₂ (30-A) gate dielectric and a thin Al₂O₃ (20- A) interfacial passivation layer (IPL). For the 50-A stack gate, no measurable C-V hysteresis and a smaller threshold voltage shift were observed, indicating that a high-quality interface can be achieved using a Al₂O₃ IPL on an AlGaN substrate. Good surface passivation effects of the Al₂O₃ IPL have also been confirmed by pulsed gate measurements. Devices with 1- mum gate lengths exhibit a cutoff frequency (fT) of 12 GHz and a maximum frequency of oscillation (f _MAX) of 34 GHz, as well as a maximum drain current of 800 mA/mm and a peak transconductance of 150 mS/mm, whereas the gate leakage current is at least six orders of magnitude lower than that of the reference high-electron mobility transistors at a positive gate bias.     

Electrical Properties of Low-$V_{T}$ Metal-Gated n-MOSFETs Using $hbox{La}_{2}hbox{O}_{3}/hbox{SiO}_{x}$ as Interfacial Layer Between HfLaO High- $kappa$ Dielectrics and Si Channel

In this letter, we report that by employing the La₂O₃/SiO_x interfacial layer between HfLaO (La = 10%) high- and Si channel, the Ta₂C metal-gated n-MOSFETs V_T can be significantly reduced by ~350 mV to 0.2 V, satisfying the low-Vy device requirement. The resultant n-MOSFETs also exhibit an ultrathin equivalent oxide thickness (~1.18 nm) with a low gate leakage (J_G = 10 mA/cm² at 1.1 V), good drive performance (I_on = 900 muA/mum at I_soff = 70 nA/mum), and acceptable positive-bias-temperature-instability reliability.     

RF and Logic Performance Improvement of $ hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}/hbox{InAs}/hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}$ Composite-Channel HEMT Using Gate-Sinking Technology

Eighty-nanometer-gate In_0.7Ga_0.3As/InAs/In_0.7Ga_0.3As composite-channel high-electron mobility transistors (HEMTs), which are fabricated using platinum buried gate as the Schottky contact metal, were evaluated for RF and logic application. After gate sinking at 250degC for 3 min, the device exhibited a high g_m value of 1590 mS/mm at V_d = 0.5 V, the current-gain cutoff frequency f_T was increased from 390 to 494 GHz, and the gate-delay time was decreased from 0.83 to 0.78 ps at supply voltage of 0.6 V. This is the highest f_T achieved for 80-nm-gate-length HEMT devices. These superior performances are attributed to the reduction of distance between gate and channel and the reduction of parasitic gate capacitances during the gate-sinking process. Moreover, such superior performances were achieved through a very simple and straightforward fabrication process with optimal epistructure of the device.     

Impacts of Fluorine Ion Implantation With Low-Temperature Solid-Phase Crystallized Activation on High- $kappa$ LTPS-TFT

In this letter, fluorine ion implantation with low- temperature solid-phase crystallized activation scheme is used to obtain a high-performance HfO₂ low-temperature poly-Si thin- film transistor (LTPS-TFT) for the first time. The secondary ion mass spectrometer (SIMS) analysis shows a different fluorine profile compared to that annealed at high temperature. About one order current reduction of I_min is achieved because 25% grain- boundary traps are passivated by fluorine implantation. In addition, the threshold voltage instability of hot carrier stress is also improved with the introduction of fluorine. The LTPS-TFT with HfO₂ gate dielectric and fluorine preimplantation can simultaneously achieve low V_TH ~ 1.32 V, excellent subthreshold swing ~0.141 V/dec, and high I_ON/I_min current ratio ~1.98 times 10⁷.     

Fabrication of Self-Aligned Enhancement-Mode $ hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ MOSFETs With $ hbox{TaN/HfO}_{2}hbox{/AlN}$ Gate Stack

In this letter, we report the fabrication and characterization of self-aligned inversion-type enhancement-mode In_0.53Ga_0.47As metal-oxide-semiconductor field-effect transistors (MOSFETs). The In_0.53Ga_0.47As surface was passivated by atomic layer deposition of a 2.5-nm-thick AIN interfacial layer. In_0.53Ga_0.47As MOS capacitors showed an excellent frequency dispersion behavior. A maximum drive current of 18.5 muA/mum was obtained at a gate overdrive of 2 V for a MOSFET device with a gate length of 20 mum. An I_on/_off ratio of 104, a positive threshold voltage of 0.15 V, and a subthreshold slope of ~165 mV/dec were extracted from the transfer characteristics. The interface-trap density is estimated to be ~7-8 times 10¹² cm^-2 ldr eV^-1 from the subthreshold characteristics of the MOSFET.     

$hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ Channel MOSFETs With Self-Aligned InAs Source/Drain Formed by MEE Regrowth

Abstract-We report Al₂O₃Zln_0.53Ga_0.47As MOSFETs having both self-aligned in situ Mo source/drain ohmic contacts and self-aligned InAs source/drain n⁺ regions formed by MBE regrowth. The device epitaxial dimensions are small, as is required for 22-nm gate length MOSFETs; a 5-nm In_0.53Ga_0.47As channel with an In_0.4sAl_0.52As back confinement layer and the n⁺⁺ source/drain junctions do not extend below the 5-nm channel. A device with 200-nm gate length showed I_D = 0.95 mA/mum current density at V_GS = 4.0 V and g_m = 0.45 mS/mum peak transconductance at V_DS = 2.0 V.     

Improved Stability of High-Performance ZnO/ZnMgO Hetero-MISFETs

Improved performance and stability was demonstrated for ZnO/ZnMgO hetero-MISFETs. The MIS gate structures that were formed using either a 50-nm-thick Al₂O₃ or HfO₂ gate dielectric layer were examined by observation of the transfer characteristic hysteresis. A significantly reduced hysteresis of less than 0.1 V was obtained for HfO₂ as compared to that for the Al₂O₃ gate dielectric. By reducing the access resistance, the 1-mum gate devices showed improved transconductance values, as high as 54 mS/mm for Al₂O₃ and 71 mS/mm for HfO₂, which are the highest values ever reported for ZnO-based FETs.     

Determination of Work Functions in the $hbox{Ta}_{1 - x}hbox{Al}_{x}hbox{N}_{y}/hbox{HfO}_{2}$ Advanced Gate Stack Using Combinatorial Methodology

Combinatorial methodology enables the generation of comprehensive and consistent data sets, compared with the ldquoone-composition-at-a-timerdquo approach. We demonstrate, for the first time, the combinatorial methodology applied to the work function (Phi_m) extraction for Ta_1-xAl_xN_y alloys as metal gates on HfO₂, for complementary metal-oxide-semiconductor applications, by automated measurement of over 2000 capacitor devices. Scanning X-ray microdiffraction indicates that a solid solution exists for the Ta_1-xAl_xN_y libraries for 0.05 les x les 0.50. The equivalent oxide thickness maps offer a snapshot of gate stack thermal stability, which show that Ta_1-xAl_xN_y alloys are stable up to 950^degC . The Phi_m of the Ta_1-xAl_xN_y libraries can be tuned as a function of gate metal composition over a wide (0.05 les x les 0.50) composition range, as well as by annealing. We suggest that Ta_0.9Al_0.1N_1.24 gate metal electrodes may be useful for p-channel metal-oxide-semiconductor applications.     

Electrical characteristics of highly reliable ultrathin hafniumoxide gate dielectric

Electrical and reliability properties of ultrathin HfO₂ have been investigated. Pt electroded MOS capacitors with HfO₂ gate dielectric (physical thickness ~45-135 Å and equivalent oxide thickness ~13.5-25 Å) were fabricated. HfO₂ was deposited using reactive sputtering of a Hf target with O₂ modulation technique. The leakage current of the 45 Å HfO₂ sample was about 1×10^-4 A/cm ² at +1.0 V with a breakdown field ~8.5 MV/cm. Hysteresis was <100 mV after 500°C annealing in N₂ ambient and there was no significant frequency dispersion of capacitance (<1%/dec.). It was also found that HfO₂ exhibits negligible charge trapping and excellent TDDB characteristics with more than ten years lifetime even at V_DD=2.0 V     

Achieving Low-$V_{T}$ Ni-FUSI CMOS by Ultra-Thin $hbox{Dy}_{2}hbox{O}_{3}$ Capping of Hafnium Silicate Dielectrics

This letter reports that the effective work function (eWF) of Ni-Fully Silicided (Ni-FUSI) devices with HfSiON gate dielectrics can be modulated toward the silicon conduction band-edge by deposition of an ultra-thin Dy₂O₃ cap layer on the host dielectric. The obtained eWF depends on the deposited cap layer thickness and the Ni-FUSI phase, with 10 Aring Dy₂O₃ cap resulting in DeltaeWF ap 400 meV and final eWF ap 4.08 eV for NiSi-FUSI. Dielectric intermixing occurs without impacting the VT uniformity, gate leakage, mobility, and reliability. Well-behaved short-channel devices ( Lg ~ 100 nm, SS ~ 70 mV/dec, and DIBL ~ 65 mV/V) are demonstrated for both HfSiON and [HfSiON/Dy₂O₃ cap (5 Aring)] devices with NiSi-FUSI gates, corresponding to a similar . This capping approach, when combined with Ni-silicide FUSI phase engineering, allows (n-p) values up to 800 meV, making it promising for low- CMOS.     

Flicker-Noise Improvement in 100-nm $L_{g} hbox{Si}_{0.50}hbox{Ge}_{0.50}$ Strained Quantum-Well Transistors Using Ultrathin Si Cap Layer

This letter presents a record low flicker-noise spectral density in biaxial compressively strained p-channel 100-nm L_gSi_0.50Ge_0.50 quantum-well FETs (QWFETs) with ultrathin Si (~2 nm) barrier layer and 1-nm EOT hafnium silicate gate dielectric. The normalized power spectral density of I_d fluctuations (S_Id/I_d ²) in Si_0.50Ge_0.50 QWFETs exhibits significant improvement by ten times over surface channel unstrained Si pMOSFETs at high V_g due to strong confinement of holes within the high-mobility QW and strong quantization in the ultrathin Si barrier layer enabled by low-thermal-budget device processing. The noise behavior in strained QW devices is found to evolve from being correlated mobility fluctuation dominated across most of V_g range to being Hooge mobility fluctuation dominated at very high V_g.     

Partial Crystallization of HfO2 for Two-Bit/Four-Level SONOS-Type Flash Memory

The nonvolatile memory properties of the partially crystallized HfO₂ charge storage layer are investigated using short-channel devices of gate length L_g down to 80 nm. Highly efficient two-bit and four-level device operation is demonstrated by channel hot electron injection programming and hot hole injection erasing for devices of L_g > 170 nm, although the reduction of the memory window is observed for devices of L_g < 170 nm. A memory window of 5.5 V, ten-year retention of V_th clearance larger than 1.5 V between adjacent levels, endurance for 10⁵ programming/erasing cycles, and immunity to programming disturbances are demonstrated. Flash memory with partially crystallized HfO₂ shows a larger memory window than HfO₂ nanodot memory, assisted by the enhanced electron capture efficiency of an amorphous HfO₂ matrix, which is lacking in other types of reported nanodot memory. The scalability, programming speed, V_th control for two-bit and four-level operation, endurance, and retention are also improved, compared with NROM devices that use a Si₃N₄ trapping layer.     

Current transport in metal/hafnium oxide/silicon structure

Based on the experimental results of the temperature dependence of gate leakage current and Fowler-Nordheim tunneling characteristics at 77 K, we have extracted the energy band diagrams and current transport mechanisms for metal/HfO₂/Si structures. In particular, we have obtained the following quantities that will be useful for modeling and simulation: i) HfO₂/Si conduction band offset (or barrier height): 1.13 ± 0.13 eV; ii) Pt/HfO₂ barrier height: ~ 2.48 eV; iii) Al/HfO₂ barrier height: ~ 1.28 eV; iv) electron effective mass in HfO₂: 0.1 m_o, where m_o is the free electron mass and v) a trap level at 1.5 ± 0.1 eV below the HfO₂ conduction band which contributes to Frenkel-Poole conduction     

Demonstration of Low-Leakage-Current Low-On-Resistance 600-V 5.5-A GaN/AlGaN HEMT

This letter demonstrates a high-voltage, high-current, and low-leakage-current GaN/AlGaN power HEMT with HfO₂ as the gate dielectric and passivation layer. The device is measured up to 600 V, and the maximum on-state drain current is higher than 5.5 A. Performance of small devices with HfO₂ and Si₃N₄ dielectrics is compared. The electric strength of gate dielectrics is measured for both HfO₂ and Si₃N₄. Devices with HfO₂ show better uniformity and lower leakage current than Si₃N₄ passivated devices. The 5.5-A HfO₂ devices demonstrate very low gate (41 nA/mm) and drain (430 nA/mm) leakage-current density and low on-resistance (6.2 Omegamiddotmm or 2.5 mOmegamiddotcm²).     

Yttrium- and Terbium-Based Interlayer on SiO2 and HfO2 Gate Dielectrics for Work Function Modulation of Nickel Fully Silicided Gate in nMOSFET

Novel yttrium- and terbium-based interlayers (Y_IL and Tb_IL, respectively) on SiO₂ and HfO₂ gate dielectrics were employed for NMOS work function Phi_m modulation of undoped nickel fully silicided (Ni-FUSI) gate. Bandedge Ni-FUSI gate Phi_m of ~4.11 and ~4.07 eV was obtained by insertion of ultrathin (~1 nm) Y_IL and Tb_IL, respectively, on the SiO₂ gate dielectric in a gate-first process (with 1000 degC anneal). NiSi Phi_m on SiO₂ could also be tuned between the Si midgap and the conduction bandedge E_C by varying the interlayer thickness. The achievement of NiSi Phi_m around 4.28 eV on the HfO₂ gate dielectric using interlayer insertion makes this an attractive Phi_m modulation technique for Ni-FUSI gates on SiO₂ and high-k dielectrics     

Enhancement-Mode Buried-Channel $hbox{In}_{0.7} hbox{Ga}_{0.3}hbox{As/In}_{0.52}hbox{Al}_{0.48}hbox{As}$ MOSFETs With High- $kappa$ Gate Dielectrics

The operation of long- and short-channel enhancement-mode In_0.7Ga_0.3As-channel MOSFETs with high-k gate dielectrics are demonstrated for the first time. The devices utilize an undoped buried-channel design. For a gate length of 5 mum, the long-channel devices have V_t= +0.25 V, a subthreshold slope of 150 mV/dec, an equivalent oxide thickness of 4.4 +/ - 0.3 nm, and a peak effective mobility of 1100 cm²/Vldrs. For a gate length of 260 nm, the short-channel devices have V_t=+0.5 V and a subthreshold slope of 200 mV/dec. Compared with Schottky-gated high-electron-mobility transistor devices, both long- and short-channel MOSFETs have two to four orders of magnitude lower gate leakage.     

ZnO transparent thin-film transistors with HfO/sub 2//Ta/sub 2/O/sub 5/ stacking gate dielectrics

The performance improvement of ZnO thin-film transistors (TFTs) using HfO₂/Ta₂O₅ stacked gate dielectrics was demonstrated. The ZnO TFTs exhibited transistor behaviour over the range 0-10 V; the field effect mobility, subthreshold slope and on/off ratio were measured to be 1.3 cm² V^-1 s^-1, 0.5 V/decade and ~10⁶, respectively.