A new interpolation technique for time interleaved \Upsigma\Updelta A/D converters

Time interleaved sigma-delta converter is a potential candidate for multi-mode wideband analog to digital (A/D) converters dedicated for multistandard receivers. However, the interpolation by zeros to compress the useful signal bandwidth at the input of the sigma-delta modulator imposes constraints on the implementation of the analog part leading to a very large die area due to the high value required for the sampling capacitor. This paper proposes a new interpolation technique using extra samples instead of zeros resulting from the oversampling of the input signal. This new technique not only reduces the die area and the order of the anti-alias filter but also improves A/D converter performance. The proposed technique was simulated and implemented in a four channel time interleaved sigma-delta designed in a 1.2 V 65?nm CMOS process.     

一种低功耗高精度Sigma-Delta调制器

提出了一种改进的三阶单环Sigma-Delta调制器,噪声传递函数采用前馈方式实现极点,降低了积分器输出信号的幅度,从而降低功耗;采用局部反馈实现零点,从而优化了输出信噪比。采用0.35μm CMOS工艺设计了该调制器,过采样率128,信号带宽24kHz,分辨率16bit,在3.3V工作电压下,模拟电路部分功耗2.7mW,数字部分功耗0.5mW。电路用开关电容技术实现,在HSPICE中通过多工艺角验证。     

A cascaded continuous-time /spl Sigma//spl Delta/ Modulator with 67-dB dynamic range in 10-MHz bandwidth

This paper presents the design of a 2-2 cascaded continuous-time sigma-delta modulator. The cascaded modulator comprises two stages with second-order continuous-time resonator loopfilters, 4-bit quantizers, and feedback digital-to-analog converters. The digital noise cancellation filter design is determined using continuous-time to discrete-time transformation of the sigma-delta loopfilter transfer functions. The required matching between the analog and digital filter coefficients is achieved by means of simple digital calibration of the noise cancellation filter. Measurement results of a 0.18-/spl mu/m CMOS prototype chip demonstrate 67-dB dynamic range in a 10-MHz bandwidth at 8 times oversampling for a single continuous-time cascaded modulator. Two cascaded modulators in quadrature configuration provide 20-MHz aggregate bandwidth. Measured anti-alias suppression is over 50 dB for input signals in the band from 150 to 170 MHz around the sampling frequency of 160 MHz.     

The Structure of Quantization Noise from Sigma-Delta Modulation

When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.     

A Power-Efficient Two-Channel Time-Interleaved ΣΔ Modulator for Broadband Applications

A two-channel time-interleaved second-order sigma-delta modulator for broadband applications including asymmetrical digital subscriber line (ADSL) is presented. The proposed two-channel SigmaDelta modulator uses a single integrator channel which does not require additional active elements for the quantizer input generation, since the integrator outputs are directly used as the input of the quantizers. As a result, the entire modulator can be implemented using only two op-amps, which is beneficial for both power consumption and area. Furthermore, this architecture is robust to channel mismatch effects and can operate with a simple clocking scheme. The SigmaDelta modulator achieves a dynamic range of 85 dB over a 1.1-MHz signal bandwidth with an effective clock frequency of 132 MHz. The circuit is implemented in 0.18-mum CMOS technology using metal-insulator-metal capacitors. The total power consumption of the SigmaDelta modulator is 5.4mW from a 1.8-V supply and occupies an active area of 1.1 mm²     

A third-order sigma-delta modulator with extended dynamic range

Oversampling modulators based on high-order sigma-delta modulation provide an effective means of achieving high-resolution analog-to-digital conversion in VLSI technology. Because high-order noise shaping greatly reduces the quantization noise in the signal band, the dynamic range of these modulators tends to be bounded by the thermal noise of the input stage and the maximum voltage swing in the signal path. This paper introduces a third-order cascaded sigma-delta modulator that uses a modified cascaded architecture and reduced gain in the first integrator to increase the dynamic range. An experimental modulator fabricated in a 1-μm CMOS technology attains a resolution of 17 b for a 25-kHz signal bandwidth while operating from a single 5-V supply. With an oversampling ratio of 128 and a clock frequency of 6.4 MHz, the modulator achieves a 104-dB dynamic range and a peak signal-to-noise+distortion ratio (SNDR) of 98 dB. As indicated by both measurements and simulations, the cascaded architecture also greatly reduces the discrete noise peaks that can be present in a single-stage architecture     

A novel versatile modulator circuit

A novel versatile modulator that can operate either as a delta modulator, a sigma-delta modulator, an amplitude modulator or a frequency modulator is presented. The proposed circuit mainly composes of a few components: which are three OTAs, one capacitor and two resistors. Among these components, two OTAs and two resistor construct a Schmitt trigger network whereas the other OTA and a capacitor compose an integrator. The advantage of this circuit is that the clock (carrier) signal employed for modulation is inherent in the circuit. No external clock is needed, only the modulating signal is required for an input. With the compactness of the circuit, it is thus suitable for IC realization. The computer simulation based on CMOS technology demonstrates that the results agree well with the theoretical analysis.     

A 14-bit, 10-Msamples/s D/A converter using multibit /spl Sigma//spl Delta/ modulation

A 14-bit digital-to-analog converter based on a fourth-order multibit sigma-delta modulator is described. The digital modulator is pipelined to minimize both its power dissipation and design complexity. The 6-bit output of this modulator is converted to analog using 64 current-steering cells that are continuously calibrated to a reference current. This converter achieves 85-dB dynamic range at 5-MHz signal bandwidth, with an oversampling ratio of 12. The chip was fabricated in a 0.5-/spl mu/m CMOS technology and operates from a single 2.5-V supply.     

A low-voltage low-power sigma-delta modulator for broadband analog-to-digital conversion

A cascade of sigma-delta modulator stages that employ a feedforward architecture to reduce the signal ranges required at the integrator inputs and outputs has been used to implement a broadband, high-resolution oversampling CMOS analog-to-digital converter capable of operating from low-supply voltages. An experimental prototype of the proposed architecture has been integrated in a 0.25-/spl mu/m CMOS technology and operates from an analog supply of only 1.2 V. At a sampling rate of 40 MSamples/sec, it achieves a dynamic range of 96 dB for a 1.25-MHz signal bandwidth. The analog power dissipation is 44 mW.     

A multi-stage sigma-delta modulator based on noise-coupling and digital feed-forward techniques

This paper presents a new structure for high-resolution, low-power and wideband discrete time multi-stage (DT-MASH) sigma-delta (ΣΔ) modulators. It uses multi-bit digital input feed forward path (DFF) and noise coupling (NC) techniques. With the DFF technique, the modulator does not need a power-consuming analog adder at the quantizer input, and the number of comparators of the quantizer will be reduced significantly. Also, because of the reduced swing of the modulator’s integrators, low power integrators can be used. Using a second-order NC technique with no extra active block, the order of the modulator, which uses some paths between analog stages, is increased, and its performance is improved with zero-optimization of the modulator’s noise transfer function (NTF). Behavioral simulations and extensive mathematical analyses confirm the effectiveness of the proposed structure. The effect of the non-idealities in the DFF and NC paths were considered in the behavioral simulations. To examine its performance, a MASH 2–1 modulator was designed in the circuit level with a 180-nm CMOS technology and 1.8 V power supply. The integrators use a new op-amp switching technique to reduce total power consumption. With an over-sampling ratio (OSR) of 8 for the 10 MHz signal bandwidth, the proposed structure improves the signal-to-noise and distortion ratio (SNDR) by 28 dB compared with a conventional MASH 2–1 structure at approximately the same power consumption and very low complexity.

     

A third-order /spl Sigma//spl Delta/ modulator in 0.18-/spl mu/m CMOS with calibrated mixed-mode integrators

This paper describes a third-order sigma-delta (/spl Sigma//spl Delta/) modulator that is designed and implemented in 0.18-/spl mu/m CMOS process. In order to increase the dynamic range, this modulator takes advantage of mixed-mode integrators that consist of analog and digital integrators. A calibration technique is applied to the digital integrator to mitigate mismatch between analog and digital paths. It is shown that the presented modulator architecture can achieve a 12-dB better dynamic range than conventional structures with the same oversampling ratio (OSR). The experimental prototype chip achieves a 76-dB dynamic range for a 200-kHz signal bandwidth and a 55-dB dynamic range for a 5-MHz signal bandwidth. It dissipates 4 mW from 1.8-V supply voltages and occupies 0.7-mm/sup 2/ silicon area.     

A low-power parametric integrator for wideband switched-capacitor ΣΔ modulators

This paper proposes a new low-power MOS parametric integrator (MPI) for the design of wideband discrete time sigma-delta (ΣΔ) modulators. The MPI is implemented with MOS capacitors, which provide the required gain by switching from inversion in the sampling phase into depletion in the amplification phase. Analysis along with simulation results illustrate that MPI consumes very low power dissipation compared to the conventional active integrators with some negligible performance changes. To verify this, the MPI is used in two wideband ΣΔ modulators, one with 8-bit resolution and the other with 13-bit resolution with input bandwidth and sampling frequency of 12.5 and 200 MHz, respectively. The first one is a second order single stage ΣΔ modulator and the second one is a MASH 2-2 modulator, both implemented in 0.18-μm CMOS technology. Simulation results indicate that these modulators save a significant amount of power consumption when their second integrator is replaced by MPI.     

Managing subthreshold leakage in charge-based analog circuits with low-V/sub TH/ transistors by analog T- switch (AT-switch) and super cut-off CMOS (SCCMOS)

The analog T-switch (AT-switch) scheme is introduced to suppress subthreshold-leakage problems in charge-based analog circuits such as switched capacitors and sample-and-hold circuits. A 0.5-V sigma-delta modulator is manufactured in a 0.15-/spl mu/m FD-SOI process with low V/sub TH/ of 0.1 V using the concept. The scheme is compared with another leakage-suppression scheme based on super cut-off CMOS (SCCMOS) and the conventional circuit which are also fabricated. The sigma-delta modulator based on AT-switch greatly improves 8.1-dB SNDR through reducing nonlinear leakage effects while the modulator based on SCCMOS improves the dynamic range rather than the SNDR by comparing with the conventional sigma-delta modulator.     

A 14-bit 80-kHz sigma-delta A/D converter: modeling, design andperformance evaluation

The development is described of a sigma-delta A/D (analog-to-digital) converter. Included is a brief overview of sigma-delta conversion. The A/D converter achieves an 88.5-dB dynamic range and a maximum signal-to-noise ratio of 81.5 dB. The harmonic distortion is negligible. This level of performance is about 10 dB higher than previously reported results for oversampled A/D converters in this frequency range. The analog modulator uses a double-integration switched-capacitor architecture with an oversampling rate of 10.24 MHz. Transconductance amplifiers having a 160-MHz f_t were developed for the integrators. The circuit is implemented in a 1.75-μm 5-V CMOS process. The analog circuitry occupies 2 mm² of silicon area and consumes 75 mW of power. Some of the difficult problems associated with evaluating the performance of sigma-delta converters are described. The design of a sigma-delta development and performance evaluation system is presented. This system includes a custom interface board linking the chip to a Sun workstation, and extensive digital signal processing and analysis software     

A digitally controlled constant envelope phase-shift modulator for low-power broad-band wireless applications

A low-power constant envelope phase-shift modulator is presented. The circuit switches the phase of a constant amplitude carrier at output according to the input digital data. Design issues and their impact on the performance of the modulator are discussed. A test chip was fabricated in a 0.18-/spl mu/m CMOS process. Experiment results verified the design principle of the modulator. The modulator consumes 2 mA and is suitable for low-power wireless applications like sensor network and personal area network. Since the circuit is implemented mostly by digital circuit, has broad-band frequency response, and supports high data rate, the modulator can be used at various wireless bands. The measured operating range of carrier frequency is 1.75 to 3.5 GHz, and the modulation data rate can go up to 500 Mb/s. In addition, the modulator can be modified to generate different modulations by digitally controlling both the phase and amplitude of the output signal from a phasor-combining circuit. Therefore, the modulator can potentially be used for software configurable radios.     

A time-domain noise-coupling technique for continuous-time sigma-delta modulators

In this paper, a time-domain noise-coupling technique based on the pulse width modulation is proposed. The time-domain quantization error is digitally extracted and shaped by an asynchronous digital filter. This digitally filtered quantization error is applied to the quantizer input to increase the modulator’s noise-shaping order. By using this technique in continuous-time sigma-delta modulators, the modulator’s shaping property is significantly enhanced. Comparative analytical calculations and simulation results are presented to estimate the performance of modulators employing the proposed quantizer. System-level simulation results reveal a (L + 2)th order noise-shaping capability of the proposed modulator while it employs only L analog integrators. The effects of main circuit non-idealities in the modulator’s performance are analytically investigated and confirmed by the simulation results.     

A cascaded sigma-delta pipeline A/D converter with 1.25 MHz signalbandwidth and 89 dB SNR

A low-noise multibit sigma-delta analog-to-digital converter (ADC) architecture suitable for operation at low oversampling ratios is presented. The ADC architecture uses an efficient high-resolution pipelined quantizer while avoiding loop stability degradation caused by pipeline latency. A 16-b implementation of the architecture, fabricated in a 0.6-μm CMOS process, cascades a second-order 5-b sigma-delta modulator with a four-stage 12-b pipelined ADC and operates at a low 8X oversampling ratio. Static and dynamic linearity of the integrated ADC are improved through the use of dynamic element matching techniques and the use of bootstrapped and clock-boosted input switches. The ADC operates at a 20 MHz clock rate and dissipates 550 mW with a 5 V/3 V analog/digital supply. It achieves an SNR of 89 dB over a 1.25-MHz signal bandwidth and a total harmonic distortion (THD) of -98 dB with a 100-kHz input signal     

碲镉汞e-APD 焦平面数字化读出电路设计

HgCdTe e-APD 工作于线性模式,通过内雪崩倍增效应将一个微弱的信号放大多个数量级。介绍了一个具有列共用ADC 制冷型(77 K)数字化混成式HgCdTe e-APD FPA 读出电路,可以应用于门控3D-LARDAR 成像,有主被动双模式成像功能。Sigma-delta 转换器比较适合于中规模128128 焦平面列共用ADC。调制器采用2-1 MASH 单比特结构,开关电容电路实现,数字抽取滤波器采用CIC 级联梳状滤波器。采用GLOBALFOUNDRIES 0.35 m CMOS 工艺,中心距100 m。设计了量化噪声抵消逻辑消除第一级调制器量化噪声,采用数字电路实现。CIC 抽取滤波器的每一级寄存器长度以方差为指标截尾,以降低硬件消耗。并且数字抽取滤波器工作电压降低到1.5 V,可以进一步降低功耗。仿真显示sigma-delta 转换器精度大于13 bit,功耗小于2.4mW,转换速率7.7 k Samples/s。     

A low-power triple-mode sigma-delta DAC for reconfigurable(WCDMA/TD-SCDMA/GSM) transmitters

A sigma-delta(Σ△) DAC with channel filtering for multi-standard wireless transmitters used in the software-defined-radio(SDR) system is presented.The conversion frequency,transfer function of the digital filter and theΣ△modulator,word-length of the IDAC and cut-off frequency of the analog reconstruction filter can be digitally programmed to satisfy specifications of WCDMA,TD-SCDMA and GSM standards.TheΣ△DAC fabricated in SMIC 0.13-μm CMOS process occupies a die area of 0.72 mm~2,while consuming 5.52/4.82/3.04 mW in WCDMA/TD-SCDMA/GSM mode from a single 1.2-V supply voltage.The measured SFDR is 62.8/60.1/ 75.5 dB for WCDMA/TD-SCDMA/GSM mode,respectively.     

14-bit 2.2-MS/s sigma-delta ADC's

This paper presents the design and test results of a fourth-order and sixth-order 14-bit 2.2-MS/s sigma-delta analog-to-digital converter (ADC). The analog modulator and digital decimator sections were implemented in a 0.35 μm CMOS double-poly triple-level metal 3.3-V process. The design objective for these ADC's was to achieve 85 dB signal-to-noise distortion ratio (SNDR) with less than 200 mW power dissipation. Both modulators employ a cascade sigma-delta topology. The fourth-order modulator consists of two cascaded second-order stages which include 1-bit and 5-bit quantizers, respectively. The sixth-order modulator has a 2-2-2 cascade structure and 1-bit quantizer at the end of each stage. An oversampling ratio of 24 was selected to give the best SNDR and power consumption with realizable gain-matching requirements between the analog and digital sections