一种基于sigma-delta调制的高效率低噪声降压式直流变换器

本论文在提高开关电源效率和降低噪声方面做了一些工作。在效率方面,提出了一个包含死区时间控制,断流模式控制以及栅宽调制功能的高效率功率管驱动电路。在控制回路中采用sigma-delta调制取代传统的PWM调制,降低了开关电源输出中与时钟有关的谐波噪声。本文在 0.35um CMOS工艺条件下实现了一个基于二阶sigma-delta调制的高效率低噪声DC-DC变换器。测试结果表明,此变换器能够达到93%的峰值效率,并且谐波噪声可以比使用PWM调制时低30dB。     

基于电容ESR和预测调制的DC-DC变换器双环控制策略研究

针对boost型DC-DC变换器,研究基于输出电容ESR纹波电压的预测调制控制策略.首先提出了无需电流采样,并采用输出电容ESR纹波电压的双环控制系统.其次,为了提升DC-DC变换器系统性能,引入了预测调制策略,可以提高变换器瞬态响应速度,减小由输入电压及负载变化引起的扰动.同时,为避免次谐波振荡,采用谷值后缘预测调制技术.最后,对该变换器进行Simulink仿真,结果表明,采用基于输出电容ESR纹波电压的双环控制,结合谷值后缘预测调制技术,可以稳定变换器输出电压,提升瞬态响应性能.该策略无需电流采样以及谐波补偿等模块,能够有效降低硬件成本.     

应用于PWM降压DC-DC变换器的高性能误差放大器

提出了一种应用于PWM降压型DC-DC变换器的高性能误差放大器。该误差放大器采用反馈结构,具有较大的动态范围,并可消除噪声影响,从而显著减小了DC-DC电源的纹波电压。另外,采用该误差放大器还有效地减小了电源启动时间。文中提出的误差放大器电路及PWM控制芯片的其他电路模块采用2.0μmBipolar工艺实现。仿真结果表明,误差放大器的开环和闭环增益分别为61dB和33dB,GBW为200MHz,SR为0.64V/μs。芯片测试结果表明,在输出电压为3.3V,负载电流为0.2A时,输出纹波电压的峰-峰值小于25mV。     

一种用于RF供电的混合结构DC-DC变换器

设计了一种基于0.13 μm CMOS工艺的混合结构DC-DC变换器。该变换器由Buck变换器和LDO串联组成。Buck变换器输出电压可根据LDO负载电流进行调节,能有效减小LDO损耗。在负载电流为20 mA时,可将整个变换器的效率提高10.5%。LDO采用片外电容补偿。高带宽误差放大器使LDO在DC~20 MHz范围内具有较高的电源抑制比。LDO对Buck变换器开关频率处的噪声抑制达-62 dB。整个电源具有较低的输出噪声,适于为RF电路供电。     

开关电容DC-DC变换器的最佳控制方法

在采用等效电量关系法对开关电容DC-DC变换器进行分析的基础上，研究了脉冲宽度调制（PWM）和频率调制（FM）的关系．得出开关电容DC-DC变换器的统一等效电路并指出：对开关电容DC-DC变换器，无论采取什么控制方法，都是能耗控制，因此级联低压差线性稳压器是一种最佳的控制方式．     

一种宽频应用的自适应计时电路

针对传统自适应导通时间控制DC-DC变换器工作频率范围窄的问题,提出了一种宽频应用的自适应计时电路。在锁相环调制DC-DC变换器的基础上,采用全CMOS电流乘法器,将振荡器的电流引入计时电路,使计时电路的中心频率跟随振荡器的基准频率变化,从而使自适应导通时间控制DC-DC变换器工作在较宽频率范围。基于0.18 μm BCD工艺对该自适应计时电路进行仿真验证。结果表明,应用该自适应计时电路的DC-DC变换器频率范围为0.27~3 MHz。     

矩阵变换器的间接空间矢量控制

矩阵变换器是一种新型的电力电子技术,具有能量可双向流通,可产生正弦输入电流和输出电压以及输入功率角可调等优点。文章基于矩阵变换器空间矢量调制法,分析虚拟整流器和逆变器的空间矢量调制,综合两个过程,得到一种直接的交-交变换器,利用MATLAB的仿真模块组建成矩阵变换器的仿真模型。仿真结果验证了空间矢量调制策略的有效性,矩阵变换器的优越性。     

矩阵变换器的过调制方法研究及其仿真

针对矩阵变换器最大电压传输比仅为0.866的问题,研究了基于矩阵变换器输出电压空间矢量的两种过调制策略。文中将空间矢量调制控制区域划分为线性区和过调制区,过调制区又分为过调制Ⅰ区和过调制Ⅱ区。在过调制区中应用过调制策略,即将输入电流空间矢量调制与输出电压空间矢量过调制方法相结合。在调制策略中根据电压调制系数不同,选用不同的参考电压矢量调整策略来实现过调制。在Matlab/Simulink下分别对过调制策略进行了仿真研究,仿真实验结果表明过调制策略能够有效地提高矩阵变换器的电压传输比。     

微波信号调制电路设计与实现

在智能微波开关的发射电路中,对高频微波信号采用了低频和中频两级调制的方法。为避免现场多对智能微波开关之间的相互干扰,首先用37～51 Hz分8级可调的低频高占空比方波信号调制21 kHz固定频率的中频信号,再用该信号调制10 GHz的高频微波信号。在信号调制的同时,用低频信号控制MOS管对高频微波模块的DC-DC供电电源反馈回路进行干预,使DC-DC电路工作于最佳状态,输出电压峰值平稳,避免了高频发射模块间歇式工作对电源电路输出的影响,提高了智能微波开关的测量精度和工作的可靠性。设计结果与理论分析结果比较接近,达到了设计要求。     

不连续导通模式PSM PT控制开关变换器

脉冲跳周期调制（Pulse Skip Modulation,PSM）采用ON/OFF控制对输出电压进行调整,提高了开关变换器的轻载效率,但存在输出电压纹波大的缺点。文中结合开关变换器的脉冲序列调制（Pulse Train,PT）控制与PSM技术,提出了开关变换器的PSM PT控制技术,其降低了输出电压的纹波,并使PT控制开关变换器在空载时能稳定工作。     

A low noise high efficiency buck DC-DC converter with sigma-delta modulation

Some research efforts to improve the efficiency and noise performance of buck DC-DC converters are explored.A carefully designed power MOSFET driver,including a dead time controller,discontinuous current mode(DCM) controller and gate width controller,is proposed to improve efficiency.Instead of PWM modulation, sigma-delta modulation is introduced into the feedback loop of the converter to move out the clock-referred harmonic spike.The proposed converter has been designed and fabricated by a 0.35μm CMOS process.Measured results show that the peak efficiency of the converter can reach 93%and sigma-delta modulation suppresses the harmonic spike by 30 dB over PWM modulation.     

Development of a new adaptive sigma-delta modulator scheme applied to multilevel inverter control

Interest in multilevel inverters is increasing in recent years, especially in high voltage applications. Traditional pulse width modulation (PWM) techniques can be applied to control this type of switched converter. However, it is necessary to adapt these techniques to the particularities of multilevel operation. As an alternative, other modulation techniques, such as sigma-delta modulation (SDM) can be used. In this case, it is possible to use advanced modulation techniques, such as adaptive modulation, to adapt the SDM to the multilevel operation. This article presents a new adaptive sigma-delta modulator that controls a five levels multilevel inverter. The algorithm that generates the sigma-delta signal is implemented in a field-programmable gate array (FPGA). This allows a very fast operation independent of the overall control circuit operation response. In addition, the FPGA can generate the control signals necessary to drive the power semiconductors in the power stage. The resulting modulator is simpler than the PWM version.     

一种采用斩波稳零技术的16位,96kHz带宽Σ-Δ AD转换器

介绍了一个16位精度Σ-Δ型模拟数字转换器.它由一个模拟的调制器和一个数字降采样滤波器组成.调制器采用了传统的单环两阶的结构,在第一阶调制器中采用了斩波稳零技术来消除电路的闪烁噪声.数字的降采样器包括多相梳状滤波器和波数字滤波器,功耗低,面积小.实验结果表明转换器获得了92dB的动态范围和96kHz的带宽.整个芯片由0.18μm六层金属CMOS工艺制造,芯片面积为2.68mm2,功率消耗仅为15.5mW.     

宽带∑-△A/D转换器中数字抽取滤波器的设计与验证

无线便携式移动设备与宽带intemet接入技术的发展,对∑-△A/D转化器的带宽要求越来越高。文中结合前端5阶宽带乏△调制器,设计了一种降低功耗与面积的数字抽取滤波器,应用于宽带高精度AD转换器中。MATLAB／simulink仿真结果表明,经过数字抽取滤波器滤波后信噪比为97．8dB,通带边界频率为1．8MHz,最小阻带衰减为70dB,通带内波纹0．0025dB,可满足设计要求。∑-△A/D转换器高精度、低功耗的优点,可广泛应用于中特种设备检验检测仪器仪表中。     

A fourth-order bandpass sigma-delta modulator

The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta (ΣΔ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio     

Improved low-distortion sigma-delta ADC with DWA for WLAN standards

An improved low distortion sigma-delta ADC (analog-to-digital converter) for wireless local area network standards is presented. A feed-forward MASH 2-2 multi-bit cascaded sigma-delta ADC is adopted; however, this work shows a much better performance than the ADCs which have been presented to date by adding a feedback factor in the second stage to improve the performance of the in-band SNDR (signal to noise and distortion ratio), using 4-bit ADCs in both stages to minimize the quantization noise. Data weighted averaging technology is therefore used to decrease the mismatch noise induced by the 4-bit DACs, which improves the SFDR (spurious free dynamic range) of the ADC.The modulator has been implemented by a 0.18μm CMOS process and operates at a single 1.8 V supply voltage.Experimental results show that for a 1.25 MHz @ -6 dBFS input signal at 160 MHz sampling frequency, the improved ADC with all non-idealities considered achieves a peak SNDR of 80.9 dB and an SFDR of 87 dB, and the effective number of bits is 13.15 bits.     

The Structure of Quantization Noise from Sigma-Delta Modulation

When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.     

A CMOS oversampling bandpass cascaded D/A converter with digital FIR and current-mode semi-digital filtering

An oversampling bandpass digital-to-analog converter has been designed so as to eliminate the carrier leak and in-band SNR degradation that accompany I and Q channel mismatch in wireless transmitters. The converter combines a cascaded noise-shaping sigma-delta (/spl Sigma//spl Delta/) modulator with digital finite impulse response (FIR) and mixed-signal semi-digital filters that attenuate out-of-band quantization noise. The performance of the converter in the presence of current source mismatch has been improved through the use of bandpass data weighted averaging. An experimental prototype of the converter, integrated in a 0.25-/spl mu/m CMOS technology, provides 83 dB of dynamic range for a 6.25-MHz signal band centered at 50 MHz, and suppresses out-of-band quantization noise by 38 dB.     

基于ΣΔ调制技术的CPFSK调制芯片设计

采用ΣΔ调制技术的小数分频频率合成器设计了CPFSK调制电路,对调制电路的原理以及噪声性能进行了细致的分析。芯片集成了2RC波形成形电路、三阶单级ΣΔ调制器、双模分频器、鉴频鉴相器、电荷泵和压控振荡器,在四电平2RC-CPFSK调制时,16kHz的带宽内可以实现25.6kbps的信息速率传输。电路采用0.35μm标准CMOS工艺实现,调节片外电感,芯片最高工作频率可以到200MHz。