The Performance of Acoustic-Optical $Q$-switched Mode-Locking 1.34 $mu$m Nd:GdVO$_{4}$ Laser

A diode-end-pumped $Q$ -switched mode-locking $hbox{Nd:GdVO}_{4}$ laser operating at 1.34 $mu{hbox {m}}$ with an acousto-optical (AO) Q-switch in a compact V-type cavity was realized in our experiment for the first time. When the AO Q-switch repetition rate was 10 kHz, the maximum average output power of 750 mW and the pulse energy of 75 $muhbox{J}$ were obtained at the maximum incident pump power of 9 W. The mode-locking modulation depth of about 100% was obtained at certain pump power over the threshold. The mode-locked pulse inside in the $Q$-switched pulse had a repetition rate of 341 MHz, and its average pulsewidth was estimated to be about 350 ps. A developed rate equation model for the $Q$ -switched and mode-locked lasers with an AO Q-switch were proposed by using the hyperbolic secant functional methods. The results of numerical calculations of the rate equations were in good agreement with the experimental results.      

Compact Variable ${rm TE}$-${rm TM}$ Polarization Splitter Based on Simplified Coherent Coupling in Lithium Niobate

A compact-sized electrically tunable ${rm TE}$- ${rm TM}$ mode splitter composed of a mode converter and an asymmetric Y-branch structure is presented. The asymmetric Y-branch consists of a straight and a bent waveguides to split two polarization modes based on the mode-sorting effect. To shorten the device length, a simplified coherently coupled-bending structure is utilized for the bent waveguide. Experimental results show that the device length is reduced about 52%, extinction ratios of both ${rm TE}$ and ${rm TM}$ modes are higher than 25 dB, yet the applied voltage is not significantly increased.      

Impacts of $hbox{N}_{2}$ and $hbox{NH}_{3}$ Plasma Surface Treatments on High-Performance LTPS-TFT With High-$kappa$ Gate Dielectric

Low-temperature polycrystalline-silicon thin-film transistors (LTPS-TFTs) with high- $kappa$ gate dielectrics and plasma surface treatments are demonstrated for the first time. Significant field-effect mobility $mu_{rm FE}$ improvements of $sim$86.0% and 112.5% are observed for LTPS-TFTs with $hbox{HfO}_{2}$ gate dielectric after $hbox{N}_{2}$ and $ hbox{NH}_{3}$ plasma surface treatments, respectively. In addition, the $hbox{N}_{2}$ and $ hbox{NH}_{3}$ plasma surface treatments can also reduce surface roughness scattering to enhance the field-effect mobility $mu_{rm FE}$ at high gate bias voltage $V_{G}$, resulting in 217.0% and 219.6% improvements in driving current, respectively. As a result, high-performance LTPS-TFT with low threshold voltage $V_{rm TH} sim hbox{0.33} hbox{V}$, excellent subthreshold swing S.S. $sim$0.156 V/decade, and high field-effect mobility $mu_{rm FE} sim hbox{62.02} hbox{cm}^{2}/hbox{V} cdot hbox{s}$ would be suitable for the application of system-on-panel.      

Experimental Demonstration of Deeply-Etched SiO$_{2}$ Ridge Optical Waveguides and Devices

Deeply-etched ${hbox{SiO}}_{2}$ optical ridge waveguides are fabricated and characterized. A detailed discussion of the fabrication process (especially for the deep etching process) is presented. The measured propagation losses for the fabricated waveguides with different core widths range from $0.33sim {hbox {0.81}}~{hbox {dB}}/{hbox {mm}}$. The loss is mainly caused by the scattering due to the sidewall roughness. The losses in bending sections are also characterized, which show the possibility of realizing a small bending radius (several tens of microns). 1 $,times {rm N}$ ( ${rm N}=2$, 4, 8) multimode interference couplers based on the deeply-etched ${hbox{SiO}}_{2}$ ridge waveguide are also fabricated and show fairly good performances.      

1580-V–40-$hbox{m}Omegacdot hbox{cm}^{2}$ Double-RESURF MOSFETs on 4H-SiC $(hbox{000}bar{hbox{1}})$

Double-reduced-surface-field (RESURF) MOSFETs with $hbox{N}_{2}hbox{O}$ -grown oxides have been fabricated on the 4H-SiC $(hbox{000} bar{hbox{1}})$ face. The double-RESURF structure is effective in reducing the drift resistance, as well as in increasing the breakdown voltage. In addition, by utilizing the 4H-SiC $(hbox{000}bar{hbox{1}})$ face, the channel mobility can be increased to over 30 $hbox{cm}^{2}/hbox{V}cdothbox{s}$, and hence, the channel resistance is decreased. As a result, the fabricated MOSFETs on 4H-SiC $( hbox{000}bar{hbox{1}})$ have demonstrated a high breakdown voltage $(V_{B})$ of 1580 V and a low on-resistance $(R_{rm ON})$ of 40 $hbox{m}Omega cdothbox{cm}^{2}$. The figure-of-merit $(V_{B}^{2}/R_{rm ON})$ of the fabricated device has reached 62 $hbox{MW/cm}^{2}$, which is the highest value among any lateral MOSFETs and is more than ten times higher than the “Si limit.”      

Performance Improvement of N-Type $hbox{TiO}_{x}$ Active-Channel TFTs Grown by Low-Temperature Plasma-Enhanced ALD

We report on performance improvement of $n$-type oxide–semiconductor thin-film transistors (TFTs) based on $hbox{TiO}_{x}$ active channels grown at 250 $^{circ}hbox{C}$ by plasma-enhanced atomic layer deposition. TFTs with as-grown $hbox{TiO}_{x}$ films exhibited the saturation mobility $(mu_{rm sat})$ as high as 3.2 $hbox{cm}^{2}/hbox{V}cdothbox{s}$ but suffered from the low on–off ratio $(I_{rm ON}/I_{rm OFF})$ of $hbox{2.0} times hbox{10}^{2}$. $hbox{N}_{2}hbox{O}$ plasma treatment was then attempted to improve $I_{rm ON}/I_{rm OFF}$. Upon treatment, the $hbox{TiO}_{x}$ TFTs exhibited $I_{rm ON}/I_{rm OFF}$ of $hbox{4.7} times hbox{10}^{5}$ and $mu_{rm sat}$ of 1.64 $hbox{cm}^{2}/hbox{V}cdothbox{s}$, showing a much improved performance balance and, thus, demonstrating their potentials for a wide variety of applications such as backplane technology in active-matrix displays and radio-frequency identification tags.      

A Center-Offset Polycrystalline-Silicon Thin-Film Transistor With ${rm n}^{+}$ Amorphous-Silicon Contacts

We have studied a bottom-gate polycrystalline-silicon thin-film transistor (poly-Si TFT) with amorphous-silicon (a-Si) ${rm n}^{+}$ contacts and center-offset gated structure, where intrinsic poly-Si is used in the center-offset region. The fabrication process is compatible with the conventional a-Si TFT with addition of thermal annealing for crystallization of a-Si. The bottom-gate poly-Si TFT with a 5-$muhbox{m}$ offset length exhibited a field-effect mobility of 18.3 $hbox{cm}^{2}/hbox{V} cdot hbox{s}$ and minimum OFF-state current of $hbox{2.79} times hbox{10}^{-12} hbox{A}/muhbox{m}$ at $V_{rm ds} = hbox{5} hbox{V}$. The leakage currents are two orders of magnitude lower than those of a nonoffset TFT with mobility drop from 23.8 to 18.3 $hbox{cm}^{2}/ hbox{V} cdot hbox{s}$.      

$hbox{TiN/ZrO}_{2}$/Ti/Al Metal–Insulator–Metal Capacitors With Subnanometer CET Using ALD-Deposited $hbox{ZrO}_{2}$ for DRAM Applications

We provide the first report of the structural and electrical properties of $hbox{TiN/ZrO}_{2}$/Ti/Al metal–insulator–metal capacitor structures, where the $hbox{ZrO}_{2}$ thin film (7–8 nm) is deposited by ALD using the new zirconium precursor ZrD-04, also known as Bis(methylcyclopentadienyl) methoxymethyl. Measured capacitance–voltage ($C$– $V$) and current–voltage ( $I$–$V$) characteristics are reported for premetallization rapid thermal annealing (RTP) in $hbox{N}_{2}$ for 60 s at 400 $^{circ}hbox{C}$, 500 $^{circ}hbox{C}$, or 600 $^{ circ}hbox{C}$. For the RTP at 400 $^{circ}hbox{C}$ , we find very low leakage current densities on the order of nanoamperes per square centimeter at a gate voltage of 1 V and low capacitance equivalent thickness values of $sim$ 0.9 nm at a gate voltage of 0 V. The dielectric constant of $ hbox{ZrO}_{2}$ is 31 $pm$ 2 after RTP treatment at 400 $^{circ}hbox{C}$.      

A Comparative NBTI Study of $hbox{HfO}_{2}$, $hbox{HfSiO}_{x}$, and SiON p-MOSFETs Using UF-OTF $I_{rm DLIN}$ Technique

The time, temperature, and oxide-field dependence of negative-bias temperature instability is studied in $hbox{HfO}_{2}/hbox{TiN}$, $ hbox{HfSiO}_{x}/hbox{TiN}$, and SiON/poly-Si p-MOSFETs using ultrafast on-the-fly $I_{rm DLIN}$ technique capable of providing measured degradation from very short (approximately microseconds) to long stress time. Similar to rapid thermal nitrided oxide (RTNO) SiON, $hbox{HfO}_{2}$ devices show very high temperature-independent degradation at short (submilliseconds) stress time, not observed for plasma nitrided oxide (PNO) SiON and $hbox{HfSiO}_{x}$ devices. $hbox{HfSiO}_{x}$ shows lower overall degradation, higher long-time power-law exponent, field acceleration, and temperature activation as compared to $hbox{HfO}_{2}$, which are similar to the differences between PNO and RTNO SiON devices, respectively. The difference between $ hbox{HfSiO}_{x}$ and $hbox{HfO}_{2}$ can be attributed to differences in N density in the $hbox{SiO}_{2}$ IL of these devices.      

A 67 dBm $OIP_{3}$ Multistacked Junction Varactor

A multistacked varactor is presented for ultra-linear tunable radio frequency applications. The varactor elements are applied in anti-series configuration and are characterized by an “exponential” $C$- $V _{R}$ relationship. Third-order intermodulation ($IM_{3}$) is cancelled through proper harmonic loading of the terminals of the anti-series configuration. Multiple stacking is used to further increase the power handling and to minimize the remaining fifth-order distortion. The measured output intercept point ($OIP_{3}$ ) at 2 GHz is $ > 67~{rm dBm}$ for modulated signals up to 10 MHz bandwidth, while providing a capacitance tuning ratio of 3:1 with an average quality factor of 40 and maximum control voltage of 10 V.      

180$^{circ}$ and 90$^{circ}$ Phase Shifting Networks With an Octave Bandwidth and Small Phase Errors

A new phase shifting network for both 180 $^{circ}$ and 90 $^{circ}$ phase shift with small phase errors over an octave bandwidth is presented. The theoretical bandwidth is 67% for the 180$^{circ}$ phase bit and 86% for the 90$^{circ}$ phase bit when phase errors are $pm 2^{circ}$. The proposed topology consists of a bandpass filter (BPF) branch, consisting of a LC resonator and two shunt quarter-wavelength transmission lines (TLs), and a reference TL. A theoretical analysis is provided and scalable parameters are listed for both phase bits. To test the theory, phase shifting networks from 1 GHz to 3 GHz were designed. The measured phase errors of the 180$^{circ}$ and the 90$^{circ}$ phase bit are $pm 3.5^{circ}$ and $pm 2.5^{circ}$ over a bandwidth of 73% and 102% while the return losses are better than 18 dB and 12 dB, respectively.      

High-Performance $hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}$ -Channel MOSFETs With High-$kappa$ Gate Dielectrics and $alpha$-Si Passivation

Long and short buried-channel $hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}$ MOSFETs with and without $alpha$-Si passivation are demonstrated. Devices with $alpha$-Si passivation show much higher transconductance and an effective peak mobility of 3810 $hbox{cm}^{2}/ hbox{V} cdot hbox{s}$. Short-channel MOSFETs with a gate length of 160 nm display a current of 825 $muhbox{A}/muhbox{m}$ at $V_{g} - V_{t} = hbox{1.6} hbox{V}$ and peak transconductance of 715 $muhbox{S}/muhbox{m}$. In addition, the virtual source velocity extracted from the short-channel devices is 1.4–1.7 times higher than that of Si MOSFETs. These results indicate that the high-performance $hbox{In}_{0.7}hbox{Ga}_{0.3} hbox{As}$-channel MOSFETs passivated by an $alpha$ -Si layer are promising candidates for advanced post-Si CMOS applications.      

High-Performance Poly-Silicon TFTs Using a High-$k$ $hbox{PrTiO}_{3}$ Gate Dielectric

In this letter, a polycrystalline-silicon thin-film transistor (poly-Si TFT) with a high- $k$ $hbox{PrTiO}_{3}$ gate dielectric is proposed for the first time. Compared to TFTs with a $hbox{Pr}_{2}hbox{O}_{3}$ gate dielectric, the electrical characteristics of poly-Si TFTs with a $hbox{PrTiO}_{3}$ gate dielectric can be significantly improved, such as lower threshold voltage, smaller subthreshold swing, higher $I_{rm on}/I_{rm off}$ current ratio, and larger field-effect mobility, even without any hydrogenation treatment. These improvements can be attributed to the high gate capacitance density and low grain-boundary trap state. All of these results suggest that the poly-Si TFT with a high- $k$ $hbox{PrTiO}_{3}$ gate dielectric is a good candidate for high-speed and low-power display driving circuit applications in flat-panel displays.      

$S$ - and $C$ -Band Ultra-Compact Phase Shifters Based on All-Pass Networks

Ultra-compact phase shifters are presented. The proposed phase-shifting circuits utilize the lumped element all-pass networks. The transition frequency of the all-pass network, which determines the size of the circuit, is set to be much higher than the operating frequency. This results in a significantly small chip size of the phase shifter. To verify this methodology, 5-bit phase shifters have been fabricated in the $S$ - and $C$ -band. The $S$ -band phase shifter, with a chip size of 1.87 mm $,times,$0.87 mm (1.63 mm $^{2}$), has achieved an insertion loss of ${hbox{6.1 dB}} pm {hbox{0.6 dB}}$ and rms phase-shift error of less than 2.8$^{circ}$ in 10% bandwidth. The $C$ -band phase shifter, with a chip size of 1.72 mm $,times,$0.81 mm (1.37 mm $^{2}$), has demonstrated an insertion loss of 5.7 dB $pm$ 0.8 dB and rms phase-shift error of less than 2.3 $^{circ}$ in 10% bandwidth.      

Characterization and Modeling of RF-Performance $(f_{T})$ Fluctuation in MOSFETs

The fluctuation of RF performance (particularly for $f_{T}$ : cutoff frequency) in the transistors fabricated by 90-nm CMOS technology has been investigated. The modeling for $f_{T}$ fluctuation is well fitted with the measurement data within approximately 1% error. Low-$V_{t}$ transistors (fabricated by lower doping concentration in the channel) show higher $f_{T}$ fluctuation than normal transistors. Such a higher $f_{T}$ fluctuation results from $C_{rm gg}$ (total gate capacitance) variation rather than $g_{m}$ variation. More detailed analysis shows that $C_{rm gs} + C_{rm gb}$ (charges in the channel and the bulk) are predominant factors over $C_{rm gd}$ (charges in LDD/halo region) to determine $C_{rm gg}$ fluctuation.      

Zn$_{1 - x}$Mg$_{x}$ O Homojunction-Based Ultraviolet Photodetector

Zn$_{1 - {x}}$ Mg$_{x}$ O p-n photodiodes were fabricated on (0001) sapphire substrates using a pulsed laser deposition technique with different Mg contents. Ti–Au and Ni–Au metals deposited using vacuum evaporation were used as n-type and p-type contacts, respectively. The X-ray diffraction analysis showed the Zn$_{1 - {x}}$Mg$_{x}$O double layers have a single phase hexagonal wurtzite structure. The optical bandgap of Zn$_{1 - {x}}$Mg$_{x}$O films has been tuned from 3.27 to 4.26 eV by increasing the Mg content ${x} =0.0$ to ${x}=0.34$. Correspondingly, the cutoff wavelength of the resultant detectors varies from 380 to 284 nm. Zn$_{1 - {x}}$Mg$_{x}$O p-n photodiodes with different Mg contents exhibit very good performance, with a very low dark current (${≪}$ 20 pA) at the bias voltage of 10 V. The ultraviolet to visible rejection ratio is more than three orders of magnitude.      

Multiwavelength $Q$-switched Laser by Incorporating a LiNbO$_{3}$ Phase Modulator in Fabry–PÉrot Cavity

In this letter, we present a simple and compact laser cavity that can be used for $Q$-switching and multiwavelength oscillation. It is shown that a LiNbO $_{3}$ phase modulator with relatively low driven voltage inserted into a Fabry–PÉrot cavity can act simultaneously as an effective component for suppressing the homogeneous line broadening, switching the $Q$ -value of the laser cavity, and a polarizer. Multiwavelength operation of Yb-doped fiber laser is achieved by phase modulation. $Q$-switching is achieved due to the residual intensity modulation of the phase modulator, and the pulse performance is also impacted by the phase modulation amplitude. Three stable wavelengths with identical wavelength spacing of 3.3 nm and pulsed laser of 0.2 $mu$J per pulse energy at the repetition rate of 55.8 kHz are demonstrated. The full-width at half-maximum pulse duration is of 2 $mu$s, and the polarization extinction ratio is $>$23 dB.      

A 5-GHz CMOS Type-II PLL With Low $K_{rm VCO}$ and Extended Fine-Tuning Range

A 5-GHz dual-path integer-$N$ Type-II phase-locked loop (PLL) uses an LC voltage-controlled oscillator and softly switched varactors in an overlapped digitally controlled integral path to allow a large fine-tuning range of approximately 160 MHz while realizing a low susceptibility to noise and spurs by using a low $K_{rm VCO}$ of 3.2 MHz/V. The reference spur level is less than $-$70 dBc with a 1-MHz reference frequency and a total loop-filter capacitance of 26 pF. The measured phase noise is $-$75 and $-$115 dBc/Hz at 10-kHz and 1-MHz offsets, respectively, using a loop bandwidth of approximately 30 kHz. This 0.25-${hbox{mm}}^{2}$ PLL is fabricated in a 90-nm digital CMOS process and consumes 11 mW from a 1.2-V supply.      

A Sub-100 $mu{rm W}$ Ku-Band RTD VCO for Extremely Low Power Applications

This letter presents the microwave performance of a sub-100 $mu{rm W}$ Ku-band differential-mode resonant tunneling diode (RTD)-based voltage controlled oscillator (VCO) with an extremely low power consumption of 87 $mu{rm W}$ using an InP-based RTD/HBT MMIC technology. In order to achieve the extremely low-power Ku-band RTD VCO, the device size of RTD is scaled down to $0.6times 0.6 mu{rm m}^{2}$. The obtained dc power consumption of 87 $mu{rm W}$ is found to be only 1/18 of the conventional-type MMIC VCOs reported in the Ku-band. The fabricated RTD VCO has a phase noise of $-$100.3 dBc/Hz at 1 MHz offset frequency and a tuning range of 140 MHz with the figure-of-merit (FOM) of $-$194.3 dBc/Hz.      

The Electrical and Interfacial Properties of Metal-High-$kappa$ Oxide-Semiconductor Field-Effect Transistors With $hbox{LaAlO}_{3}$ Gate Dielectric

$hbox{LaAlO}_{3}$ is a promising candidate for gate dielectric of future VLSI devices. In this letter, n-channel metal–oxide–semiconductor field-effect transistors with $hbox{LaAlO}_{3}$ gate dielectric were fabricated, and the electron mobility degradation mechanisms were studied. The leakage current density is $hbox{7.6} times hbox{10}^{-5} hbox{A/cm}^{2}$ at $-!$ 1 V. The dielectric constant is 17.5. The surface-recombination velocity, the minority-carrier lifetime, and the effective capture cross section of surface states were extracted from gated-diode measurement. The rate of threshold voltage change with temperature $(Delta V_{T} / Delta T)$ from 11 K to 400 K is $-!$ 1.51 mV/K, and the electron mobility limited by surface roughness is proportional to $E_{rm eff}^{-0.66}$.