利用S2C Stratix IV TAI LM进行SoC原型验证的方法学

FPGA原型验证是一种在FPGA上搭建SoC和ASIC设计原型的方法学,可以方便的进行硬件验证和早期软件开发。此方法学也称为ASIC原型验证或SoC原型验证。在FPGA上搭建SoC和ASIC设计原型已经成为验证硬件设计和早期软硬件协同设计的主流方法学。现在的设计者都已经认识到了FPGA原型验证的重要性,但是设计者在进行FPGA原型验证的时候常常要面临许多挑战和困难.     

FPGA配置过程监控系统设计

为了解决系统上电后FPGA应用程序配置失败的问题,设计了FPGA配置过程监控系统。深入分析了FPGA配置的工作流程,阐述了FPGA配置监控系统的核心监控电路、监控软件的设计思想、代码实现及仿真验证过程。最后,用MATLAB对实验数据进行分析处理,得出了FPGA器件的配置失败率和失败曲线以验证设计的可行性和优越性。实验结果表明:利用该系统可以使FPGA配置成功率达到100%,比传统设计方法的FPGA配置成功率提高了0.041%,满足了系统对FPGA配置应用程序成功率高、可靠性强的要求。应用结果显示,FPGA配置监控系统能及时监测出FPGA配置过程所出现的异常,判断分析出问题的根源,最终使FPGA应用程序在系统一次性上电后配置成功。     

基于NiosⅡ的SD卡驱动程序开发

提出一种在FPGA Nios Ⅱ软核处理器下SD卡驱动设计的方法.采用Altera公司的FPGA可编程逻辑器件,构建了Nios Ⅱ软核处理器平台,并在此之上实现了SD卡的驱动设计.实验结果表明:设计提高了FPGA系统的设计灵活度,并有效地控制了FPGA的资源利用率.     

多通道EOPDH/EOS网桥芯片的FPGA设计

本文介绍了一种EOPDH/EOS网桥芯片的FPGA设计,具体说明了本网桥芯片的FPGA电路设计。将许多复杂的功能集中在FPGA上实现,既可以使得设计目标快速产品化,并可以根据市场要求的变化及时修改电路设计,大大体现出了采用FPGA设计的及时性和灵活性。本设计最终采用了XilinxSpartan-6得以验证实现。     

ASIC设计自动化最新工具—FPGA开发系统

本文介绍了ASIC设计自动化最新工具——FPGA开发系统的软、硬件支撑环境,FPGA的概况,特点和基本结构,FPGA系列器件和工作频率以及在微机FPGA开发系统上如何进行ASIC电路的设计,最后给出一个设计实例的流程。     

多通道EOPDH/EOS网桥芯片的FPGA设计

本文介绍了一种EOPDH/EOS网桥芯片的FPGA设计,具体说明了本网桥芯片的FPGA电路设计。将许多复杂的功能集中在FPGA上实现,既可以使得设计目标快速产品化,并可以根据市场要求的变化及时修改电路设计,大大体现出了采用FPGA设计的及时性和灵活性。本设计最终采用了XilinxSpartan-6得以验证实现。     

基于FPGA的高速电路设计方法的研究

本文针对影响系统数据处理速度的两个主要方面，给出了用FPGA设计高速电路系统的设计方法和技巧，并用设计实例在ACTEL FPGA上予以验证，对基于FPGA高速电路系统的设计具有普遍的指导意义。     

基于NiosII的SD卡驱动程序开发

提出一种在FPGANiosⅡ软核处理器下SD卡驱动设计的方法。采用Altera公司的FPGA可编程逻辑器件．构建了NiosH软核处理器平台,并在此之上实现了SD卡的驱动设计。实验结果表明：设计提高了FPGA系统的设计灵活度,并有效地控制了FPGA的资源利用率。     

从ASIC到FPGA的转换系统时钟设计方案

基于原型验证的需要和FPGA对ASIC市场的取代．越来越多的ASIC设计需要移植到FPGA＆来实现。然而,ASIC与FPGA在内部结构上差异很大,尤其是时钟结构,在移植过程中需要特别注意。文中以Xilinx公司的Vitrex-4 FPGA为例,对比了ASIC与FPGA的时钟结构,给出了门控时钟、生成时钟和多FPGA时钟同步在设计转换过程中的处理方法。     

利用S2C Stratix Ⅳ TAI LM进行SoC原型验证的方法学

FPGA原型验证是一种在FPGA上搭建SoC和ASIC设计原型的方法学,可以方便的进行硬件验证和早期软件开发。此方法学也称为ASIC原型验证或SoC原型验证。在FPGA上搭建SoC和ASIC设计原型已经成为验证硬件设计和早期软硬件协同设     

A visualization-based approach for bump-pad/IO-ball placement and routing in flip-chip/BGA technology

The routing problem in area array integrated circuit (IC) packaging has become an extremely complex problem in the realm of high I/O count IC packages. With the advent of flip-chip and ball grid array (BGA) technology to meet the current demands of smaller size and high wiring densities, the routing problem lies in the core of electronic design automation process. In this paper, we describe an intuitive computer visualization-based approach for placement and routing of bonding pads that would result in low manufacturing costs and smaller component size compared to conventional approaches. This novel approach is an extension of "balls shifted as needed" method for I/O ball placement in BGA package enabling single-layer board-level routing for any I/O count. The I/O ball/pad layout and routing designs along with results are presented for two routing layers with the inclusion of vias in the design. This routing scheme is shown to be easily extensible to accommodate more practical multilayer routing and can be incorporated in current electronic design automation (EDA) computer-aided design (CAD) tools to offer an integrated routing solution for area array chip-package-board codesign. The results show that different trace routing patterns lead to different area requirements for same number of I/Os. This has led to the formulation of new design paradigms which are presented in the paper for smaller component size.     

Reliability and wireability optimizations for chip placement on multichip modules

The chip placement problem of multichip module (MCM) designs is to map the chips properly to the chip sites on the MCM substrate. Chip placement affects not only the thermal characteristics of an MCM but also routing efficiency, which translates directly into manufacturability, performance, and cost. This paper presents a solution methodology for the optimal placement problem considering both thermal and routing design objectives simultaneously. The coupling is achieved through use of a hybrid-force model that is a combination of the traditional interconnection-force model and a novel thermal-force model. The placement procedure can be used as a design tool to place chips and then determine the tradeoffs which can be made in placing for reliability and wireability. Experiments on five examples including three benchmarks show that the present algorithm yields very high-quality results.     

一种新的基于查找表的时钟性能驱动的增量式布局算法

提出了一种新的时钟性能驱动的增量式布局算法,它针对目前工业界较为流行的标准单元布局,应用查找表模型来计算延迟.由于在布局阶段较早地考虑到时钟信息,可以通过调整单元位置,更有利于后续的有用偏差时钟布线和偏差优化问题.来自于工业界的测试用例结果表明,该算法可以有效地改善合理偏差范围的分布,而对电路的其它性能影响很小.     

一种中频接收电路的版图设计

利用Cadence版图设计工具采用B300工艺对一种中频接收电路芯片的版图设计实例,阐述了模拟集成电路版图的设计过程,论述了包括单元库建立、布局、布线、设计规则检查（DRC）和版图对照原理图检查（LVS）等在内的设计步骤以及进行每一步骤的具体方法,尤其对布局和布线这样的关键步骤进行了重点讨论。最后给出了完整的芯片版图。     

IO单元自动排布算法IOAP

提出了一种应用于芯片物理设计过程中IO单元自动排布的新算法。IO单元排布是芯片物理设计过程中长期依赖经验的环节。IO单元排布的优化对布线,电源网格和设计收敛性的优化有很大贡献。文章重点研究边缘IO单元排布,提出了IO单元自动排布算法(IOAP)。此算法及其相关软件直接应用于视频解码芯片和无线传感器网络处理器芯片(已流片成功)的物理设计流程中。结果表明,IOAP有效改善了芯片的电源网格,时序和布线结果,减少了布线努力,提高了设计收敛性。     

Routing and wavelength assignment vs. wavelength converter placement in all-optical networks

Blocking has been the key performance index in the design of an all-optical network. Existing research demonstrates that an effective routing and wavelength assignment strategy and a proper wavelength converter placement algorithm are the two primary vehicles for improving the blocking performance. However, these two issues have largely been investigated separately in that the existing RWA algorithms have seldom considered the presence of wavelength conversion, while the wavelength converter placement algorithms have largely assumed that a static routing and random wavelength assignment algorithm is employed. The main objective of this article is to present some strong evidence that these two issues need to be considered jointly, and call for the reexamination of both RWA and wavelength converter placement.     

ALGA: Automated layout generator for analog CMOS circuits

A computer-aided design (CAD) system called ALGA for an analog circuit layout is presented. The main contribution of this paper is to construct a weight graph that represents the topological connectivity of a given analog circuit. By using the weight graph, some efficient techniques can be designed to avoid devices mismatch and place all devices according to the device size constraints. Moreover, an algorithm is presented to perform the device placement step and propose an effective approach to reduce noise coupling in the routing step. A design method has been implemented in several Complementary Metal Oxide Semiconductor (CMOS) analog circuits. It is seen that the proposed system can generate good analog circuit design.     

移动数字电视调谐芯片中I2C接口电路设计

采用TSMC 0.13μm CMOS工艺,对多模多频段移动数字电视调谐芯片内I2C接口电路进行设计和验证.采用数字集成电路设计流程,详细验证接口电路的时序.布局布线后得到较为理想的版图面积与功耗.版图后仿真结果表明,在100 MHz时钟下,电路满足I2C协议的时序要求,可广泛应用于移动数字电视调谐芯片中.