An integrated mass flow sensor with on-chip CMOS interfacecircuitry

A multielement monolithic mass flow sensor which developed for possible use in automotive and industrial process control applications is reported. The chip illustrates the use of a common microstructure (a thin dielectric window/diaphragm) for the simultaneous measurement of flow velocity (rate), flow direction, gas type, and pressure. These transducers are merged with on-chip interface electronics to amplify and multiplex the transducer signals, control on-chip actuators, perform self-test, reduce the number of external leads required, and demonstrate process compatibility with a p-well CMOS process. The on-chip circuitry also implements a bandgap sensor for the measurement of ambient temperature. Thus, the chip simultaneously monitors all parameters needed for the computation of true mass flow, requires only ten external leads, and delivers high-level buffered output signals     

A CMOS delta-sigma true RMS converter

Conventionally, monolithic electronics true rms converters are constructed by bipolar circuitry. This paper describes a new architecture based on delta-sigma (ΔΣ) modulation to realize a low-cost rms converter in CMOS technologies, especially intended for handheld digital multimeters. The signal-to-quantization noise ratio as well as transfer characteristics of this architecture have been deduced to obtain initial design parameters. The use of an indirect charge transfer technique makes the converter gain depend only on an on-chip capacitor ratio, reducing gain drift and offering good gain accuracy. Measured results show that this converter achieves a signal-to-noise ratio of 88 dB and a relative error of ±0.2% for arbitrary inputs with a signal crest factor up to three. The signal bandwidth exceeds 50 kHz, and the full-scale input range is greater than 0.4 V_rms. Without trimming and calibration, this converter has an absolute gain error less than ±0.4%. This chip is fabricated in a 0.8-μm double-poly, double-metal CMOS process and occupies active area of 1 mm ²     

Single-unit neural recording with active microelectrode arrays

This paper discusses the single-unit recording characteristics of microelectrode arrays containing on-chip signal processing circuitry. Probes buffered using on-chip unity-gain operational amplifiers provide an output resistance of 200 ohm with an input-referred noise of 11-muV root-mean-square (rms) (100 Hz-10 kHz). Simultaneous in vivo recordings from single neurons using buffered and unbuffered (passive) iridium recording sites separated by less than 20 microm have shown that the use of on-chip circuitry does not significantly degrade system noise. Single-unit neural activity has also been studied using probes containing closed-loop preamplifiers having a voltage gain of 40 dB and a bandwidth of 13 kHz, and several input dc-baseline stabilization techniques have been evaluated. Low-noise in vivo recordings with a multiplexed probe have been demonstrated for the first time using an external asymmetrical clock running at 200 kHz. The multiplexed system adds less than 8-muV rms of noise to the recorded signals, suppressing the 5-V clock transitions to less than 2 ppm.     

CMOS active pixel image sensors for highly integrated imagingsystems

A family of CMOS-based active pixel image sensors (APSs) that are inherently compatible with the integration of on-chip signal processing circuitry is reported. The image sensors were fabricated using commercially available 2-μm CMOS processes and both p-well and n-well implementations were explored. The arrays feature random access, 5-V operation and transistor-transistor logic (TTL) compatible control signals. Methods of on-chip suppression of fixed pattern noise to less than 0.1% saturation are demonstrated. The baseline design achieved a pixel size of 40 μm×40 μm with 26% fill-factor. Array sizes of 28×28 elements and 128×128 elements have been fabricated and characterized. Typical output conversion gain is 3.7 μV/e^- for the p-well devices and 6.5 μV/e^- for the n-well devices. Input referred read noise of 28 e^- rms corresponding to a dynamic range of 76 dB was achieved. Characterization of various photogate pixel designs and a photodiode design is reported. Photoresponse variations for different pixel designs are discussed     

An implantable multielectrode array with on-chip signal processing

This active probe can be used for the long-term recording of extracellular neural biopotentials and as a basis for closed-loop neural prostheses. The probe incorporates on-chip circuitry for amplifying, multiplexing, and buffering neural signals recorded from ten recording electrodes spaced 100-/spl mu/m apart. It requires only three leads and operates from a single 5-V supply. On-chip self-test circuitry for testing electrode impedance levels is provided. The on-chip circuitry is fabricated in a die area of 1.3 mm/SUP 2/ using 6-/spl mu/m LOCOS enhancement-depletion NMOS technology, and dissipates 5 mW of power. The probe is 4.7 mm long and 15 /spl mu/m thick, and has a shank which tapers from 160 /spl mu/m near the base to less than 15 /spl mu/m near the tip.     

A wireless implantable multichannel digital neural recording systemfor a micromachined sieve electrode

This paper reports the development of an implantable, fully integrated, multichannel peripheral neural recording system, which is powered and controlled using an RF telemetry link. The system allows recording of ±500 μV neural signals from axons regenerated through a micromachined silicon sieve electrode. These signals are amplified using on-chip 100 Hz to 3.1 kHz bandlimited amplifiers, multiplexed, and digitized with a low-power (<2 mW), moderate speed (8 μs/b) current-mode 8-b analog-to-digital converter (ADC). The digitized signal is transmitted to the outside world using a passive RF telemetry link. The circuit is implemented using a bipolar CMOS process. The signal processing CMOS circuitry dissipates only 10 mW of power from a 5-V supply while operating at 2 MHz and consumes 4×4 mm² of area. The overall circuit including the RF interface circuitry contains over 5000 transistors, dissipates 90 mW of power, and consumes 4×6 mm² of area     

An NMOS Microcomputer Peripheral Interface Unit Incorporating an Analog-to-Digital Converter

A peripheral interface unit for a microcomputer control system fabricated by a standard n-channel silicon-gate enhancement/depletion MOS process is described. This unit can accept analog and digital inputs, generate pulse outputs, and multiply. The analog input capability is made possible by an on-chip A/D converter using a constant slope approach with an external capacitor. This converter can perform a 10 bit conversion in 5 ms and has an input voltage range of 0-5 V with only one 8 V power supply for the analog circuits. The die area required by the converter is small and the precision analog specifications needed for the process and devices are few. The die area of the converter is 3 mm/sup 2/, out of a total unit area of 35 mm/sup 2/.     

An On-chip Calibration Technique for Reducing Supply Voltage Sensitivity in Ring Oscillators

A technique for reducing the supply voltage sensitivity of a ring oscillator using on-chip calibration is described. A 1-V 0.13-mum CMOS PLL demonstrates robust performance against VCO supply noise over operating frequencies of 0.5 to 2 GHz. In the presence of a 10-mV 1-MHz VCO supply noise, the measured rms jitter of the proposed PLL with on-chip calibration is 3.95 ps at a 1.4-GHz operating frequency, while a conventional design measures 8.22 ps rms jitter. For 10-MHz VCO supply noise, the measured rms jitter is improved from 16.8 ps to 3.97 ps. The total power consumption of the PLL is 9.6 mW at 1.4 GHz, and the combined core die area of the PLL and the calibration circuitry is 0.064 mm²     

A monolithic 10-bit A/D using I/SUP 2/L and LWT thin-film resistors

Describes the function, circuit details, and performance of a monolithic 10-bit A/D converter. The converter is a successive approximation type using linear compatible I/SUP 2/L for the SAR. The converter is completely self-contained, including both clock and voltage reference. Biasing is arranged to take advantage of naturally occurring interfaces in the circuitry, simplifying the overall circuit in comparison to discrete or hybrid approaches. The processing also includes on-chip thin-film resistors which are laser-wafer-trimmed (LWR) for overall accuracy and temperature stability. The finished circuits operate with no missing codes over the -55/spl deg/ to +125/spl deg/C temperature range.     

An implantable CMOS circuit interface for multiplexedmicroelectrode recording arrays

A second-generation multichannel probe designed for measuring single-unit activity in neural structures is described. The probe includes CMOS circuitry for electronically positioning the recording sites with respect to the active neurons and for amplifying and multiplexing the recorded signals. The probe selects eight active recording sites from among 32 on the probe shank using a static input channel selector. The neural signals on the selected channels are then amplified and multiplexed to the outside world. The probe offers a typical AC gain of 300 (15 Hz to 7 kHz), a DC gain of 0.3, and an equivalent input noise of 15 μV rms. Operating from a single 5-V supply, the probe dissipates 2.5 mW of power and implements channel selection, self-testing, data output, and initialization using three external leads. The probe is realized using 12 masks in a high-yield single-sided dissolved wafer process with a 3-μm feature size for the circuitry and a 3-μm pitch on the electrode shanks     

A low-jitter wide-range skew-calibrated dual-loop DLL usingantifuse circuitry for high-speed DRAM

This paper describes a delay-locked loop (DLL) circuit having two advancements, a dual-loop operation for a wide lock range and programmable replica delays using antifuse circuitry and internal voltage generator for a post-package skew calibration. The dual-loop operation uses information from the initial time difference between reference clock and internal clock to select one of the differential internal loops. This increases the lock range of the DLL to the lower frequency. In addition, incorporation of the programmable replica delay using antifuse circuitry and the internal voltage generator allows for the elimination of skews between external clock and internal clock that occur from on-chip and off-chip variations after the package process. The proposed DLL, fabricated on 0.16-μm DRAM process, operates over the wide range of 42-400 MHz with 2.3-V power supply. The measured results show 43-ps peak-to-peak jitter and 4.71-ps rms jitter consuming 52 mW at 400 MHz     

A monolithic current-mode CMOS DC-DC converter with on-chip current-sensing technique

A monolithic current-mode CMOS DC-DC converter with integrated power switches and a novel on-chip current sensor for feedback control is presented in this paper. With the proposed accurate on-chip current sensor, the sensed inductor current, combined with the internal ramp signal, can be used for current-mode DC-DC converter feedback control. In addition, no external components and no extra I/O pins are needed for the current-mode controller. The DC-DC converter has been fabricated with a standard 0.6-/spl mu/m CMOS process. The measured absolute error between the sensed signal and the inductor current is less than 4%. Experimental results show that this converter with on-chip current sensor can operate from 300 kHz to 1 MHz with supply voltage from 3 to 5.2 V, which is suitable for single-cell lithium-ion battery supply applications. The output ripple voltage is about 20 mV with a 10-/spl mu/F off-chip capacitor and 4.7-/spl mu/H off-chip inductor. The power efficiency is over 80% for load current from 50 to 450 mA.     

A dual differential charge-coupled analog delay device

A dual differential charge-coupled analog device providing signal delays of 24 and 48 elements has been designed for sampled data analog signal processing applications. The aim of this design was to eliminate some of the disadvantages that have been associated with previous charge-coupled devices (CCD's). These include clock pickup, thermally generated dc offsets, and complex external control and amplification circuitry. The device has an input strobing circuit and an on-chip output amplifier. With a clock frequency of 8 kHz and a 400-mV rms input signal, the total harmonic distortion was below 0.2 percent and the signal-to-noise ratio was better than 70 dB with a 4-kHz bandwidth. The device gain was 6 dB and a gain variation of 0.2 dB was observed over a temperature range of 0 to 55°C.     

A single-ended 12-bit 20 Msample/s self-calibrating pipeline A/Dconverter

This paper describes a fully monolithic 12-bit, 20 Msample/s, A/D converter. A power dissipation of 250 mW from a single 5 V supply is achieved using a radix=2 pipeline architecture. Linearity and full-scale errors are removed through self-calibration and digital correction with on-chip circuitry. A novel single-ended to differential sample and hold stage is proven to have very good single-ended input performance up to the Nyquist frequency. The total silicon area is 3.2×3.1 mm² in a 0.7 μm CMOS process. Several circuit techniques used in this design together with experimental results are presented     

A low-noise demultiplexing system for active multichannelmicroelectrode arrays

This paper reports a low-noise demultiplexing system capable of reconstructing multichannel single-unit neural signals derived from multiplexed microelectrode arrays. The overall multiplexing-demultiplexing system realizes ten channels, a per-channel gain of 68 dB, a bandwidth from 100 Hz to 6 kHz, and an equivalent noise level (referred to the probe input) of 13 microV rms. It provides for signaling over the power supply to allow control of on-chip probe functions such as self-testing. The interchannel crosstalk is less than 3%, and switching noise is suppressed by blanking the transition intervals. The 200 kHz probe sample clock is tracked automatically over a range from 150 to 250 kHz. Neural signals as low as 20 microV (typically 640 microV at the demultiplexing system input) can be reconstructed. The overall system organization is compatible with the demultiplexing of as many as 40 time-multiplexed electrode channels from a single probe data line.     

A gigasample/second 5-b ADC with on-chip track and hold based on anindustrial 1 μm GaAs MESFET E/D process

To enhance the dynamic accuracy of high-speed A/D conversion, a 5-b flash converter with on-chip track and hold circuitry (T&H) was developed. The design is based on TriQuint's commercial 1 μm GaAs E/D MESFET process. Dynamic characterization was performed up to 1 gigasample/second (GS/s). An accuracy of 4.4 effective bits even at 1 GS/s with full Nyquist input was achieved. A comparison showing the accuracy with T&H in operation and in tracking-only mode is given. The outstanding performance is due to a carefully designed and the use of differential source-coupled FET logic (SCFL) in the converter     

Analog VLSI Circuit Implementation of an Adaptive Neuromorphic Olfaction Chip

In this paper, we present the analog circuit design and implementation of the components of an adaptive neuromorphic olfaction chip. A chemical sensor array employing carbon black composite sensing materials with integrated signal processing circuitry forms the front end of the chip. The sensor signal processing circuitry includes a dc offset cancellation circuit to ameliorate loss of measurement range associated with chemical sensors. Drawing inspiration from biological olfactory systems, the analog circuits used to process signals from the on-chip odor sensors make use of temporal "spiking" signals to act as carriers of odor information. An on-chip spike time dependent learning circuit is integrated to dynamically adapt weights for odor detection and classification. All the component subsystems implemented on chip have been successfully tested in silicon     

Demonstration of a 311-GHz Fundamental Oscillator Using InP HBT Technology

In this paper, a sub-millimeter-wave HBT oscillator is reported. The oscillator uses a single-emitter 0.3 m15 m InP HBT device with maximum frequency of oscillation greater than 500 GHz. The passive components of the oscillator are realized in a two metal process with benzocyclobutene used as the primary transmission line dielectric. The oscillator is implemented in a common base topology due to its inherent instability. The design includes an on-chip resonator, output matching circuitry, and injection locking port. A free-running frequency of 311.6 GHz has been measured by down-converting the signal. Additionally, injection locking has been successfully demonstrated with up to 17.8 dB of injection-locking gain. This is the first fundamental HBT oscillator operating above 300 GHz.     

Ge-blade damascene process for post-CMOS integration of nano-mechanical resonators

A process is demonstrated for fabrication of high-frequency mechanical resonators applicable for on-chip radio-frequency communication. This Ge-blade damascene process (GBDP) provides ultranarrow lateral gaps using lithographically defined sacrificial Ge blades (high-aspect-ratio Ge features). The use of Ge as the sacrificial material eliminates the need for a hydrogen fluoride etch process to release the mechanical structures, and, hence, simplifies the integration of microelectromechanical (MEMS) with CMOS circuitry. Polycrystalline silicon-germanium (poly-SiGe) is used as the structural material in order to keep the thermal budget low (maximum temperature 425 /spl deg/C), so as to be compatible with CMOS metallization stacks. A 24-MHz double-ended tuning fork resonator was successfully fabricated using the GBDP.