Simulation of high-speed interconnects

With the rapid developments in very large-scale integration (VLSI) technology, design and computer-aided design (CAD) techniques, at both the chip and package level, the operating frequencies are fast reaching the vicinity of gigahertz and switching times are getting to the subnanosecond levels. The ever increasing quest for high-speed applications is placing higher demands on interconnect performance and highlighted the previously negligible effects of interconnects such as ringing, signal delay, distortion, reflections, and crosstalk. In this review paper various high-speed interconnect effects are briefly discussed. In addition, recent advances in transmission line macromodeling techniques are presented. Also, simulation of high-speed interconnects using model-reduction-based algorithms is discussed in detail     

Characteristic analysis of coupled HTS interconnects withtwo-dimensional FDTD

In this work, the frequency-dependent RLGC parameters of high-speed coupled high T_c superconductor (HTS) interconnects are extracted with a two-dimensional (2-D) FDTD algorithm. The response signals of an HTS interconnect circuit and a normal Al interconnect circuit are simulated and compared, showing that not only the signal dispersion, delay, and magnitude decay of HTS interconnects are smaller than that of Al interconnects, the crosstalk of HTS interconnects is much smaller, too     

Crosstalk modeling for coupled RLC interconnects with application to shield insertion

On-chip interconnect delay and crosstalk noise have become significant bottlenecks in the performance and signal integrity of deep submicrometer VLSI circuits. A crosstalk noise model for both identical and nonidentical coupled resistance-inductance-capacitance (RLC) interconnects is developed based on a decoupling technique exhibiting an average error of 6.8% as compared to SPICE. The crosstalk noise model, together with a proposed concept of effective mutual inductance, is applied to evaluate the effectiveness of the shielding technique.     

高速VLSI电路中传输线瞬态响应的灵敏度分析

本文用特征法分析计算高速VLSI电路中传输线的瞬态响应相对于传输线参数和终端负载参数的灵敏度,从而为VLSI电路信号连接线的优化设计提供了一个有用工具。传输线的终端负载可以为非线性,传输的信号形状可以任意,这是该方法区别于基于数值拉氏逆变换的灵敏度分析方法的最大特点。     

Analysis of lossy multiconductor transmission lines using theasymptotic waveform evaluation technique

A method is described for the transient analysis of lossy coupled transmission line networks with nonlinear elements. The method combines the asymptotic waveform evaluation technique with a piecewise decomposition algorithm. Two to three orders of magnitude speedup can be achieved relative to previously published methods with comparable accuracy. The method is useful for delay and crosstalk simulation of high speed VLSI interconnects     

An optical holographic backplane interconnect system

An optical holographic backplane interconnect system capable of high-speed information transmission between optoelectronic transmitter/receiver boards is described. Using conjugate pairs of transmission gratings in a folded reflection geometry, a practical method of insulating the interconnect system from wavelength variations due to temperature or power fluctuations can be achieved. The final demonstration unit was developed in a fully packaged form and has the potential for reconfigurable interconnects and may serve as a testbed for a variety of interconnect networks and hardware protocols     

Analysis and optimization of coplanar RLC lines for GSI global interconnection

Compact physical models are derived for the delay and crosstalk of on-chip coplanar transmission lines, which are used in state-of-the-art high-speed microprocessors. These lines are mainly used for long global interconnects that are relatively thick and wide and have prominent inductive effects. The models are then used to optimize the design of coplanar global interconnects.     

Through-silicon-via insertion for performance optimization in three-dimensional integrated circuits

Through-silicon-via (TSV) interconnect is one of the main technologies for three-dimensional integrated circuits production (3-D ICs). Based on a parasitic parameters extraction model, first order expressions for the TSV resistances, inductances, and capacitance as functions of physical dimension and material characteristic are derived. Analyzing the impact of TSV size and placement on the interconnect timing performance and signal integrity, this paper presents an approach for TSV insertion in 3D ICs to minimize the propagation delay with consideration to signal reflection. Simulation results in multiple heterogeneous 3D architectures demonstrate that our approach in generally can result in a 49.96% improvement in average delay, a 62.28% decrease in the reflection coefficient, and the optimization for delay can be more effective for higher non-uniform inter-plane interconnects. The proposed approach can be integrated into the TSV-aware design and optimization tools for 3-D circuits to enhance system performance.     

Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing

Every new VLSI technology generation has resulted in interconnects increasingly limiting the performance, area, and power dissipation of new processors. Subsequently, it is necessary to devise efficient interconnect design techniques to reduce the impact of VLSI interconnects on overall system design. New optimizations of a wave-pipelined multiplexed (WPM) interconnect routing circuit are described in this paper. These WPM circuits can be used with current interconnect repeater circuits to further reduce interconnect delay, interconnect area, transistor area, and/or power dissipation. For example, new area constrained WPM circuit optimizations illustrate that the interconnect circuit power can be reduced by 26% or the interconnect performance can be improved by 74%. Moreover, in both these cases, because a significant number of repeaters are eliminated, the transistor area can reduce by 41% or 29%, respectively. Finally, the tolerance of WPM circuits to crosstalk noise, power supply noise, clock skew, and manufacturing variations is also presented. This study of tolerance levels defines the conditions under which the WPM circuit will function correctly, and it is shown in this paper for the first time that WPM circuits are robust enough to operate with variability that can be encountered in deep submicrometer technologies.     

Sensitivity analysis of multiconductor transmission lines andoptimization for high-speed interconnect circuit design

Sensitivity analysis of multiconductor transmission lines is derived from a new, all-purpose multi-conductor transmission line model in both frequency domain and time domain. Computer implementation of this new model as well as the sensitivity analysis has been completed. It enables efficient, accurate simulations of interconnect circuit responses as well as sensitivity analysis with respect to both electrical and physical transmission line parameters. By applying sensitivity analysis to high-speed interconnect circuit design, design variables are optimized to achieve simultaneous minimization of crosstalk, delays and reflections at desired nodes in the circuit without violating any indispensable design rules. Numerical examples are presented to demonstrate the validity of the proposed sensitivity analysis and illustrate its application to the optimization of high-speed interconnect circuit design     

A new on-chip interconnect crosstalk model and experimentalverification for CMOS VLSI circuit design

A new, simple closed-form crosstalk model is proposed. The model is based on a lumped configuration but effectively includes the distributed properties of interconnect capacitance and resistance. CMOS device nonlinearity is simply approximated as a linear device. That is, the CMOS gate is modeled as a resistance at the driving port and a capacitance at a driven port. Interconnects are modeled as effective resistances and capacitances to match the distributed transmission behavior. The new model shows excellent agreement with SPICE simulations. Further, while existing models do not support the multiple line crosstalk behaviors, our model can be generalized to multiple lines. That is, unlike previously published work, even if the geometrical structures are not identical, it can accurately predict crosstalk. The model is experimentally verified with 0.35-μm CMOS process-based interconnect test structures. The new model can be readily implemented in CAD analysis tools. This model can be used to predict the signal integrity for high-speed and high-density VLSI circuit design     

On Modeling of Parallel Repeater-Insertion Methodologies for SoC Interconnects

Parallel repeaters are proven to outperform serial repeaters in terms of delay, power and silicon area when regenerating signals in system-on-chip (SoC) interconnects. In order to avoid fundamental weaknesses associated with previously published parallel repeater-insertion models, this paper presents a new mathematical modeling for parallel repeater-insertion methodologies in SoC interconnects. The proposed methodology is based on modeling the repeater pull-down resistance in parallel with the interconnect. Also, to account for the effect of interconnect inductance, two moments were used in the transfer function, as opposed to previous Elmore delay models which consider only one moment for RC interconnects. A direct consequence of this new type of modeling is an increased challenge in the mathematical modeling of interconnects. HSpice electrical and C++/MATLAB simulations are conducted to assess the performance of the proposed optimization methodology using a 0.25-$mu$m CMOS technology. Simulation results show that this repeater-insertion methodology can be used to optimize SoC interconnects in terms of propagation delay, and provide VLSI/SoC designers with optimal design parameters, such as the type as well as the position and size of repeaters to be used for interconnect regeneration, faster than with conventional HSpice simulations.      

Crosstalk and transient analyses of high-speed interconnects andpackages

A multiconductor interconnect is modeled using resistors and linear-dependent current and voltage sources. The analysis of a high-speed circuit including lossy interconnection buses is then reduced to simulation of the circuit together with the equivalent circuits of the interconnects. The authors present a new method for the crosstalk and transient analysis of lossy interconnects with arbitrary termination circuits. In order to analyze an interconnect containing N signal conductors, they derive closed-form formulas to determine its transfer functions, and they apply the inverse Fourier transform to obtain its time-domain pulse response functions. Two types of equivalent circuit models can be formulated once the pulse response functions of the interconnect are found. The circuit schematics of the models depend on the number of the signal conductors, irrespective of the physical parameters of the interconnect. These models are compatible with standard circuit simulation tools since they consist of linear resistive networks and linear-dependent sources only. Two example circuits are studied to examine the accuracy and efficiency of the method     

Permalloy loaded transmission lines for high-speed interconnect applications

The mutual inductance and self-inductance of global interconnects are important but difficult to extract and model in deep submicrometer very large scale integration (VLSI) designs. The absence of effective mutual magnetic field shielding limits the maximum unbuffered interconnect line length. In this paper, we propose and demonstrate that permalloy-loaded transmission lines can be used for high-speed interconnect applications to overcome these limitations. Permalloy films were incorporated into planar transmission lines using a CMOS-compatible process. The line characteristics show that eddy-current effects are the limiting factors for the high-frequency permalloy applications when ferromagnetic resonance are restrained through geometry design. Patterning permalloy films effectively extends their application to above 20 GHz. The line characteristic impedances are about /spl sim/90 /spl Omega/. Under 50 mA dc current biases, the line parameters did not change much. Moreover, the patterned permalloy reduces the magnetic field coupling between two adjacent transmission lines by about 10 dB in our design. The demonstrated operation frequency range, current carrying capability and magnetic field shielding properties indicate that the permalloy loaded lines are suitable for high-speed interconnect applications in CMOS technologies.     

Bus encoder design for reduced crosstalk,power and area in coupled VLSI interconnects

This research work presents a novel circuit for simultaneous reduction of power, crosstalk and area using bus encoding technique in RC modeled VLSI interconnect. Bus-invert method is used to reduce inter-wire coupling, which is actually responsible for crosstalk, delay and power dissipation in coupled interconnects. The proposed method focuses on simplified and improved encoder circuit for 4, 8 and 16 coupled lines. In past, the researchers developed encoders that usually focused on minimizing power dissipation and/or crosstalk, thereby paying heavy penalty in terms of chip area. However, the proposed encoder and decoder while significantly reducing crosstalk demonstrates an overall reduction of power dissipation by 68.76% through drastically limiting switching activity. Furthermore, while reducing the complexity, chip area and transistor count of the circuit is reduced by more than 57%.     

Electromagnetic analysis of multiconductor losses and dispersion in high-speed interconnects

A self-consistent electromagnetic analysis of multiconductor transmission lines is presented for high-speed, high-density MMIC's and VLSI interconnects. In contrast to classical approach, this analysis handles the multiconductor as normal dielectric with high conductivity in electromagnetic simulation. Therefore, dispersion and loss effects can exactly be described in this model. Examples of interconnect circuits with up to four conductors are analyzed for dispersion and frequency-dependent losses. Propagation characteristics of multimode along symmetrical and asymmetrical multiconductor are obtained. Some inherent influences of losses on high-density interconnects and physical dependence of these effects are also discussed.     

超大规模集成电路中互连结构的逻辑模型

本文首次提出一种新观点，超大规模集成电路中互连结构的等效模型应具有层次性，对于底层的电路设计，应将互加看作一种具有分布参数的多端口网络，而对于高层次的模块设计，则应将互连看作一种逻辑元件，基于这种观点，本文提出了一种表格型的逻辑模型，它可以将互连产生的三种主要负效应：串扰、延迟和信号变形人武部考虑在内。     

2001 needs for multi-level interconnect technology

Looks at the materials and thermal alternatives for scaled, next-century VLSI/ULSI interconnects. It is shown that ad hoc executions of programs to calculate interconnect parameters for VLSI/ULSI design and analysis are too time-consuming to be practical. The tool used in this study to model a hypothetical interconnect system was Hewlett Packard's HTVE (HP Interconnect Value Extractor)