SiC衬底上栅长70 nm fT / fmax >160 GHz的InAlN/GaN HEMTs器件

在SiC衬底上制备了InAlN/GaN 高电子迁移率晶体管（HEMTs）,并进行了表征。为提高器件性能,综合采用了多种技术,包括高电子浓度,70 nm T型栅,小的欧姆接触电阻和小源漏间距。制备的InAlN/GaN器件在栅偏压为1 V时得到的最大饱和漏电流密度为1.65 A/mm,最大峰值跨导为382 mS/mm。70 nm栅长器件的电流增益截止频率fT和最大振荡频率fmax分别为162 GHz和176 GHz。     

Germanium FETs and capacitors with rare earth CeO2/HfO2 gates

Long channel Ge FETs and capacitors with CeO₂/HfO₂/TiN gates were fabricated by photolithography and gate wet etch. Rare earth CeO₂ in direct contact with Ge was used as a passivating layer producing lowest D_it values in the mid 10¹¹ eV⁻¹ cm⁻² range. HfO₂ cap reduces leakage and improves equivalent oxide thickness scaling of the whole gate stack. The p-FETs show exceptionally high I_ON/I_OFF ratio 10⁶, mainly due to low OFF current, and peak channel mobility around 80 cm²/V s. The n-FETs, although functional, show inferior performance producing ON currents an order of magnitude lower compared to p-FETs.     

Schottky barrier SOI-MOSFETs with high-k La(2)O(3)/ZrO(2) gate dielectrics

Schottky barrier SOI-MOSFETs incorporating a La₂O₃/ZrO₂ high-k dielectric stack deposited by atomic layer deposition are investigated. As the La precursor tris(N,N′-diisopropylformamidinato) lanthanum is used. As a mid-gap metal gate electrode TiN capped with W is applied. Processing parameters are optimized to issue a minimal overall thermal budget and an improved device performance. As a result, the overall thermal load was kept as low as 350, 400 or 500 °C. Excellent drive current properties, low interface trap densities of 1.9 × 10¹¹ eV⁻¹ cm⁻², a low subthreshold slope of 70-80 mV/decade, and an I_ON/I_OFF current ratio greater than 2 × 10⁶ are obtained.     

Simulation of InGaAs subchannel DG-HEMTs for analogue/RF applications

The paper reports on the influence of a barrier thickness and gate length on the various device parameters of double gate high electron mobility transistors (DG-HEMTs). The DC and RF performance of the device have been studied by varying the barrier thickness from 1 to 5 nm and gate length from 10 to 150 nm, respectively. As the gate length is reduced below 50 nm regime, the barrier thickness plays an important role in device performance. Scaling the gate length leads to higher transconductance and high frequency operations with the expense of poor short channel effects. The authors claim that the 30-nm gate length, mole fractions tuned In_0.53Ga_0.47As/In_0.7Ga_0.3As/In_0.53Ga_0.47As subchannel DG-HEMT with optimised device structure of 2 nm In_0.48Al_0.52As barrier layer show a peak g_m of 3.09 mS/µm, V_T of 0.29 V, I_ON/I_OFF ratio of 2.24 × 10⁵, subthreshold slope ~73 mV/decade and drain induced barrier lowering ~68 mV/V with f_T and f_max of 776 and 905 GHz at V_ds = 0.5 V is achieved. These superior performances are achieved by using double-gate architecture with reduced gate to channel distance.     

N2O treatment enhancement-mode InAlN/GaN HEMTs with HfZrO2 High-k insulator

A normally-off InAlN/GaN MIS-HEMT with HfZrO₂ gate insulator was realized and investigated. By using N₂O plasma treatment beneath the gate region, 13 nm InAlN Schottky layer was oxidized to AlON_x + 4 nm InAlN Schottky layer. The strong polarization induced carriers in traditional InAlN/GaN 2 DEG quantum well was reduced for enhancement-mode operation. High-k thin film HfZrO₂ was used for gate insulator of E-mode device to further suppress gate leakage current and enhance device gate operation range. The maximum drain current of E-mode InAlN/GaN MIS-HEMT was 498 mA/mm and this value was higher than previous published InAlN/GaN E-mode devices. The measurement results of low-frequency noise also concluded that the low frequency noise is attributed to the mobility fluctuation of the channel and N₂O plasma treatment did not increase fluctuation center of gate electrode.     

Characteristics of Al/sub 2/O/sub 3//AllnN /GaN MOSHEMT

InAlN/GaN is a new heterostructure system for HEMTs with thin barrier layers and high channel current densities well above 1 A/mm. To improve the leakage characteristics of such thin-barrier devices, AlInN/GaN MOSHEMT devices with a 11 nm InAlN barrier and an additional 5 nm Al₂O₃ barrier (deposited by ALD) were fabricated and evaluated. Gate leakage in reverse direction could be reduced by one order of magnitude and the forward gate voltage swing increased to 4 V without gate breakdown. Compared to HEMT devices of similar geometry, no degradation of the current gain cutoff frequency was observed. The results showed that InAlN/GaN FETs with high channel current densities can be realised with low gate leakage characteristics and high structural aspect ratio by insertion of a thin Al₂O ₃ gate dielectric layer     

Study of gate dielectric permittivity variation with different equivalent oxide thickness on channel engineered deep sub-micrometer n-MOSFET device for mixed signal applications

The impact of high permittivity gate dielectrics with different equivalent oxide thickness (EOT) for conventional, low and high tilt angle halo implants on the performance of 100 nm n-MOSFETs device is studied using device simulator Synopsys ISE-TCAD. In this paper, we systematically increase the value of gate dielectric (3.9-50) and investigate its effects on conventional, low angle of tilt (10^o) and high angle of tilt (50^o) halo implants for different device parameters of 100 nm n-MOSFETs using two different EOT viz. 1.5 nm and 2.0 nm. The impact of gate dielectric permittivity along with the different angles of halo implants on short channel performance contributing to the DIBL, the subthreshold swing, I_ON/I_OFF ratio, and the threshold voltage V_T are studied for two different EOT thicknesses. The device has been investigated for digital performance parameters like the variation of substrate-body voltage on DIBL, I_OFF, I_ON and the threshold voltage V_T for sub 100 nm technology generation. It has also been investigated for analog performance like trans-conductance generation factor (gm/I_D) and overall gain (gmR₀).     

基于再生长欧姆接触工艺的220 GHz InAlN/GaN 场效应晶体管

本文在蓝宝石衬底上研制了具有高电流增益截止频率(f_T)的InAlN/GaN异质结场效应晶体管 (HFETs)。基于MOCVD外延n -GaN欧姆接触工艺实现了器件尺寸的缩小,有效源漏间距(L_sd)缩小至600 nm。此外,采用自对准工艺制备了50 nm直栅。由于器件尺寸的缩小,V_gs= 1 V下器件最大饱和电流(I_ds)达到2.11 A/mm,峰值跨导达到609 mS/mm。小信号测试表明,器件f_T达到220 GHz、最大振荡频率(f_max)达到48 GHz。据我们所知,该f_T值是目前国内InAlN/GaN HFETs器件报道的最高结果。     

NBTI and hot carrier effect of Schottky-barrier p-MOSFETs

The experimental investigation of NBTI and hot carrier induced device degradation in Pt-silicided Schottky-barrier p-MOSFETs has been performed. The investigations on the threshold voltage shifts, the degradation of inverse subthreshold slope, and the decrease of I_ON/I_OFF ratio have been carried out using the modulation of Schottky-barrier height and width. After NBTI and hot carrier stress, the decrease of I_ON could be explained by the lower hole tunneling current through the more increased Schottky-barrier height and the increased I_OFF could be explained by the increase of the amount of electron thermal emission and tunneling through thinner Schottky-barrier into the near drain. After hot carrier stress, it is observed that the threshold voltage shifts to more negative values for all stress gate voltages and the drain current is decreased. The device degradation is more significant as the stress gate voltage decreases.     

Modeling and simulation of enhancement mode p-GaN Gate AlGaN/GaN HEMT for RF circuit switch applications

An enhancement mode p-GaN gate AlGaN/GaN HEMT is proposed and a physics based virtual source charge model with Landauer approach for electron transport has been developed using Verilog-A and simulated using Cadence Spectre, in order to predict device characteristics such as threshold voltage, drain current and gate capacitance. The drain current model incorporates important physical effects such as velocity saturation, short channel effects like DIBL (drain induced barrier lowering), channel length modulation (CLM), and mobility degradation due to self-heating. The predicted I_d-V_ds, I_d-V_gs, and C-V characteristics show an excellent agreement with the experimental data for both drain current and capacitance which validate the model. The developed model was then utilized to design and simulate a single-pole single-throw (SPST) RF switch.     

Comparative study of AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors with Al2O3 and HfO2 gate oxide

AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors (MOSHFETs) with Al₂O₃ gate oxide which was deposited by atomic layer deposition (ALD) were fabricated and their performance was then compared with that of AlGaN/GaN MOSHFETs with HfO₂ gate oxide. The capacitance (C)-voltage (V) curve of the Al₂O₃/GaN MOS diodes showed a lower hysteresis and lower interface state density than the C-V curve of the HfO₂/GaN diodes, indicating better quality of the Al₂O₃/GaN interface. The saturation of drain current in the I_D-V_GS relation of the Al₂O₃ AlGaN/GaN MOSHFETs was not as pronounced as that of the HfO₂ AlGaN/GaN MOSHFETs. The gate leakage current of the Al₂O₃ MOSHFET was five to eight orders of magnitude smaller than that of the HfO₂ MOSHFETs.     

Organic memristive devices based on silver nanoparticles and DNA

A novel organic memory device ‘Al/silver nanoparticles-deoxyribonucleic acid-cetyltrimethylammonium Bromide/ITO’ (Al/Ag NPs–DNA–CTMA/ITO) was fabricated. The measured I–V curve of the device exhibits unipolar switching. The conductivity and the memristive characteristics are significantly improved by the introduction of Ag nanoparticles, but with a poor stability. Better stability is achieved by annealing the device, which also changes the switching characteristic from unipolar to bipolar. As the annealing temperature is raised, the switching voltage first decreases and then increases, while the current I_RESET first increases and then decreases. The range of the optimal annealing temperature is from 383 K to 403 K and the maximum ON/OFF current ratio (I_ON/I_OFF) can reach 10⁴. The switching voltage, the current, and I_ON/I_OFF all increase with the applied voltage amplitude, and V_SET and I_ON/I_OFF obey a quadratic and Boltzmann relationship, respectively.     

High mobility compressive strained Si0.5Ge0.5 quantum well p-MOSFETs with higher-k/metal-gate

Strained SiGe quantum well p-MOSFETs with LaLuO₃ higher-k dielectric were fabricated and characterized. The strained Si/strained Si_0.5Ge_0.5/strained SOI heterostructure transistors showed good output and transfer characteristics with an I_on/I_off ratio of 10⁵. The extracted hole mobility shows an enhancement of about 2.5 times over Si universal hole mobility and no degradation compared to HfO₂ or even SiO₂ gate dielectric devices.     

Investigation of scalability of In0.7Ga0.3As quantum well field effect transistor (QWFET) architecture for logic applications

In this paper, the scalability of In_0.7Ga_0.3As QWFET is investigated using two-dimensional numerical drift-diffusion simulation. Numerical drift-diffusion simulations were calibrated using experimental results on short-channel In_0.7Ga_0.3As QWFETs [7] to include the effects of velocity overshoot. Logic figures of merit (sub-threshold slope, saturated threshold voltage, drain induced barrier lowering, I_ON/I_OFF ratio over a specified gate swing, effective injection velocity and intrinsic switching delay) extracted from the numerical simulations are in excellent agreement with the experimental data. Three alternate QWFET device architectures are proposed and thoroughly investigated for 15 nm node and beyond logic applications. Amongst them, double-gate In_0.7Ga_0.3As QWFET shows the best scalability in terms of logic figures of merit, thus making it an ideal candidate for the design and demonstration of the ultimate scaled transistor.     

Optimisation of electrical parameters in Fe DS-SBTFET and its application as a digital inverter

In this paper, the design geometry of Ferroelectric Dopant Segregated Schottky Barrier Tunnel Field Effect Transistor (Fe DS-SBTFET) has been proposed. Various electrical properties such as I_ON/I_OFF ratio and subthreshold swing (SS) of the proposed design have been premeditated and compared with different asymmetric structures. The impact of various types and thickness of buffer on the ferroelectric properties have been analysed. The device has been optimised for various doping concentrations and lengths of the dopant segregated layer (DSL). The digital applications of the proposed device in terms of complementary TFET digital inverter circuit have been studied. The transient characteristics and the delay parameters by considering various ferroelectric thicknesses have been analysed. Moreover, the transfer characteristics and electric field have been explored in the presence and absence of ferroelectric layer to obtain a better insight into the ferroelectric properties of the proposed structure. The electric field at the tunnelling junction is enhanced by the presence of ferroelectric layer which improves the ON current. The structure with ferroelectric thickness of 6 nm provides the best I_ON/I_OFF ratio of 1.2 × 10⁹ and SS of 14 mV/dec.     

具有低电压、低“迟滞效应”的C60薄膜晶体管

以C60为激活层,同时以聚合物/高K氧化物双绝缘层结构研制了N型有机场效应晶体管。结果表明,采用这种双层结构的绝缘层能够很好的将Ta2O5和PMMA的优点结合在一起,即既利用了Ta2O5的高介电常数又利用了PMMA与半导体层良好的界面接触特性。与采用单一Ta2O5或这PMMA绝缘层的器件相比,这种具有双层结构的器件性能大幅提升。最终研制了能够在10V低电压下正常工作的C60晶体管,其场效应迁移率、阈值电压和开关电流比分别为0.26 cm2/Vs, 3.2V和8.31×104。同时,利用修饰绝缘层PMMA的疏水性大大降低了这种具有双层结构的N型有机晶体管的“迟滞效应”,从而让器件工作时有较好的稳定性。     

Performance enhancement of core-shell JLFET by gate/dielectric engineering

ABSTRACT

In this paper, enhancement of volume depletion is studied on P-type double gate junctionless Field Effect Transistor (P-DGJLFET) by Gate work function and Gate dielectric engineering. The formation of parasitic BJT action in junctionless device along with DIBL effect is curtailed by integrating Rectangular Core-Shell (RCS) architecture with varying core doping along with different gate oxides and electrodes, respectively. After validating our simulations with the experimental results on Junctionless P-type FET, we demonstrated that RCS based P-DGJLFET with high K dielectric and aluminium as gate electrode exhibits superior ON/OFF ratio, Lower DIBL, better ON current, good OFF current and desired threshold voltage at channel length 5 nm. An exceptional ON/OFF current ratio (I_ON/I_OFF) of 10¹⁰ is achieved when core is made thicker than shell. The DIBL is reduced by 62.5% when thin core along with SiO₂ is replaced by thick core and HfO₂. Also, the stringent requirement of lower work function in Junctionless P-type is relaxed using RCS architecture. The performance of RCS with polysilicon as gate electrode is better than conventional DGJLFET with aluminium as gate electrode. A comprehensive comparison on performances between different technology boosters applied on double gate JLT in the literature and proposed device is also presented.     

Ultrathin InAlN/AlN Barrier HEMT With High Performance in Normally Off Operation

We present GaN-based high electron mobility transistors (HEMTs) with a 2-nm-thin InAlN/AlN barrier capped with highly doped n⁺⁺ GaN. Selective etching of the cap layer results in a well-controllable ultrathin barrier enhancement-mode device with a threshold voltage of +0.7 V. The n⁺⁺ GaN layer provides a 290-Omega/square sheet resistance in the HEMT access region and eliminates current dispersion measured by pulsed IV without requiring additional surface passivation. Devices with a gate length of 0.5-mum exhibit maximum drain current of 800 mA/mm, maximum transconductance of 400 mS/mm, and current cutoff frequency fT of 33.7 GHz. In addition, we demonstrate depletion-mode devices on the same wafer, opening up perspectives for reproducible high-performance InAlN-based digital integrated circuits.     

Optimization design on breakdown voltage of AlGaN/GaN high-electron mobility transistor

Simulations are carried out to explore the possibility of achieving high breakdown voltage of GaN HEMT (high-electron mobility transistor). GaN cap layers with gradual increase in the doping concentration from 2×10¹⁶ to 5×10¹⁹ cm^-3 of N-type and P-type cap are investigated, respectively. Simulation results show that HEMT with P-doped GaN cap layer shows more potential to achieve higher breakdown voltage than N-doped GaN cap layer under the same doping concentration. This is because the ionized net negative space charges in P-GaN cap layer could modulate the surface electric field which makes more contribution to RESURF effect. Furthermore, a novel GaN/AlGaN/GaN HEMT with P-doped GaN buried layer in GaN buffer between gate and drain electrode is proposed. It shows enhanced performance. The breakdown voltage of the proposed structure is 640 V which is increased by 12% in comparison to UID (un-intentionally doped) GaN/AlGaN/GaN HEMT. We calculated and analyzed the distribution of electrons'' density. It is found that the depleted region is wider and electric field maximum value is induced at the left edge of buried layer. So the novel structure with P-doped GaN buried layer embedded in GaN buffer has the better improving characteristics of the power devices.     

30 nm T-gate enhancement-mode InAlN/AlN/GaN HEMT on SiC substratesfor future high power RF applications

The DC and RF performance of 30 nm gate length enhancement mode (E-mode) InAlN/AlN/GaN high electron mobility transistor (HEMT) on SiC substrate with heavily doped source and drain region have been investigated using the Synopsys TCAD tool. The proposed device has the features of a recessed T-gate structure, InGaN back barrier and Al₂O₃ passivated device surface. The proposed HEMT exhibits a maximum drain current density of 2.1 A/mm, transconductance g_m of 1050 mS/mm, current gain cut-off frequency f_t of 350 GHz and power gain cut-off frequency f_max of 340 GHz. At room temperature the measured carrier mobility (μ), sheet charge carrier density (n_s) and breakdown voltage are 1580 cm²/(V·s), 1.9×10¹³ cm^-2, and 10.7 V respectively. The superlatives of the proposed HEMTs are bewitching competitor or future sub-millimeter wave high power RF VLSI circuit applications.