共查询到20条相似文献,搜索用时 93 毫秒
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IC生产线晶圆片冲洗甩干设备的开发和应用 总被引:1,自引:1,他引:0
杨建忠 《电子工业专用设备》2004,33(3):64-68
从IC生产线晶圆片旋转冲洗甩干工艺出发,介绍了半导体晶圆片清洗后的旋转冲洗甩干方法,以及新近开发研制的CXS系列旋转冲洗甩干机的技术原理、结构特点及工艺应用情况。 相似文献
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由《半导体国际》主办的“第四届晶圆清洗研讨会”8月9日在上海圆满闭幕。会议吸引了200多名国内知名晶圆厂经理人和工程师,另外,TFTLCD制造厂的工程师也积极参与了本次研讨会。针对制造工艺中的清洗案例和解决方案,晶圆厂和设备材料供应商的专家及经理人就单晶圆清洗、兆声波清洗、喷淋法、浸泡法等各种清洗技术的应用等话题,与听众进行了热烈的互动。 相似文献
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晶圆切割中背面崩裂问题的分析 总被引:2,自引:1,他引:1
半导体技术不断发展,越来越多的新材料、新工艺应用在晶圆制造中。这对封装核心工序的划片工艺提出了很大挑战。在划片工艺中背面崩裂的控制是一个难点。文章主要是从工艺材料、工艺条件、划片刀以及设备四方面分析产生背面崩裂的主要因素以及优化方法。同时介绍了两种控制背面崩裂较有效的切割工艺:减少应力的开槽切割工艺和DBG工艺。 相似文献
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在功率金属氧化物半导体器件生产中,有些为了达到特殊的器件性能,采用深沟槽工艺,其沟槽深度可达几十微米,该类产品在关键的深沟槽刻蚀中,晶片边缘经常会有硅针缺陷产生,该缺陷在后续湿法清洗过程中,会成为颗粒的主要来源,影响晶片良率和污染湿法清洗机台。文章阐述了两种通过优化沟槽光刻工艺来解决此种缺陷的方法,一种为沟槽层光刻采用倒梯形工艺,另一种为沟槽层光刻采用负光阻工艺,两种方法旨在将晶片周边保护起来,在深沟槽刻蚀中下层材质不被损伤,解决深沟槽工艺产品周边硅针缺陷问题。 相似文献
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全自动太阳能硅片清洗机是对脱胶预清洗之后的硅片进行进一步的清洗。为了保证得到洁净的硅片,除了采用碱溶液清洗之外,清洗设备还增加了浸泡、超声清洗、抛动、鼓泡等清洗工艺,提高了硅片的清洗质量和可靠性,保证了硅片的清洗合格率。采用先进的自动控制系统,不仅能满足客户的现有工艺要求,还可以根据用户的需求进行不同的工艺配置。 相似文献
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随着半导体工业的发展,对芯片的厚度要求愈来愈薄。在半导体制造中通过对硅片进行背面减薄达到芯片变薄的目的。然而由于硅片的厚度变薄,在后续的制造过程中也增加了硅片破裂的概率。对于已经几乎加工完毕的芯片,破片造成的成本显然是相当高昂的。文章对硅片在背面减薄工序和流通环节中可能产生破片的因素进行了研究探索,通过对设备的部分装置进行改造,改进流通环节中的一些方法,经过总结数据,验证了硅片在背面减薄工序中降低破片率的可行性。 相似文献
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Ultra clean technology (ultra clean processing environment, ultra clean wafer surface, perfect process-parameter control) is a crucial factor in developing high quality process technology for future ULSI fabrication. Wafers should never be exposed to air. The possibility of performing all wafer processes in equipment having the same hardware configuration is discussed based on the concept of a closed manufacturing system in conjunction with highly advanced super clean systems. 相似文献
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硅片脱胶技术的现状及发展研究 总被引:1,自引:1,他引:0
介绍了硅棒在线切割后的脱胶工艺技术,分析了硅片脱胶的技术发展和难点,通过介绍主要工艺设备的工作原理来剖析脱胶技术的现状以及未来发展的趋势。 相似文献
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Concurrent bombardment of a growing film surface by Ar ions having low kinetic energies comparable to typical inter-atomic
binding energies has been utilized to activate the film surface. It has been shown that such activation is quite effective
and can be substituted for substrate heating during crystal growth. As a result, high quality, device grade epitaxial silicon
films have been successfully grown at very low temperatures of 250°–300° C. In this epitaxial growth process, dopant impurities
in the target are fully incorporated into the grown film and 100% electrically activated at such low temperatures. The direction
for further reducing the epitaxial silicon growth temperature has been examined experimentally, and it is shown that the establishment
of anultra clean processing environment andultra clean wafer surface as well asperfect process parameter control are quite essential for very low temperature silicon epitaxy. 相似文献
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《Microelectronic Engineering》1999,45(2-3):209-223
Under gravitational and thermal constraints of IC process technology, 300 mm diameter silicon wafers can partly relax via slip dislocation generation and propagation, degrading the electrical characteristics of the leading edge device. We present a force balance model to describe the strain relaxation in large wafer diameter, which includes heat transfer effects and the criterion for yielding under a plane stress state. The material attributes, e.g. oxygen and its state of aggregation, are taken into account. While the plastic deformation of silicon wafers caused by thermal stresses at high temperatures can be controlled by process design, the control of plastic deformation due to gravitational forces may be accomplished by equipment design. This system approach allows calculation of wafer mechanics and ramp rate profiles for an arbitrary high-temperature process. The quantitative theory proposed here provides guidance for computer simulation to configure stable slip-free wafer process flow under mechanical and thermal loads. Applications include high speed simulations for use in ‘what if’ experiments or initial simulations of large scale experimental sequences. The simulator developed can also be used by IC manufacturers to determine optimum wafer throughput and cycle times in front-end device processes. 相似文献
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The ShellCase wafer-level packaging process uses commercial semiconductor wafer processing equipment. Dies are packaged and encapsulated into separate enclosures while still in wafer form. This wafer level chip size package (WLCSP) process encases the die in a solid die-size glass shell. The glass encapsulation prevents the silicon from being exposed and ensures excellent mechanical and environmental protection. A proprietary compliant polymer layer under the bumps provides on board reliability. Bumps are placed on the individual contact pads, are reflowed, and wafer singulation yields finished packaged devices. This WLCSP fully complies with Joint Electron Device Engineering Council (JEDEC) and surface mount technology (SMT) standards. Such chip scale packages (CSP's) measure 300-700 μm in thickness, a crucial factor for use in various size sensitive electronic products 相似文献