Planar p-on-n HgCdTe heterojunction mid-wavelength infrared photodiodes formed using plasma-induced junction isolation

Planar p-on-n HgCdTe heterojunction photodiodes have been fabricated using a plasma-induced type conversion process for device junction isolation. The technique is presented as a fully planar alternative technology to the commonly used mesa isolation structure. The starting material consisted of an indium-doped n-type mid-wavelength infrared (MWIR) HgCdTe absorbing layer that was capped by a 1-μm-thick wider bandgap arsenic-doped p-type layer. Junction-isolated p-on-n diodes were formed by selectively p-to-n type converting the p-type cap layer using a plasma process. Photodiode dark current-voltage measurements were performed as a function of temperature, along with noise and responsivity. The devices have cut-off wavelengths between 4.8 μm and 5.0 μm, exhibit diffusion-limited dark currents down to 145 K, give R₀A values greater than 1 × 10⁷Ω·cm² at 80 K and greater than 1 × 10⁵Ω·cm² at 120 K, and have negligible 1/f noise current at zero applied bias.     

Status of the MBE technology at leti LIR for the manufacturing of HgCdTe focal plane arrays

This paper presents recent developments that have been made in Leti Infrared Laboratory in the field of molecular beam epitaxy (MBE) growth and fabrication of medium wavelength and long wavelength infrared (MWIR and LWIR) HgCdTe devices. The techniques that lead to growth temperature and flux control are presented. Run to run composition reproducibility is investigated on runs of more than 15 consecutively grown layers. Etch pit density in the low 10⁵ cm⁻² and void density lower than 10³ cm⁻² are obtained routinely on CdZnTe substrates. The samples exhibit low n-type carrier concentration in the 10¹⁴ to 10¹⁵ cm⁻³ range and mobility in excess of 10⁵ cm²/Vs at 77 K for epilayers with 9.5 μm cut-off wavelength. LWIR diodes, fabricated with an-on-p homojunction process present dynamic resistance area products which reach values of 8 10³ Ωcm² for a biased voltage of −50 mV and a cutoff wavelength of 9.5 μm at 77 K. A 320 × 240 plane array with a 30 μm pitch operating at 77 K in the MWIR range has been developed using HgCdTe and CdTe layers MBE grown on a Germanium substrate. Mean NEDT value of 8.8 mK together with an operability of 99.94% is obtained. We fabricated MWIR two-color detectors by the superposition of layers of HgCdTe with different compositions and a mixed MESA and planar technology. These detectors are spatially coherent and can be independently addressed. Current voltage curves of 60 × 60 μm² photodiodes have breakdown voltage exceeding 800 mV for each diode. The cutoff wavelength at 77 K is 3.1 μm for the MWIR-1 and 5 μm for the MWIR-2.     

Molecular beam epitaxy grown long wavelength infrared HgCdTe on Si detector performance

The use of silicon as a substrate alternative to bulk CdZnTe for epitaxial growth of HgCdTe for infrared (IR) detector applications is attractive because of potential cost savings as a result of the large available sizes and the relatively low cost of silicon substrates. However, the potential benefits of silicon as a substrate have been difficult to realize because of the technical challenges of growing low defect density HgCdTe on silicon where the lattice mismatch is ∼19%. This is especially true for LWIR HgCdTe detectors where the performance can be limited by the high (∼5×10⁶ cm⁻²) dislocation density typically found in HgCdTe grown on silicon. We have fabricated a series of long wavelength infrared (LWIR) HgCdTe diodes and several LWIR focal plane arrays (FPAs) with HgCdTe grown on silicon substrates using MBE grown CdTe and CdSeTe buffer layers. The detector arrays were fabricated using Rockwell Scientific’s planar diode architecture. The diode and FPA and results at 78 K will be discussed in terms of the high dislocation density (∼5×10⁶ cm²) typically measured when HgCdTe is grown on silicon substrates.     

Uniformity in HgCdTe diode arrays fabricated by reactive ion etching

Two-dimensional, midwavelength infrared (MWIR) HgCdTe detector arrays have been fabricated using reactive ion etching (RIE). Detector-to-detector uniformity has been studied in the devices fabricated with CdTe- and ZnS-passivation layers. Mapping of the doping profile, passivant/HgCdTe interface electrical properties, and diode impedance-area product (R₀A_j) in a two-dimensional array of diodes has been carried out. Temperature and perimeter/area dependence of the dark current are studied to identify the bulk and surface current components. Maximum R₀A_j=2×10⁷ Θcm² was achieved in CdTe-passivated, 200×200 μm² diode arrays. It demonstrates that CdTe-passivated, RIE-processed HgCdTe is a feasible technology.     

Ten-inch molecular beam epitaxy production system for HgCdTe growth

Growth of Hg_1−xCd_xTe by molecular beam epitaxy (MBE) has been under development since the early 1980s at Rockwell Scientific Company (RSC), formerly the Rockwell Science Center; and we have shown that high-performance and highly reproducible MBE HgCdTe double heterostructure planar p-on-n devices can be produced with high throughput for various single- and multiplecolor infrared applications. In this paper, we present data on Hg_1−xCd_xTe epitaxial layers grown in a ten-inch production MBE system. For growth of HgCdTe, standard effusion cells containing CdTe and Te were used, in addition to a Hg source. The system is equipped with reflection high energy electron diffraction (RHEED) and spectral ellipsometry in addition to other fully automated electrical and optical monitoring systems. The HgCdTe heterostructures grown in our large ten-inch Riber 49 MBE system have outstanding structural characteristics with etch-pit densities (EPDs) in the low 10⁴ cm⁻² range, Hall carrier concentration in low 10¹⁴ cm⁻³, and void density <1000 cm². The epilayers were grown on near lattice-matched (211)B Cd_0.96Zn_0.04Te substrates. High-performance mid wavelength infrared (MWIR) devices were fabricated with R₀A values of 7.2×10⁶ Ω-cm² at 110 K, and the quantum efficiency without an antireflection coating was 71.5% for cutoff wavelength of 5.21 μm at 37 K. For short wavelength infrared (SWIR) devices, an R₀A value of 9.4×10⁵ Ω-cm² at 200 K was obtained and quantum efficiency without an antireflection coating was 64% for cutoff wavelength of 2.61 μm at 37 K. These R₀A values are comparable to our trend line values in this temperature range.     

A study on the key factors affecting the electronic properties of monocrystalline silicon solar cells

The model of monocrystalline silicon solar cells is established,and the effects of wafer parameters,such as the p-Si（100） substrate thickness,the defect density,and the doping concentration,on the electronic properties of monocrystalline silicon solar cells are analyzed.The results indicate that the solar cells with an Al back-surface-field will have good electronic properties when the wafers meet the following three conditions：（i） the defect density is less than 1.0×1011 cm^-3;（ii） the doping concentration is from 5×10^15 cm^-3 to 1×10^17 cm^-3,i.e.the bulk resistivity is from 0.5 Ω·cm to 10 Ω·cm;（iii） the cells substrate thickness is in the range of 100 μm to 200 μm.     

Impact of critical processes on HgCdTe diode performance and yield

HgCdTe detector performance and yield are strongly dependant on CdZnTe substrate and HgCdTe epilayer properties, and on key device processes, especially for 8–12 μm application. Due to the correlation and optimization between these figures and diode performance, AIM has developed a mature HgCdTe technology for superior detector performance and high production rate. To meet high yield and performance for long wavelength (LW) HgCdTe diodes, dislocation densities of < 1 × 10^t cm⁻² both in substrate and epilayer have to be ensured. By a unique AIM substrate growth process, dislocation densities of 2 × 10⁴-9 × 10⁴ cm⁻² are achieved for all substrates and epilayers (100% yield). The etch pit density (EPD) on 〈111〉 epilayers is revealed by an AIM proprietary etching procedure. One critical effect is the dislocations in the diode area, which can originate from the substrate and epilayer growth and the subsequent device processes, respectively. Our studies have shown that device processes can cause additional dislocations in the diode area. Diode yield was clearly improved by a combination of wet and dry etching for diode contact etching.     

Low-Noise Mid-Wavelength Infrared Avalanche Photodiodes

Mid-wavelength infrared (MWIR) p ⁺–n ⁻–n ⁺ avalanche photodiodes (APDs) were fabricated using two materials systems, one with mercury cadmium telluride (HgCdTe) on a silicon (Si) substrate and the other with an indium arsenide/gallium antimonide (InAs/GaSb) strained layer superlattice (SLS). Diode characteristics, avalanche characteristics, and excess noise factors were measured for both sets of devices. Maximum zero-bias resistance times active area (R ₀ A) of 3 × 10⁶ Ω cm² and 1.1 × 10⁶ Ω cm² and maximum multiplication gains of 1250 at −10 V and 1800 at −20 V were measured for the HgCdTe and the SLS, respectively, at 77 K. Gains reduce to 200 in either case at 120 K. Excess noise factors were almost constant with increasing gain and were measured in the range of 1 to 1.2.     

Pressure electrical contact improved by carbon black paste

Pressure and pressureless electrical contacts were evaluated by measuring the contact electrical resistivity between copper mating surfaces. Pressure electrical contacts with a contact resistivity of 2×10⁻⁵ Ω·cm² have been attained using a carbon black paste of a thickness of less than 25 μm as the interface material. In contrast, a pressureless contact with silver paint as the interface material exhibits a higher resistivity of 3×10⁻⁵ Ω·cm² or above. A pressureless contact with colloidal graphite as the interface material exhibits the same high contact resistivity (1×10⁻⁴ Ω·cm²) as a pressure contact without any interface material. On the other hand, pressureless contacts involving solder and silver epoxy exhibit lower contact resistivity than carbon black pressure contacts.     

Self-assembled metal/molecule/semiconductor nanostructures for electronic device and contact applications

We report a fabrication approach in which we combine self-assembled metal/molecule nanostructures with chemically stable semiconductor surface layers. The resulting structures have well controlled dimensions and geometries (∼4 nm Au nanoclusters) provided by the chemical self-assembly and have stable, low-resistance interfaces realized by the chemically stable semiconductor cap layer (low-temperature grown GaAs passivated by the organic tether molecules). Scanning tunneling microscope imaging and current-voltage spectroscopy of nanocontacts ton-GaAs fabricated using this approach indicate high quality, ohmic nanocontacts having a specific contact resistance of ∼1 × 10⁻⁷Ω·cm² and a maximum current density of ∼1×10⁷ A/cm², both comparable to those observed in large area contacts. Uniform 2-D arrays of these nanocontact structures have been fabricated and characterized as potential cells for nanoelectronic device applications.     

Advances in composition control for 16 µm LPE P-on-n HgCdTe heterojunction photodiodes for remote sensing applications at 60K

With good composition control in both p-type cap and n-type base LPE layers, it is possible to make barrier-free two-layer P-on-n HgCdTe heterojunction photodiodes with very long cutoff wavelengths. Diode arrays with good R_oA operability, good quantum efficiency, and low 1/f noise at 60K have been demonstrated at cutoff wavelengths to 16.3μm. The diode performance continues to improve at lower temperatures, following a diffusion-current trend to at least 35K. Measured R_oA values of 2×10⁵ ohm-cm² for an 18 μm cutoff at 35K are the highest reported at this very long wavelength. A simple defect model applied to the area dependence of R_oA at 40K implied a defect areal density of 3×10⁴ cm⁻² and a defect impedance of 3×10⁶ ohm.     

P- and N-type doping of GaN and AlGaN epitaxial layers grown by metalorganic chemical vapor deposition

Mg- and Si-doped GaN and AlGaN films were grown by metalorganic chemical vapor deposition and characterized by room-temperature photoluminescence and Hall-effect measurements. We show that the p-type carrier concentration resulting from Mg incorporation in GaN:Mg films exhibits a nonlinear dependence both on growth temperature and growth pressure. For GaN and AlGaN, n-type doping due to Si incorporation was found to be a linear function of the silane molar flow. Mg-doped GaN layers with 300K hole concentrations p ∼2×10¹⁸ cm⁻³ and Si-doped GaN films with electron concentrations n∼1×10¹⁹ cm⁻³ have been grown. N-type Al_0.10Ga_0.90N:Si films with resistivities as low as p ∼6.6×10⁻³ Ω-cm have been measured.     

Progress in the Molecular Beam Epitaxy of HgCdTe on Large-Area Si and CdZnTe Substrates

This paper presents the progress in the molecular beam epitaxy (MBE) growth of HgCdTe on large-area Si and CdZnTe substrates at Raytheon Vision Systems. We report a very high-quality HgCdTe growth, for the first time, on an 8 cm × 8 cm CdZnTe substrate. This paper also describes the excellent HgCdTe growth repeatability on multiple 7 cm × 7 cm CdZnTe substrates. In order to study the percentage wafer area yield and its consistency from run to run, small lots of dual-band long-wave infrared/long-wave infrared triple-layer heterojunction (TLHJ) layers on 5 cm × 5 cm CdZnTe substrates and single-color double-layer heterojunction (DLHJ) layers on 6-inch Si substrates were grown and tested for cutoff wavelength uniformity and micro- and macrovoid defect density and uniformity. The results show that the entire lot of 12 DLHJ-HgCdTe layers on 6-inch Si wafers meet the testing criterion of cutoff wavelength within the range 4.76 ± 0.1 μm at 130 K and micro- and macrovoid defect density of ≤50 cm⁻² and 5 cm⁻², respectively. Likewise, five out of six dual-band TLHJ-HgCdTe layers on 5 cm × 5 cm CdZnTe substrates meet the testing criterion of cutoff wavelength within the range 6.3 ± 0.1 μm at 300 K and micro- and macrovoid defect density of ≤2000 cm⁻² and 500 cm⁻², respectively, on the entire wafer area. Overall we have found that scaling our HgCdTe MBE process to a 10-inch MBE system has provided significant benefits in terms of both wafer uniformity and quality.     

High-resistivity GaSb bulk crystals grown by the vertical bridgman method

Heavily compensated GaSb (2-in.-diameter substrates) with resistivity as high as 7 × 10³ Ω-cm, corresponding to a net donor concentration of 3.5×10¹³ cm⁻³ at 77 K, and 16.4 Ω-cm, corresponding to net donor concentration of 1.16×10¹⁶ cm⁻³ at 300 K, have been obtained by tellurium (Te) compensation in vertical-Bridgman-grown bulk crystals. Very interesting p- to n-type as well as n- to p-type changes have been observed as a function of temperature in these samples.     

Indium doping of HgCdTe grown by metalorganic chemical vapor deposition-direct alloy growth using triisopropylindium and diisopropyltellurium triisopropylindium adduct

A new indium source, triisopropylindium, was used to dope HgCdTe layers grown by metalorganic chemical vapor deposition n-type with carrier concentrations, n_H, in the range between low 10¹⁵ and low 10¹⁷ cm⁻³ at 77K. The reproducibility of carrier concentration was found to be excellent for n_H<3×10¹⁵ cm⁻³. High electron mobilities and minority carrier lifetime comparable to published values indicate that indium doping produces high quality n-type HgCdTe material. State-of the-art photodiodes were obtained by growing a p-type HgCdTe layer by liquid phase epitaxy on an indium doped layer. In addition, and adduct compound formed between diisopropyltellurium (DIPTe) and triisopropylindium (TIPIn): DIPTe·InTIP, was also found to be a viable n-type dopant for HgCdTe especially at concentrations in the low 10¹⁵ cm⁻³ or less.     

Correlation of arsenic incorporation and its electrical activation in MBE HgCdTe

The behavior of arsenic for p-type doping of MBE HgCdTe layers has been studied for various annealing temperatures and arsenic doping concentrations. We have demonstrated that arsenic is in-situ incorporated into HgCdTe layers during MBE growth. The carrier concentration has been measured by the Van der Pauw technique, and the total arsenic concentration has been determined by secondary ion mass spectroscopy. After annealing at 250°C under an Hg over pressure, As-doped HgCdTe layers show highly compensated n-type properties and the carrier concentration is approximately constant (∼mid 10¹⁵ cm⁻³) until the total arsenic concentration in the HgCdTe layers approach mid 10¹⁷ cm⁻³. The source of n-type behavior does not appear to be associated with arsenic dopants, such as arsenic atoms occupying Hg vacancy sites, but rather unidentified structural defects acting as donors. When the total arsenic concentration is above mid 10¹⁷ cm⁻³, the carrier concentration shows a dependence on the arsenic concentration while remaining n-type. We conjecture that the increase in n-type behavior may be due to donor arsenic tetramers or donor tetramer clusters. Above a total arsenic concentration of 1∼2×10¹⁸ cm⁻³, after annealing at 300°C, the arsenic acceptor activation ratio rapidly decreases below 100% with increasing arsenic concentration and is smaller than that after annealing at 450°C. The electrically inactive arsenic is inferred to be in the form of neutral arsenic tetramer clusters incorporated during the MBE growth. Annealing at 450°C appears to supply enough thermal energy to break some of the bonds of neutral arsenic tetramer clusters so that the separated arsenic atoms could occupy Te sites and behave as acceptors. However, the number of arsenic atoms on Te sites is saturated at ∼2×10¹⁸ cm⁻³, possibly due to a limitation of its solid solubility in HgCdTe.     

MOCVD grown CdZn Te/GaAs/Si substrates for large-area HgCdTe IRFPAs

Large-area HgCdTe 480×640 thermal-expansion-matched hybrid focal plane arrays were achieved by substituting metalorganic chemical vapor deposition (MOCVD)-grown CdZnTe/GaAs/Si alternative substrate in place of bulk CdZnTe substrates for the growth of HgCdTe p-on-n double-layer heterojunctions by controllably-doped mercury-melt liquid phase epitaxy (LPE). (100) CdZnTe was grown by MOCVD on GaAs/Si using a vertical-flow high-speed rotating disk reactor which incorporates up to three two-inch diameter substrates. Layers having specular surface morphology, good crystalline structure, and surface macro defect densities <50 cm⁻² are routinely achieved and both the composition uniformity and run-to-run reproducibility were very good. As the composition of the CdZnTe layers increases, the x-ray full width at half maximum (FWHM) increases; this is a characteristic of CdZnTe grown by VPE techniques and is apparently associated with phase separation. Despite a broader x-ray FWHM for the fernary CdZnTe, the FWHM of HgCdTe grown by LPE on these substrates decreases, particularly for [ZnTe] compositions near the lattice matching condition to HgCdTe. An additional benefit of the ternary CdZnTe is an improved surface morphology of the HgCdTe layers. Using these silicon-based substrates, we have demonstrated 78K high-performance LWIR HgCdTe 480×640 arrays and find that their performance is comparable to similar arrays fabricated on bulk CdZnTe substrates for temperatures exceeding approximately 78K. The performance at lower temperatures is apparently limited by the dislocation density which is typically in the low-mid 10⁶ cm⁻² range for these heteroepitaxial materials.     

Indium-tin oxide/Si contacts with In- and Sn-diffusion barriers in polycrystalline Si thin-film transistor liquid-crystal displays

Indium and tin were used as the diffusion barrier between indium-tin oxide (ITO) and polycrystalline-silicon layers to reduce the contact resistance. The ITO/Si contacts may be adopted in thin-film transistor liquid-crystal displays (TFT-LCD) to reduce the number of fabrication steps. With In and Sn layers, contact-resistance values of 5 × 10⁻³−4×10⁻³ Ωcm² were obtained. These values were higher than those of the conventional ITO/Mo/Al/Si contacts (3×10⁻⁵−4 × 10⁻⁴ Ωcm²) but lower than the values obtained from ITO/Si contacts (about 1×10⁻² Ωcm²). The Sn was stable after annealing, but In diffused into Si and lost its function as the diffusion barrier.     

MWIR DLPH HgCdTe photodiode performance dependence on substrate material

Mid wavelength infrared p-on-n double layer planar heterostructure (DLPH) photodiodes have been fabricated in HgCdTe double layers grown in situ by liquid phase epitaxy (LPE), on CdZnTe and for the first time on CdTe/sapphire (PACE-1). Characterization of these devices shed light on the nature of the material limits on device performance for devices performing near theoretical limits. LPE double layers on CdZnTe and on PACE-1 substrates were grown in a horizontal slider furnace. All the photodiodes are p-on-n heterostructures with indium as the n-type dopant and arsenic the p-type dopant. Incorporation of arsenic is via implantation followed by an annealing step that was the same for all the devices fabricated. The devices are passivated with MBE CdTe. Photodiodes have been characterized as a function of temperature. R₀A_imp values obtained between 300 and 78K are comparable for the two substrates and are approximately a factor of five below theoretical values calculated from measured material parameters. The data, for the PACE-1 substrate, indicates diffusion limited performance down to 110K. Area dependence gives further indications as to the origin of diffusion currents. Comparable R₀A_imp for various diode sizes indicates a p-side origin. R₀A and optical characteristics for the photodiodes grown on lattice-matched CdZnTe substrates and lattice mismatched PACE-1 are comparable. Howover, differences were observed in the noise characteristics of the photodiodes. Noise was measured on 50 × 50 μm devices held under a 100 mV reverse bias. At 110K, noise spectrum for devices from the two substrates is in the low 10⁻¹⁵ A/Hz^1/2 range. This value reflects the Johnson noise of the room temperature 10¹⁰ Ω feedback resistor in the current amplifier that limits the minimum measurable noise. Noise at 1 Hz, −100 mV and 120K for the 4.95 μm PACE-1 devices is in the 1–2 × 10⁻¹⁴ A/Hz^1/2, a factor of 5–10 lower than previously grown typical PACE-1 n⁺-on-p layers. Noise at 120K for the 4.60 μm PACE-1 and LPE on CdZnTe was again below the measurement technique limit. Greatest distinction in the noise characteristics for the different substrates was observed at 163K. No excess low frequency noise was observed for devices fabricated on layers grown by LPE on lattice-matched CdZnTe substrates. Photodiode noise measured at 1Hz, −100 mV and 163K in the 4.60 μm PACE-1 layer is in the 1–2×10⁻¹³ A/Hz^1/2, again a factor of 5–10 lower than previously grown PACE-1 n⁺-on-p layers. More variation in noise (4×10⁻¹³−2×10⁻¹² A/Hz^1/2) was observed for devices in the 4.95 μm PACE-1 layer. DLPH devices fabricated in HgCdTe layers grown by LPE on lattice-matched CdZnTe and on lattice-mismatched PACE-1 have comparable R₀A and quantum efficiency values. The distinguishing feature is that the noise is greater for devices fabricated in the layer grown on lattice mismatched substrates, suggesting dislocations inherent in lattice mismatched material affects excess low frequency noise but not zero bias impedance.     

Controlled p-type Sb doping in LPE-grown Hg1−x Cdx Te epilayers

A Te-rich liquid-phase-epitaxial growth process is reported whereby reproducible Sb-doped layers are prepared with hole concentrations and hole mobilities ranging from 1.8×10¹⁶ to 1.3×10¹⁹ cm⁻³ and 280 to 29 cm²/V s, respectively, at 77K for x-values ranging from 0.23 to 0.29. An effective electronic distribution coefficient for Sb of 0.01 is calculated from the hole concentration at 77K and the concentration of Sb in the growth solution. The process for group Va doping of low-x Hg_1−x Cd_x Te from Te-rich solutions and the procedure for the growth of a CdZnTe buffer layer on a CdTeSe substrate are described. For Te-rich Cd−Zn−Te growth solutions the distribution coefficient of Zn was found to be 18. The growth of a structure consisting of an Sb-doped HgCdTe epilayer on a CdZnTe buffer layer lattice matched (Δa/a<10⁻⁴) to a CdSeTe substrate has been demonstrated.