A new technique for the determination of the charge centroid in MNOS structures

A new technique of determining the charge centroid in MNOS structures is presented. The technique is based on the measurement of the flat-band voltage shift determined from C(V) characteristics and on the determination of the charge originated from the nitride traps by TDRC technique.     

A self-consistent algorithm to extract interface trap states of MOS devices on alternative high-mobility substrates

A new self-consistent technique is proposed to simultaneously extract the density of interface traps (D_it) and flat-band voltages of MOS structures fabricated on technologically relevant high-mobility semiconductors with arbitrary combination of gate stacks. The technique is based on novel analysis of the low-frequency C-V measurement. The two major problems associated with the existing low-frequency C-V technique for arbitrary substrate/oxide combinations are resolved by (i) accurate calculation of the ideal semiconductor capacitance using a self-consistent, quantum-mechanical model including wave function penetration effect, and (ii) accurate determination of the flat-band voltage utilizing an iterative scheme. The proposed technique has been applied to extract D_it profiles of a number of MOS structures fabricated on III-V semiconductors like InGaAs (with ALD grown Al₂O₃ gate dielectric) and elemental semiconductors like Ge (with GeON gate dielectric). The advantages of the proposed technique have been demonstrated by comparing with D_it profiles extracted from other capacitor-based extraction methods.     

Carrier transport mechanisms of multilevel nonvolatile memory devices with a floating gate consisting of hybrid organic/inorganic nanocomposites

Nonvolatile memory devices based on a poly(4-vinylphenol) (PVP) layer containing Cu₂ZnSnS₄ (CZTS) nanoparticles were fabricated by using a simple spin-coating method. An energy dispersive spectrum revealed that the CZTS nanoparticles were Cu poor and Zn rich. Transmission electron microscopy images showed that the CZTS nanoparticles were randomly distributed in the PVP layer. Capacitance–voltage (C–V) curves for Al/CZTS nanoparticles embedded in PVP layer/p-Si devices at 1 MHz showed a hysteresis with flat-band voltage (V_fb) shifts, which resulted from the existence of CZTS nanoparticles acting as trap sites in the memory devices. The magnitudes of the V_fb corresponding to the memory window shifts between 1.0 and 2.5 V, as determined from the C–V data at 1 MHz, were dependent on the voltages applied to the memory device, indicative of multilevel characteristics for the memory effect. The operating mechanisms of the writing and the erasing processes for Al/CZTS nanoparticles embedded in PVP layer/p-Si devices are described on the basis of the C–V results and the energy-band diagrams.     

Transport and storage properties of CrSi2/Si junctions made using the CAPVD technique

p-CrSi₂/n-crystSi and p-CrSi₂/p-crystSi hetero junctions produced by cathodic arc physical vapor deposition were worked out by means of capacitance–voltage–temperature (C–V–T) and current–voltage–temperature (I–V–T) measurements to investigate storage and transport properties. Former measurement on p-CrSi₂/n-crystSi structure confirmed an abrupt type junction together with a building voltage at the proximity of 0.7 V. Though a fairly well rectification ratio (10³ at ±2 V) was realized by I–V measurement, it became deteriorated with the increase in ambient temperature. From temperature dependence of I–V variations, distinct conduction mechanisms were identified. In forward (reverse) direction trap assisted single-multistep tunneling recombination (generation) and space-charge limited current flow that corresponded to low and high bias voltage regions, respectively, were identified. Moreover, an activation energy (E_A) determined from the slopes of I–V–T curves as 0.22 and 0.26 eV was interpreted as the energy position of a chromium–boron (Cr–B) complex-type point defect residing in n/p doped c-Si semiconductor in CrSi₂/n–c-Si and CrSi₂/p–c-Si junctions. The retrieved E_A was in agreement with the recent DLTS measurement. Based on the experimental observations, schematic current path was built to interpret I–V/C–V behaviors. The model was successful in explaining the decrease in measured capacitance under large forward bias voltage reported for the first time by us for the present CrSi₂/Si junctions.     

Interface states in polyfluorene-based metal–insulator–semiconductor devices

Hybrid metal–insulator–semiconductor structures based on ethyl-hexyl substituted polyfluorene (PF2/6) as the active polymer semiconductor were fabricated on a highly doped p-Si substrate with Al₂O₃ as the insulating oxide layer. We present detailed frequency-dependent capacitance–voltage (C–V) and conductance–voltage characteristics of the semiconductor/insulator interface. PF2/6 undergoes a transition to an ordered crystalline phase upon thermal cycling from its nematic-liquid crystalline phase, confirmed by our atomic force microscope images. Thermal cycling of the PF2/6 films significantly improves the quality of the (PF2/6)/Al₂O₃ interface, which is identified as a reduced hysteresis in the C–V curve and a decreased interface state density (D_it) from ∼3.9 × 10¹² eV⁻¹ cm⁻² to ∼3.3 × 10¹¹ eV⁻¹ cm⁻² at the flat-band voltage. Interface states give rise to energy levels that are confined to the polymer/insulator interface. A conductance loss peak, observed due to the capture and emission of carriers by the interface states, fits very well with a single time constant model from which the D_it values are inferred.     

Comparison of La-based high-k dielectrics: HfLaSiON and HfLaON

For the first time, we present a comparative study on HfLaSiON and HfLaON gate dielectric with an equivalent oxide thickness (EOT) of 0.8 nm (T_inv = 1.2 nm). A detailed DC analysis of I_on vs. I_off shows HfLaON performs somewhat better than HfLaSiON. However, positive bias temperature instability (PBTI) lifetime of HfLaSiON is higher than HfLaON by about 2 orders of magnitude. On the other hand, hot carrier stress lifetime for HfLaSiON was similar to that of HfLaON. From the activation energy and U-trap, we found that the cause of different threshold voltage (V_T) shifts under PBT stress and detrapping was originated from stable electron traps induced by different charge trapping rates.     

Au/SnO2/n-Si (MOS) structures response to radiation and frequency

Metal-insulator-semiconductor (MOS) structures with insulator layer thickness of 290 Å were irradiated using a ⁶⁰Co (γ-ray) source and relationships of electrical properties of irradiated MOS structures to process-induced surface defects have been investigated both before and after γ-irradiation. The density of surface state distribution profiles of the sample Au/SnO₂/n-Si (MOS) structures obtained from high-low frequency capacitance technique in depletion and weak inversion both before and after irradiation. The measurement capacitance and conductance are corrected for series resistance. Series resistance (Rs) of MOS structures were found both as function of voltage, frequency and radiation dose. The C(f)-V and G(f)-V curves have been found to be strongly influenced by the presence of a dominant radiation-induced defects. Results indicate interface-trap formation at high dose rates (irradiations) is reduced due to positive charge build-up in the semiconductor/insulator interfacial region (due to the trapping of holes) that reduces the flow rate of subsequent holes and protons from the bulk of the insulator to the Si/SnO₂ interface. The series resistance decreases with increasing dose rate and frequency the radiation-induced flat-band voltage shift in 1 V. Results indicate the radiation-induced threshold voltage shift (ΔV_T) strongly dependence on radiation dose rate and frequency.     

“Higher-κ” dielectrics for advanced silicon microelectronic devices: A combinatorial research study

Combinatorial methodology is used to rapidly screen suitable ternary higher-κ dielectrics for future complementary metal oxide semiconductor (CMOS), and dynamic random access memory (DRAM) devices. Dielectric constant (κ) and leakage current (L_C) were mapped from capacitance–voltage (C–V) and current–voltage (I–V) measurements. HfO₂–TiO₂–Y₂O₃ library films, made by pulsed laser deposition (PLD), have been characterized. We found a band of compositions in the middle of the HfO₂–TiO₂–Y₂O₃ phase diagram that have dielectric constants in the range of 50–80, with reasonably low leakage currents, that are therefore promising for these applications.     

Frequency and voltage dependency of interface states and series resistance in Al/SiO2/p-Si MOS structure

The capacitance–voltage (C–V) and conductance–voltage (G/ω–V) characteristics of Al/SiO₂/p-Si metal-oxide-semiconductor (MOS) Schottky diodes have been measured in the voltage range from ?3 to +3 V and frequency range from 5 KHz to 1 MHz at room temperature. It is found that both C and G/ω of the MOS capacitor are very sensitive to frequency. The fairly large frequency dispersion of C–V and G/ω–V characteristics can be interpreted in terms of the particular distribution of interface states at SiO₂/Si interface and the effect of series resistance. At relatively low frequencies, the interface states can follow an alternating current (AC) signal that contributes to excess capacitance and conductance. This leads to an anomalous peak of C–V curve in the depletion and accumulation regions. In addition, a peak at approximately ?0.2 V appears in the R_s–V profiles at low frequency. The peak values of the capacitance and conductance decrease with increasing frequency. The density distribution profile of interface state density (N_ss) obtained from C_HF–C_LF capacitance measurement also shows a peak in the depletion region.     

Improvement of oxide thickness determination on MOS structures using capacitance–voltage measurements at high frequencies

It is well known that capacitance–voltage (C–V) measurements provide a simple determination of oxide thickness, but with the scaling down of components the classical method is not appropriated any more. We have observed that for two devices with the same oxide thickness and different surfaces, the classical method is accurate for large area but it is not adapted for the small one. We present a new procedure to make an accurate electrical determination of the oxide thickness on metal-oxide-semiconductor (MOS) structures of low dimensions in U.L.S.I. technology. Our method does not require a measurement in strong accumulation. It is based on C–V measurements at frequencies higher than 1 MHz associated to a non-linear optimisation of the experimental and theoretical band bending versus bias voltage curve (Ψ_S=f(V_g)), in the depletion mode. By this way, a corrective factor is estimated with precision in order to make an accurate determination of the oxide thickness value. We show that the frequency associated to the non-linear optimisation of Ψ_S=f(V_g) is function of the MOS device dimensions and is increased when the surface decreases. The experimental results obtained on low-dimension MOS structures and different oxide thickness are precise and in total agreement with those measured by ellipsometry. By using our new procedure the accuracy of oxide thickness determination is improved.     

Graphical method for determining the flat band voltage for silicon on sapphire

A method based on the graphical solution of equations for the standard high frequency C-V curve and its first derivative yields the flat-band voltage directly. Since only the accumulation section of the C-V curve is employed, errors due to the surface states are small. The method is particularly suitable for thin film structures such as SOS where substantial depletion of the silicon layer is now eliminated.     

Flat band voltage control on low Vt metal-gate/high-κ CMOSFETs with small EOT (Invited Paper)

The unwanted high threshold voltage (V_t) is the major challenge for metal-gate/high-κ CMOS especially at small equivalent-oxide-thickness (EOT). We have investigated the high V_t issue that is due to flat-band voltage (V_fb) roll-off at smaller EOT. A mechanism of charged oxygen vacancies formed by interface reaction was proposed to explain the V_fb roll-off effect. This interface reaction can be decreased by inserting a thin interfacial SiON and using novel low temperature process. The self-aligned and gate-first metal-gate/high-κ CMOSFETs using these methods have achieved low V_t and good control of V_fb roll-off at small 0.6–1.2 nm EOT.     

Electrical properties of vacuum annealed La2O3 thin films grown by E-beam evaporation

In this article, the conduction mechanisms of metal-oxide-semiconductor with vacuum annealed Lanthana (La₂O₃) oxide film are investigated. Lanthana films with thicknesses of 3.5, 4.7, and 11 nm were deposited by E-beam evaporation on n-Si (100), and annealed at various temperatures (300-500 °C) in ultra-high vacuum (10⁻¹⁰-10⁻⁹ Torr) for 90 min. From the measurement of spectroscopic ellipsometry, it is found that film thickness is increased with annealing temperature, which would be cause of flat-band voltage shift (ΔV_FB) due to the growth of interfacial layer. From the capacitance measurement, it is found that ΔV_FB of the film is reduced by post-deposition anneal (PDA) compared to that of as-deposited film, but increase again at high temperature annealing, especially in the case of thin film (3.5 nm). From the applied voltage and temperature dependence of the leakage current of the film, with different gate electrode materials (Ag, Al, and Pt), it is shown that the leakage currents are associated with ohmic and Poole-Frenkel (P-F) conductions when flat-band voltage (V_FB) is less than zero, and ohmic and Space-Charge-Limited Current (SCLC) conductions when V_FB is greater than zero. The dielectric constants obtained from P-F conduction for Al gate electrode case is found to be 11.6, which is consistent with the C-V result 11.9. Barrier height of trap potential well is found to be 0.24 eV from P-F conduction. Based on SCLC theory, leakage currents of 3.5 and 11 nm films with different PDA temperatures are explained in terms of oxide trap density.     

Photon-assisted capacitance–voltage study of organic metal–insulator–semiconductor capacitors

The results are reported of a detailed investigation into the photoinduced changes that occur in the capacitance–voltage (C–V) response of an organic metal–insulator–semiconductor (MIS) capacitor based on the organic semiconductor poly(3-hexylthiophene), P3HT. During the forward voltage sweep, the device is driven into deep depletion but stabilizes at a voltage-independent minimum capacitance, C_min, whose value depends on photon energy, light intensity and voltage ramp rate. On reversing the voltage sweep, strong hysteresis is observed owing to a positive shift in the flatband voltage, V_FB, of the device. A theoretical quasi-static model is developed in which it is assumed that electrons photogenerated in the semiconductor depletion region escape geminate recombination following the Onsager model. These electrons then drift to the P3HT/insulator interface where they become deeply trapped thus effecting a positive shift in V_FB. By choosing appropriate values for the only disposable parameter in the model, an excellent fit is obtained to the experimental C_min, from which we extract values for the zero-field quantum yield of photoelectrons in P3HT that are of similar magnitude, 10^?5 to 10^?3, to those previously deduced for π-conjugated polymers from photoconduction measurements. From the observed hysteresis we deduce that the interfacial electron trap density probably exceeds 10¹⁶ m^?2. Evidence is presented suggesting that the ratio of free to trapped electrons at the interface depends on the insulator used for fabricating the device.     

Investigation of Characteristics of Al2O3/n-In x Ga1−x As (x = 0.53, 0.7, and 1) Metal–Oxide–Semiconductor Structures

The electrical properties of Al₂O₃/n-InGaAs metal–oxide–semiconductor capacitors (MOSCAPs) with In content of 0.53, 0.7, and 1 (InAs) have been investigated. Results show small capacitance–voltage (C–V) frequency dispersion in accumulation (1.70% to 1.85% per decade) for these MOSCAPs, mostly being assigned to border traps in Al₂O₃. With higher In content, shorter minority-carrier response time and smaller C–V hysteresis are observed. The reduction of C–V hysteresis might be related to the reduction of Ga-bearing oxides in Al₂O₃/InGaAs interfaces as indicated by x-ray photoelectron spectroscopy.     

On threshold and flat-band voltages for MOS devices with polysilicon gate and nonuniformly doped substrate

Expressions for the flat-band voltage V_FB and threshold voltage V_T for MOS devices with polysilicon gate and nonuniformly doped substrate are given. The role of metal-semiconductor contacts and the assumptions involved in the analysis are discussed. Both V_FB and V_T have three extra terms over the conventional expressions, two terms result from nonuniform doping and one is due to a voltage drop in the gate produced by space charge. Contrasts are made to devices with metal gates and uniformly doped substrates. The commonly used expression for mobile channel charge in terms of gate voltage is clarified.     

Fixed negative interface charges compromise organic ferroelectric field-effect transistors

Capacitance–voltage (C–V) and current–voltage measurements have been undertaken on metal-ferroelectric-semiconductor capacitors and ferroelectric field-effect transistors (FeFETs) using the ferroelectric polymer poly(vinylidenefluoride-trifluoroethylene) as the gate insulator and poly(3-hexylthiophene) as the active semiconductor. C–V measurements, voltage-dependence of gate currents and FeFET transfer characteristics all confirm that ferroelectric polarization is stable and only reverses when positive/negative coercive fields are exceeded for the first time. The apparent instability observed following the application of depletion voltages arises from the development of a negative interfacial charge which more than compensates the ferroelectric-induced shift, resulting in a permanent shift in threshold voltage to positive values. Application of successive bipolar voltage sweeps to a diode-connected FeFET show that significant remanent polarization is only induced in an unpoled device when the coercive field is exceeded during the first application of accumulation voltages. This initial polarization and its growth during subsequent bipolar voltage sweeps is accompanied by the accumulation of the fixed interfacial negative charges which cause the positive turn on voltages seen in C–V and transfer characteristics. The origin of the negative charge is ascribed either to layers of irreversible ferroelectric domains at the insulator surface or to the drift to the insulator-semiconductor interface of F^- ions produced electrolytically during the application of accumulation voltages.     

Adaptation of admittance analysis to extract interface traps of a-Si:H/c-Si heterojunctions

Complete admittance expressions, adapted from the equations previously presented for Metal/Oxide/Semiconductor (MOS) structure, were derived and modified admittance approach was successfully applied on a-Si:H/c-Si heterojunction to deduce surface state density (N_ss) by employing capacitance–voltage (C–V) and conductance–voltage (G/ω–V) measurements. Through the approach, N_ss was determined as 6×10¹² cm⁻² eV⁻¹ that was mutually checked by continuum model, used previously for evaluating N_ss in MOS structure. Furthermore, locating such an amount at the interface of a-Si:H and c-Si, experimentally measured C–V curve was reproduced through AFORS-HET simulation program. Presence of such a large amount of N_ss was originated due to native oxide layer, confirmed through spectroscopic elipsometry measurement.     

An experimental determination of the forward-biased emitter-base capacitance

An accurate f_T measurement technique is presented, enabling to derive, after correction for the diffusion capacitance, the emitter transition capacitance from f_T(IC). Results are compared with the Poon-Gummel C-V expression, confirming experimentally a maximum of transition-layer capacitance at the “built-in” voltage V₁.     

Co gamma irradiation effects on electrical characteristics of Al/Y2O3/n-Si/Al capacitors

Al/Y₂O₃/n-Si/Al capacitors were irradiated by using a ⁶⁰Co gamma ray source and a maximum dose up to 8.4 kGy. The effect of an annealing treatment performed at 600 or 900 °C on the yttrium oxide (Y₂O₃) films was investigated by XRD and Raman spectroscopy. High-frequency capacitance-voltage (C-V) and conductance-voltage (G-V) measurements as well as quasi-static measurements of the MOS structures were analysed. The annealing improves the crystalline state of the Y₂O₃ thin film material and decreases the values of the flat-band voltage and of the interface trap level density indicating an improvement of the electrical properties of the interface thin film-substrate. But at this interface, the formation of an yttrium-silicate layer was also evidenced. After gamma irradiation, the values of the flat-band voltage and of the interface trap level density related to the Al/Y₂O₃/n-Si/Al structure increase and especially for the structure made with the materials annealed at 900 °C for 1 h. In that case, the structure is very sensitive to a gamma irradiation dose up to 8.4 kGy.