一种低电压、低功耗CMOS基准电压源的设计

本文设计了一种低电压、低功耗、高电源抑制比CMOS基准电压源。该电路基于工作在亚阈值区的MOS管,利用PTAT电流源与微功耗运算放大器构成负反馈系统以提高电源电压抑制比。SPICE仿真显示,在1V的电源电压下,输出基准电压为609mV,温度系数为72ppm/℃,静态工作电流仅为1.23μA。在1-5V的电源电压变化范围内,电压灵敏度为130μV/V,低频电源电压抑制比为74dB。该电路为全CMOS电路,不需要用到寄生PNP三极管,具有良好的CMOS工艺兼容性。     

Self-Balanced Charge Pump with Fast Lock Circuit

A self-balanced charge pump （CP） with fast lock circuit to achieve nearly zero phase error is proposed and analyzed. The proposed CP is designed based on the SMIC 0.25μm 1P5M complementary metal oxide semiconductor （CMOS） process with a 2.5 V supply voltage, HSPICE simulation shows that even if the mismatch of phase/frequency detector （PFD） was beyond 10%, the charge pump could still keep nearly zero phase error, Incorporated fast lock circuit can shorten start-up time to below 300 ns.     

一种高性能的BiCMOS带隙基准电压源

提出了一种新颖的利用负反馈环路以及RC滤波器提高电源抑制比的高精密CMOS带隙基准电压源．采用上海贝岭的1．2μm BiCMOS工艺进行设计和仿真,spectre模拟表明该电路具有较高的精度和稳定性,带隙基准的输出电压为1．254V,在2．7V-5．5V电源电压范围内基准随输人电压的最大偏移为0．012mV,基准的最大静态电流约为11．27μA;当温度-40℃-120℃范围内,基准温度系数为1mV;在电源电压为3．6V时,基准的总电流约为10．6μA,功耗约为38．16μW;并且基准在低频时具有100dB以上的电源电压抑制比（PSRR）,基准的输出启动时间约为39μs．     

一种新型的高电源抑制比带隙基准源的设计

利用有源PMOS负载反相器组成电压减法器,将电源噪声引入运放反馈,得到了一种高电源抑制比的基准电压源。对基准源的低频电源噪声抑制进行了推导和分析。仿真结果表明,在3 V电源电压下,在-40~85℃范围内,温度系数低于1.976 ppm/℃;在27℃下,1 KHz时,电源抑制比达88 dB.     

高电源噪声抑制比带隙基准源设计

采用CSMC 0.35μm工艺,通过在电源和带隙基准源电路间插入电流源缓冲级的方法,设计提高带隙基准源电源噪声抑制能力的带隙基准源.在最低工作电压不变的情况下,所设计的带隙基准电源大幅度提高了电路的电源抑制比,且功耗低.仿真结果表明:电源抑制比值为110dB/40dB,Iq=12μA,Vmin=2.4V,可作为模拟IP(知识产权)且易集成于单片系统中.     

高阶曲率补偿电流模式的CMOS带隙基准源

为获得一个稳定而精确的基准电压,提出了一种适用于低电源电压下高阶曲率补偿的电流模式带隙基准源电路,通过在传统带隙基准源结构上增加一个电流支路,实现了高阶曲率补偿。该电路采用Chartered 0.35μm CMOS工艺,经过Spectre仿真验证,输出电压为800mV,在-40～85℃温度范围内温度系数达到3×10^-6℃^-1,电源抑制比在10kHz频率时可达-60dB,在较低电源电压为1．7V时电路可以正常启动,补偿改进后的电路性能较传统结构有很大提高．     

低电压基准电压源

设计了一个低电源电压的高精密的CMOS带隙电压基准源,采用SMIC 0.18μm CMOS工艺。实现了一阶温度补偿,具有良好的电源抑制比。测试结果表明,在1.5 V电源电压下,电源抑制比为47 dB,在0~80℃的温度范围内,输出电压变化率为0.269%,功耗为0.22 mW,芯片核面积为0.057 mm2。     

一种新型高精度低压CMOS带隙基准电压源

为消除运算放大器失调电压对带隙电压精度的影响,采用NPN型三极管产生ΔVbe,并设计全新的反馈环路结构产生了低压带隙电压.电路采用SMIC 0.18μm CMOS工艺实现,该新型低压带隙基准源设计输出电压为0.5V,温度系数为8ppm/℃,电源抑制比达到-130dB,并成功运用于16位高速ADC芯片中.     

在芯片可调低电压带隙基准源设计

为高速双模预分频器提供所需的稳定的参考电平,提出了一种基于带隙基准核的在芯片可调低电压带隙基准源电路设计方法,通过在双极型晶体管的附近并联少量电阻,获得数值可调的、常温下具有零温度系数的低电压基准。讨论了运放的反馈环路、失调电压以及开环增益等各项因素对基准电压精度的影响,并给出了相关的分析公式。设计采用0.18μm数模混合CMOS工艺。仿真结果表明,电路的电源抑制比(PSRR)为-48dB,-40℃~+125℃温度变化范围内的温漂系数为8.3×10-6/℃。电路综合性能良好,能满足低温漂、高精度的设计要求。     

A PLL Clock Frequency Multiplier Using Dynamic Current Matching Adaptive Charge-Pump and VCO Frequency Reuse

A 3.5 times PLL clock frequency multiplier for low voltage different signal （LVDS） driver is presented. A novel adaptive charge pump can automatically switch the loop bandwidth and a voltage-controlled oscillator （VCO） is designed with the aid of frequency ranges reuse technology. The circuit is implemented using 1st Silicon 0.25 μm mixed-signal complementary metal-oxide-semiconductor （CMOS） process. Simulation results show that the PLL clock frequency multiplier has very low phase noise and very short capture time .     

Application of Nanometer-Size Titanium Dioxide in Extreme-Trace V（Ⅴ） Analysis

0Introduction Vanadiumplaysanimportantroleinmodernindustry,es peciallyinsteelandchemicalindustry.Forinstance,itscompoundsarewidelyappliedintheproceduresofvitrioland petroleumchemicalmanufactureascatalyzers[14].Vanadium hasseveralvalences,butgenerallyitslowvalencesturnintohighoneseasilyinenvironment[5].BecauseV(Ⅴ)isthemost stableandpoisonousone,weoftenlayemphasisonitinenvi ronmentalpollutioncontrol.Vanadiumexistsinenvironmentalwaterwithextremelylowconcentration.Inseawateritscontentislessthan…     

Voltammetric Response of Epinephrine at Carbon Nanotube Modified Glassy Carbon Electrode and Activated Glassy Carbon Electrode

0Introduction Epinephrine(EP)isanimportantcate cholamineneurotransmitterinthemammaliancentralnervoussystem,whichissecretedbythesu prarenalglandalongwithnorepinephrine.Itisgen erallyusedtotreathypertension,bronchialasthma,organicheartdisease,andincardiacsurgeryand myocardialinfarction[1].VariousmethodshavebeendevelopedforEPstudy,suchascapillaryelectro phoresis(CE)[2],highperformanceliquidchroma tography(HPLC)andflowinjectionanalysis(FIA)[3].Numerousobservationsontheelectro chemicalbehavio…     

Electrochemical determination of trace amounts of lead (II) and cadmium (II) at a calix[6]arene modified carbon paste electrode

An electrochemical method for the simultaneous determination of lead(II) and Cadmium(II) with a calix[6]arene modified carbon paste electrode (CPE) has been developed. Pb²⁺ and Cd²⁺ were accumulated at the surface of the modified electrode via formation of chemical complexes with calix[6]arene, and reduced at 1.40 V. During the following anodic potential sweep, reduced lead and cadmium were oxidized, and two well-defined striping peaks appeared at about −0.60 V and −0.84 V. Compared with a bare carbon paste electrode, the calix[6]arene modified CPE greatly improves the sensitivity of determining lead and cadmium. The stripping peak currents change linearly with the concentration of Pb²⁺ 3.0×10⁻⁸–8.0×10⁻⁶ mol·L⁻¹ and with that of Cd²⁺ 6.0×10⁻⁸–1.0×10⁻⁵ mol ·L⁻¹. The detection limits of Pb²⁺ and Cd²⁺ are found to be 8.0×10⁻⁹ mol·L⁻¹ and 2.0×10⁻⁸ mol·L⁻¹, respectively. The modified carbon paste electrode was applied to determine trace levels of lead and cadmium in water samples. Comparing with that of atomic absorption spectrometry, the results suggests that the calix[6]arene modified CPE has great potential for the practical sample analysis. Foundation item: Supported by the National Natural Science Foundation of China (60171023) Biography: JI Xiao-bo (1980-), male, Master, research direction: electroanalytical chemistry.     

Ethernet controller SoC design and its low-power DFT considerations

In this paper, an Ethernet controller SoC solution and its low power design for testability (DFT) for information appliances are presented. On a single chip, an enhanced one-cycle 8-bit micro controller unit (MCU), media access control (MAC) circuit and embedded memories such as static random access memory (SRAM), read only memory (ROM) and flash are all integrated together. In order to achieve high fault coverage, at the same time with low test power, different DFT techniques are adopted for different circuits: the scan circuit that reduces switching activity is implemented for digital logic circuits; BIST-based method is employed for the on-chip SRAM and ROM. According to the fault-modeling of embedded flash, we resort to a March-like method for flash built in self test (BIST). By all means above, the result shows that the fault coverage may reach 97%, and the SoC chip is implemented successfully by using 0.25 μm two-poly four-metal mixed signal complementary metal oxide semiconductor (CMOS) technology, the die area is 4.8×4.6 mm2. Test results show that the maximum throughput of Ethernet packets may reach 7 Mb · s⁻¹. Biography: ZHENG Zhaoxia (1975–), female,Ph.D. candidate, Lecturer, research direction: system one chip (SOC) integrated circuits design.     

一种高阶温度补偿的CMOS带隙参考源

介绍了一种基于CSMC 0.5-μm 2P3M n-阱混合信号CMOS工艺的高阶温度补偿的带隙参考源。该CMOS带隙参考源利用了Buck电压转换单元和与温度无关的电流,提供了一种对基极-发射极电压V_BE的高阶温度补偿。它还采用共源共栅结构以提高电源抑制比。在5V电源电压下,温度变化范围为-20～100℃时,该带隙参考源的温度系数为5.6ppm/℃。当电源电压变化范围为4～6V时,带隙参考源输出电压的变化为0.4mV。     

Optimizing Conditions of Enhancing Granule Sludge Concentration and Performance

An expanded granular sludge bed （EGSB） reactor was adopted to study the influence factors and rule of enhancing granular sludge concentration and performance. The experiment was performed at 33 ℃, pH 6.0-8.0 with continuous flow by adding proper quantity of nutritional trace elements. The results show that SLR was the key of steady operation of EGSB reactor. The increment of the granular sludge was influenced by volume loading rate （VLR）, liquid up-flow velocity and sludge loading rate （SLR）. Concentration of granular sludge increased rapidly when liquid up-flow velocity was over 0.94 m · h^-1 with SLR being at 1.0-2.0 d ^-1. With the propriety parameters： liquid up-flow velocity 2.52 m · h^-1, SLR 1.0-2.2 d^-1 and VLR 8.2-13.1 kg · m ^3 · d^-1, 23 days＇ continuous operation resulted in an increment by over 80% of granular sludge concentration in the EGSB reactor, plus good granular sludge property.     

Meteorological conditions of ice accretion based on real-time observation of high voltage transmission line

Meteorological conditions during ice accretion on the 500 kV high voltage transmission lines and test cables are presented, together with a calculation of liquid water content (LWC). The data include meteorological observations and real-time ice accretion on the transmission lines of the central China power grid, from 2008 to 2009 in Hubei Province. Also included are observations of ice thickness, microphysics of fog droplets, and other relevant data from a nearby automated weather station at Enshi radar station, from January to March 2009. Results show that temperature at Zhangen tower #307 was correlated with the temperature at Enshi radar station. The temperature on the surface of the high voltage transmission line was 2-4°C higher than ambient air temperature, although the temperatures were positively correlated. Ice formation temperature was about -2°C and ice shedding temperature was about -2 to -1°C on the high voltage transmission line, both of which were lower than the temperature threshold values on the test cable. Ice thickness was significantly affected by temperature variation when the ice was thin. The calculated LWC was correlated with observed LWC, although the calculated value was greater.     

Dynamic control on grain-size distribution of terrigenous sediments in the western South China Sea: Implication for East Asian monsoon evolution

High-resolution oxygen isotope stratigraphy of Core MD05-2901, which is located off eastern Vietnam in the western South China Sea （SCS）, was established and indicated that the core spans a time period of the past 450 ka. Based on the bulk density, fractional porosity and lithogenic content of the sediments, terrigenous mass accumulation rate （TMAR） was obtained, which is 4.9-6.0 g cm^-2 ka^-1 on average during interglacial stages, higher than that during glacial stages, i.e. 1.9-5.0 g cm^-2 ka^-1, which is different from northern and southern SCS which show higher TMAR in glacial stages. By principle component analysis of grain size distribution of all the samples, two main control factors （F1 and F2） were obtained, which are responsible for about 80% variance of granularity. The contents of grain size population 1.26-2.66 μm% and 10.8-14.3 μm% which are sensible to F1 show high-frequency fluctuation, and correlate well with the summer insolation at 15^o N. They exhibit a distinct cyclicity with frequencies near 23 ka and 13 ka, in contrast to a strong frequency peak near 100 ka obtained in proxies 4.24-7.42 μm% and 30.1-43.7 μm% controlled mainly by F2. The sedimentary character of this part of the SCS was controlled by variations of input flux from two main source areas, namely the southwest and north SCS, which were transported by different circulations of surface current forced by East Asian summer monsoon and winter monsoon respectively. We believe that the East Asian summer monsoon has fluctuated with high frequency and been forced by changes in solar insolation in low latitude associated with precession and half precession, while ice-volume forcing is probably a primary factor in determining the strength and timing of the East Asian winter monsoon but with less important insolation forcing.     

Design of a CMOS Adaptive Charge Pump with Dynamic Current Matching

A novel structure for a charge pump circuit is proposed, in which the charge-pump （CP） current can adaptively regulated according to phase-locked loops （PLL） frequency synthesis demand. The current follow technology is used to make perfect current matching characteristics, and the two differential inverters are implanted to increase the speed of charge pump and decrease output spur due to theory of low voltage difference signal. Simulation results, with 1st silicon 0. 25μm 2. 5 V complementary metal-oxide-semiconductor （CMOS） mixed-signal process, show the good current matching characteristics regardless of the charge pump output voltages.     

自偏置的多段曲率校正带隙基准源

典型的帶隙基准电压源电路是由CMOS工艺产生的具有负温度系数的寄生横向BJT的发射结电压VEB和具有正温度系数的热电压Vt 相补偿产生零温度系数的基准帶隙电压源。但是VEB与温度不是线性关系, 因此VREF需要被校正。本文介绍了一种高精度自偏置多段二次曲率补偿的CMOS帶隙基准电压源。采用0.5 m CMOS工艺、工作电压为3.3V,该芯片室温下功耗为94W。设计在0 oC—75 oC有效温度系数达到了0.7ppm/oC。