Fabrication of low defect density 3C-SiC on SiO2 structures using wafer bonding techniques

This paper reports on a process to fabricate single-crystal 3C-SiC on SiO₂ structures using a wafer bonding technique. The process uses the bonding of two polished polysilicon surfaces as a means to transfer a heteroepitaxial 3C-SiC film grown on a Si wafer to a thermally oxidized Si wafer. Transfer yields of up to 80% for 4 inch diameter 3C-SiC films have been achieved. Homoepitaxial 3C-SiC films grown on the 3C-SiC on SiO₂ structures have a much lower defect density than conventional 3C-SiC on Si films.     

用于MEMS器件芯片级封装的金-硅键合技术研究

MEMS器件大都含有可动的硅结构 ,在器件加工过程中 ,特别是在封装过程中极易受损 ,大大影响器件的成品率。如果能在MEMS器件可动结构完成以后 ,加上一层封盖保护 ,可以显著提高器件的成品率和可靠性。本文提出了一种用于MEMS芯片封盖保护的金 硅键合新结构 ,实验证明此方法简单实用 ,效果良好。该技术与器件制造工艺兼容 ,键合温度低 ,有足够的键合强度 ,不损坏器件结构 ,实现了MEMS器件的芯片级封装。我们已经将此技术成功地应用于射流陀螺的制造工艺中     

界面热应力对InP/Si键合质量的影响

通过实验和理论计算,分析了InP/Si键合过程中,界面热应力的分布情况、影响键合结果的关键应力因素及退火温度的允许范围。分析结果表明,由剪切应力和晶片弯矩决定的界面正应力是晶片中心区域大面积键合失败的主要原因,为保证良好的键合质量,InP/Si键合退火温度应该在300～350℃范围内选取。具体实验验证表明,该理论计算值与实验结果相一致。最后,在300℃退火条件下,很好地实现了2inInP/Si晶片键合,红外图像显示,界面几乎没有空洞和裂隙存在,有效键合面积超过90%。     

Si/InP键合界面的研究

应用疏水处理方法成功实现了Si/InP的键合,然后通过对InP和Si的表面XPS能谱分析得到界面信息,从而了解键合机理.I-V曲线也反应了键合界面的性质,通过450、550℃退火样品的伏安特性可知道,对于InP/Si键合结构而言,退火温度与界面特性应该存在最佳值.     

InP/Si键合技术研究进展

InP材料及其器件的研制是近年来研究热点之一,而键合技术又是光电子集成研究领域内一项新的制作工艺。利用键合技术结合离子注入技术可以InP薄膜及器件集成到Si衬底上,改善机械强度,降低成本,具有非常诱人的应用前景。概括地介绍了近年来InP在Si上的键合工艺及层转移技术研究进展,并对InP和Si的几种键合工艺进行了分析。降低InP和Si键合温度,进行低温键合是其发展趋势。比较几种键合技术,利用等离子活化辅助键合是降低键合温度的有效途径。     

Silicon layer transfer using wafer bonding and debonding

Two experiments were performed that demonstrate an extension of the ion-cut layer transfer technique where a polymer is used for planarization and bonding. In the first experiment hydrogen-implanted silicon wafers were deposited with two to four microns low-temperature plasma-enhanced tetraethoxysilane (TEOS). The wafers were then bonded to a second wafer, which had been coated with a spin-on polymer. The bonded pairs were heated to the ion-cut temperature resulting in the transfer of a 400 nm layer silicon. The polymer enabled the bonding of an unprocessed silicon wafer to the as-deposited TEOS with a microsurface roughness larger than 10 nm, while the TEOS provided sufficient stiffness for ion cut. In the second experiment, an intermediate transfer wafer was patterned and vias were etched through the wafer using a 25% tetramethylammonium hydroxide (TMAH) solution and nitride as masking material. The nitride was then stripped using dilute hydrofluoric acid (HF). The transfer wafer was then bonded to an oxidized (100 nm) hydrogen-implanted silicon wafer. After ion-cut annealing a silicon-on-insulator (SOI) wafer was produced on the transfer wafer. The thin silicon layer of the SOI structure was then bonded to a third wafer using a spin-on polymer as the bonding material. The sacrificial oxide layer was then etched away in HF, freeing the thin silicon from the transfer wafer. The result produced a thin silicon-on-polymer structure bonded to the third wafer. These results demonstrate the feasibility of transferring a silicon layer from a wafer to a second intermediate “transfer” or “universal” reusable substrate. The second transfer step allows the thin silicon layer to be subsequently bonded to a potential third device wafer followed by debonding of the transfer wafer creating stacked three-dimensional structures.     

InP/Si键合界面热应力分析

从理论上分析了键合热应力产生的原因,在此基础上,采用双层条状金属热应力模型讨论InP/Si键合过程中应力的大小及分布情况.结果表明, 由剪切应力和晶片弯矩决定的界面正应力是晶片中心区域大面积键合失败的主要原因,同时InP/Si键合合适的退火温度应该在250～300 ℃.最后在300 ℃退火条件下很好地实现了InP/Si键合,界面几乎没有气泡,有效键合面积超过90%.     

High-quality crystalline layer transfer from a silicon-on-insulator substrate onto a sapphire substrate using wafer bonding

We demonstrate layer transfer of 150 nm of Si from a 200-mm, silicon-on-insulator (SOI) substrate onto a sapphire substrate using low-temperature wafer bonding (T=150°C). The crystalline quality and the thermal stability of the transferred Si layer were characterized by x-ray diffraction (XRD). A broadening of the (004) Si peak is observed only for anneal temperatures T_A≥800°C, indicating some degradation of the crystalline quality of the transferred Si film above these temperatures. The measured electron Hall mobility in the bonded Si layer is comparable to bulk silicon for T_A≤800°C, indicating excellent material quality.     

Temperature and duration effects on microstructure evolution during copper wafer bonding

Interfacial morphologies during Cu wafer bonding at bonding temperatures of 300–400°C for 30 min followed by an optional 30-min or 60-min nitrogen anneal were investigated by means of transmission electron microscopy (TEM). Results showed that increased bonding temperature or increased annealing duration improved the bonding quality. Wafers bonded at 400°C for 30 min followed by nitrogen annealing at 400°C for 30 min, and wafers bonded at 350°C for 30 min followed by nitrogen annealing at 350°C for 60 min achieve the same excellent bonding quality.     

我国半导体硅材料的发展现状

叙述了我国半导体硅材料的发展现状及与国外相比存在的差距 ,提出了发展我国硅材料的一些建议     

HgCdTe on Si: Present status and novel buffer layer concepts

We discuss buffer-layer concepts for the synthesis of low defect-density HgCdTe epilayers on Si for both hybrid and monolithically integrated, infrared focal-plane arrays (IRFPAa). The primary technical problems to overcome include the 19% lattice-parameter mismatch between HgCdTe and Si, and the (211)B surface orientation required for molecular-beam epitaxy (MBE), the growth technique of choice for HgCdTe. We provide a general overview of IRFPAs, motivations for realizing HgCdTe on Si, the current state-of-the-art parameters as a baseline, and three novel buffer-layer concepts and technologies based on (1) obedient GeSi films on SiO₂, (2) wafer bonding, and (3) chalcogenides.     

Si/Si键合结构的电学性质测量及模拟

研究Si／Si键合的电学性质对于界面研究和微电子器件的制备有着重要意义。分析了亲水处理方法键合的不同Si／Si键合结构的I—V特性,然后用SOS模型对n—Si／n—Si的C—V特性做了计算机辅助模拟,并和实际C—V曲线比较得出了平带电压VFB和界面态密度Din,这些结果对于键合的界面性质的了解和研究都是有意义的。     

Transfer of semiconductor and oxide films by wafer bonding and layer cutting

Material integration by wafer bonding and layer transfer is one of the main approaches to increase functionality of semiconductor devices and to enhance integrated circuits (IC) performance. Even though most mismatches such as different lattice constants betweeen bonding materials present no obstacle for wafer direct bonding, thermal stresses caused by thermal mismatches must be minimized by low temperature bonding to avoid debonding, sliding or cracking. In order to achieve a strong bond at low temperatures, two approaches may be adopted: 1) Bonding at room temperature by hydrogen bonding of OH, NH, or FH terminated surfaces followed by polymerization to form covalent bonds. Within this approach the key is to remove the by-products of the reaction at the bonding interface. 2) Direct formation of a covalent bond between clean surfaces without adsorbents in ultra high vacuum conditions. Low temperature bonding allows bonding processed wafers for technology integration. Layer transfer requires uniform thinning of one wafer of a bonded pair. The most promising technology involves a buried embrittled region by hydrogen implantation. A layer with a thickness corresponding to the hydrogen implantation depth is then transferred onto a bonded desired substrate by either splitting due to internal gas pressure or by forced peeling as long as the bonding energy is higher than the fracture energy in the embrittled region at the layer transfer temperature. This approach is quite generic in nature and may be applied to almost all materials. We have found that B+H co-implantation and/or H implantation at high temperatures can significantly lower the splitting temperature. However, the wafer temperature during H implantation has to be within a temperature window that is specific for each material. The experimentally determined temperature windows for some semiconductors and single crystalline oxides will be given.     

Optical and crystallographic properties of high perfection InP grown on Si(111)

The growth of InP by low-pressure metalorganic chemical vapor deposition on vicinal Si(111), misoriented 3° toward [1-10], is reported. Antiphase domain-free InP is obtained without any preannealing of the Si substrate. Crystallographic, optical, and electrical properties of the layers are significantly improved as compared to the best reported InP grown on Si(001). The high structural perfection is demonstrated by a full width at half maximum (FWHM) of 121 arcs for the (111) Bragg reflex of InP (thickness = 3.4 μm) as obtained by double crystal x-ray diffraction. The low-temperature photoluminescence (PL) efficiency is 70% of that of homoepitaxially grown InP layers. The FWHM of the near-gap PL peak is only 2.7 meV as compared to 4.5 meV of the best material grown on Si(001). For the first time, InP:Fe layers with semi-insulating characteristics (ρ > 3 × 10⁷ Ω-cm) have been grown by compensating the low residual background doping using ferrocene. Semi-insulating layers are prerequisite for any device application at ultrahigh frequencies.     

Room temperature wafer bonding of silicon, oxidized silicon, and crystalline quartz

The use of plasma immersion as preparation for room temperature wafer bonding has been investigated. Silicon wafers have been successfully bonded at room temperature after exposure to oxygen or argon plasma. Oxidized silicon wafers and crystalline quartz have been bonded after exposure to oxygen plasma. The bonded interfaces exhibit very high surface energies, comparable to what can be achieved with annealing steps in the range of 600–800°C using normal wet chemical activation before bonding. The high mechanical stability obtained after bonding at room temperature is explained by an increased dynamic in water removal from the bonded interface allowing covalent bonds to be formed. Electrical measurements were used to investigate the usefulness of plasma bonded interfaces for electronic devices.     

Capacitance-Voltage characteristics of metal-insulator-semiconductor diodes with S passivation and Si interface control layers on GaAs and InP

GaAs and InP surfaces have been prepared by gas-phase and liquid-phase polysulfide passivation techniques followed by the deposition of Si interface control layers (ICLs) by e-beam evaporation. For GaAs surfaces, the performance of an ICL consisting of 1.5 nm Si on top of 0.5 nm of Ge has also been evaluated. Metal-insulator-semiconductor diodes with aluminum top electrodes were fabricated on these surfaces using silicon nitride deposited by a remote plasma-enhanced chemical vapor technique or silicon dioxide deposited by a conventional direct plasma-enhanced chemical vapor deposition technique. The quality of the interfaces was analyzed by capacitance-voltage (C-V) measurements and the interface state densities D_it were deduced from the C-V data using the high-low method. Values as low as 1.5 × 10¹² eV⁻¹cm⁻² were obtained for polysulfide-passivated GaAs surfaces with a Ge-Si or Si ICL, the lowest ever demonstrated using the high-low method for an ex-situ technique not involving GaAs epitaxy. For InP, the Si ICL does not reduce D_it below that of 2 × 10¹² eV⁻¹ cm ⁻² that was obtained for the polysulfide passivated surface. The Si ICL produces an interface that degrades more slowly on exposure to air for both GaAs and InP.     

Transfer of n-type GaSb onto GaAs substrate by hydrogen implantation and wafer bonding

Many GaSb devices would greatly benefit from the availability of a semi-insulating substrate. Since semi-insulating GaSb is not currently available, the formation of thin GaSb layers through wafer bonding and tranfer onto a semi-insulating GaAs substrate was investigated. GaSb-on-insulator structures, formed on GaAs substrates, were realized by the ion-cut process using H⁺ ions. Blistering, bonding and layer splitting phenomena were studied to optimize the ion dose and the process window. Bonded structures of thin layers of GaSb bonded to GaAs wafers were formed using a borosilicate glass (BSG) layer. The transferred GaSb layers were characterized by atomic force microscopy, MeV helium ion channeling and high-resolution x-ray diffractometry. The transferred film possessed a narrow x-ray linewidth of about 140 arcsec indicating improved crystalline quality over the direct growth of GaSb on GaAs.     

Positron annihilation spectroscopy: Applications to Si,ZnO, and multilayer semiconductor structures

The potential of positron annihilation spectroscopy (PAS) for defect characterization at the atomic scale in semiconductors is demonstrated for Si, ZnO, and multilayer structures, such as an AlGaAs/GaAs solar cell. The types of defects discussed include: i) vacancy complexes, oxygen impurities and dopants, ii) the influence of cooling rates on spatial non-uniformities in defects, and iii) characterization of buried interfaces. In sev-eral instances, the results of the PAS investigations are correlated with data from other established semiconductor characterization techniques.     

Effects of generation/recombination processes and leakage current through interfacial “punctures” on electrical characterization of unipolar directly bonded semiconductor structures

Numerical simulations have been performed to analyze the influence of generation/recombination processes and leakage current through “interfacial” punctures on the results of electrical characterization of unipolar directly bonded semiconductor junctions by the methods previously proposed by the present author [Mater. Sci. Semicond. Process. 4 (2001) 177]. Physical quantities that characterize the electrical state of the bonded junction and phenomena brought about by the generation/recombination processes in the junction (static and high-frequency conduction due to minority carriers, influence of generation/recombination processes on the interfacial charge, etc.) are discussed.     

ECR plasma etch fabrication of C-doped base InGaAs/InP DHBT structures: A comparison of CH4/H2/Ar vs BCl3/N2 plasma etch chemistries

We compare ECR plasma etch fabrication of self-aligned thin emitter carbondoped base InGaAs/InP DHBT structures using either CH₄/H₂/Ar or BCl₃/N₂ etch chemistries. Detrimental hydrogen passivation of the carbon doping in the base region of our structure during CH₄/H₂/Ar dry etching of the emitter region is observed. Initial conductivity is not recovered with annealing up to a temperature of 500°C. This passivation is not due to damage from the dry etching or from the MOMBE growth process, since DHBT structures which are ECR plasma etched in BCl₃/N₂ have the same electrical characteristics as wet etched controls. It is due to hydrogen implantation from the plasma exposure. This is supported with secondary ion mass spectroscopy profiles of structures which are etched in CH₄/D₂/Ar showing an accumulation of deuterium in the C-doped base region.