A State-of-the-art Elliptic Curve Cryptographic Processor Operating in the Frequency Domain

We propose a novel area/time efficient elliptic curve cryptography (ECC) processor architecture which performs all finite field arithmetic operations in the discrete Fourier domain. The proposed architecture utilizes a class of optimal extension fields (OEF) GF(q ^m ) where the field characteristic is a Mersenne prime q = 2 ⁿ  − 1 and m = n. The main advantage of our architecture is that it achieves extension field modular multiplication in the discrete Fourier domain with only a linear number of base field GF(q) multiplications in addition to a quadratic number of simpler operations such as addition and bitwise rotation. We achieve an area between 25k and 50k equivalent gates for the implementations over OEFs of size 169, 289 and 361 bits. With its low area and high speed, the proposed architecture is well suited for ECC in small device environments such as sensor networks. The work at hand presents the first hardware implementation of a frequency domain multiplier suitable for ECC and the first hardware implementation of ECC in the frequency domain.

Hardware Organization to Achieve High-Speed Elliptic Curve Cryptography for Mobile Devices

Elliptic curve cryptography (ECC) is recognized as a fast cryptography system and has many applications in security systems. In this paper, a novel sharing scheme is proposed to significantly reduce the number of field multiplications and the usage of lookup tables, providing high speed operations for both hardware and software realizations.

New Bit-Parallel Systolic Architectures for Computing Multiplication,Multiplicative Inversion and Division in GF(2<Superscript>m</Superscript>) Under Polynomial Basis and Normal Basis Representations

A new bit-parallel systolic multiplier over GF(2^m) under the polynomial basis and normal basis is proposed. This new circuit is constructed by m ² identical cells, each of which consists of one two-input AND gate, one three-input XOR gate and five 1-bit latches. Especially, the proposed architecture is without the basis conversion as compared to the well-known multipliers with the redundant representation. With this proposed multiplier, a parallel-in parallel-out systolic array has also been developed for computing inversion and division over GF(2^m). The proposed architectures are well suited to VLSI systems due to their regular interconnection pattern and modular structure.

Maximize Parallelism Minimize Overhead for Nested Loops via Loop Striping

Majority of scientific and Digital Signal Processing (DSP) applications are recursive or iterative. Transformation techniques are generally applied to increase parallelism for these nested loops. Most of the existing loop transformation techniques either can not achieve maximum parallelism, or can achieve maximum parallelism but with complicated loop bounds and loop indexes calculations. This paper proposes a new technique, loop striping, that can maximize parallelism while maintaining the original row-wise execution sequence with minimum overhead. Loop striping groups iterations into stripes, where all iterations in a stripe are independent and can be executed in parallel. Theorems and efficient algorithms are proposed for loop striping transformations. The experimental results show that loop striping always achieves better iteration period than software pipelining and loop unfolding, improving average iteration period by 50 and 54% respectively.

The Negative Two’s Complement Number System

The two’s complement fractional fixed-point number system is widely used to implement digital signal processing on VLSI chips. It has a range of values from −1 to one least significant bit below +1. Either the multiplication of −1 • −1 or taking the absolute value of −1 produces a result (+1) that cannot be represented. A new system, the negative two’s complement number system, is described here that has a range of one least significant bit above −1 to +1 which eliminates the problem. This paper presents the new number system and describes algorithms for the basic arithmetic operations.

New and Improved Architectures for Montgomery Modular Multiplication

In this paper an improved Montgomery multiplier, based on modified four-to-two carry-save adders (CSAs) to reduce critical path delay, is presented. Instead of implementing four-to-two CSA using two levels of carry-save logic, authors propose a modified four-to-two CSA using only one level of carry-save logic taking advantage of pre-computed input values. Also, a new bit-sliced, unified and scalable Montgomery multiplier architecture, applicable for both RSA and ECC (Elliptic Curve Cryptography), is proposed. In the existing word-based scalable multiplier architectures, some processing elements (PEs) do not perform useful computation during the last pipeline cycle when the precision is not equal to an exact multiple of the word size, like in ECC. This intrinsic limitation requires a few extra clock cycles to operate on operand lengths which are not powers of 2. The proposed architecture eliminates the need for extra clock cycles by reconfiguring the design at bit-level and hence can operate on any operand length, limited only by memory and control constraints. It requires 2∼15% fewer clock cycles than the existing architectures for key lengths of interest in RSA and 11∼18% for binary fields and 10∼14% for prime fields in case of ECC. An FPGA implementation of the proposed architecture shows that it can perform 1,024-bit modular exponentiation in about 15 ms which is better than that by the existing multiplier architectures.

Design and Implementation of a High-Performance and Complexity-Effective VLIW DSP for Multimedia Applications

This paper presents the design and implementation of a novel VLIW digital signal processor (DSP) for multimedia applications. The DSP core embodies a distributed & ping-pong register file, which saves 76.8% silicon area and improves 46.9% access time of centralized ones found in most VLIW processors by restricting its access patterns. However, it still has comparable performance (estimated in cycles) with state-of-the-art DSP for multimedia applications. A hierarchical instruction encoding scheme is also adopted to reduce the program sizes to 24.1∼26.0%. The DSP has been fabricated in the UMC 0.13 μm 1P8M Copper Logic Process, and it can operate at 333 MHz while consuming 189 mW power. The core size is 3.2 × 3.15 mm² including 160 KB on-chip SRAM.

Fast PWM-Based Test for High Resolution ΣΔ ADCs

This work describes a novel test strategy that uses digital stimuli for cheap, fast, though accurate, testing of high resolution ΣΔ ADCs. Simulations and measurements showed a discrimination threshold on specification parameters up to −90 dBc. The proposed method helps to reduce the cost of ADC production test, to extend test coverage and to enable built-in self-test and test-based self-calibration.

Isolation of Failing Scan Cells through Convolutional Test Response Compaction

This paper describes a non-recursive fault diagnosis technique for scan-based designs with convolutional test response compaction. The proposed approach allows a time-efficient and accurate identification of failing scan cells using Gauss–Jordan elimination method.

Wireless Channel Tracking Based on Optimum Predictive LMS

A frequency domain analysis is presented to optimize the Predictive Least Mean Square (PLMS) algorithm used for wireless channel tracking. Simulation results show that the PLMS offers significant improvement in tracking performance compared to that of the conventional LMS based method. The algorithm parameters should be carefully selected in order to gain such improvements. The objective of this paper is to use frequency domain analysis to determine an expression for the Mean Square Tracking Error (MSTE) and use it to obtain the optimum PLMS algorithm parameters such as step size (μ) and smoothing constant (θ) with numerical optimization methods.

FPGA Implementation of Integer Transform and Quantizer for H.264 Encoder

This paper deals with the process of Transformation and Quantization that is carried out on each inter-predicted residual block in a video encoding process and their reduced complexity hardware implementation. H.264/AVC utilizes 4 × 4 integer transform, which is derived from the 4 × 4 DCT. We propose, a reduced complexity algorithm and a pipelined structure for the Core forward integer transform module. A multiplier-less architecture is realized with less number of shifts and adds compared to existing works. The corresponding inverse transform is exactly reversible. Each of the transformed coefficients is quantized by a scalar quantizer. The quantization step size can be varied from macroblock to macroblock. The proposed unified pipelined architecture outperforms many recent implementations in terms of gate count and is capable of processing a 4 × 4 residual block in 4 clock cycles.

O<Superscript>3</Superscript>BPSK-based Linear Decorrelating Detector for Asynchronous DS/CDMA Systems over Frequency-Selective Rayleigh Fading Channels

In this paper, a convenient signaling scheme, called orthogonal on–off BPSK (O³BPSK), along with a simple one-shot linear decorrelating detector (LDD) and a whitening Rake bank, is proposed for near–far resistant detection in asynchronous DS/CDMA systems. Based on the maximum multi-path spreading delay, a minimum duration of “off” is suggested, during which the temporally adjacent bits (TABs) that contain multi-user interference (MUI) and inter-symbol interference (ISI) from different users at the receiver are decoupled. The O³BPSK signaling scheme is combined with the whitening Rake receiver to preserve multi-path diversity gain in multi-path fading CDMA channels. The scheme offers low complexity, no detection delay, near–far resistance, and compensation for fading channels.

Cross-layer Routing Design in Cognitive Radio Networks by Colored Multigraph Model

In this paper, the cross-layer design routing in cognitive radio(CR) networks is studied. We propose a colored multigraph based model for the temporarily available spectrum bands, called spectrum holes in this paper. Based on this colored multigraph model, a polynomial time algorithm with complexity O(n ²) is also proposed to develop a routing and interface assignment, where n is the number of nodes in a CR network. Our algorithm optimizes the hop number of routing, meanwhile, the adjacent hop interference (AHI) is also optimized locally.

Negative Save Sign Extension for Multi-term Adders and Multipliers

This paper outlines a new sign extension technique for use in carry save adder trees that reduces the computational complexity. The “Negative Save” technique presented is a modification to the Baugh–Wooley sign extension technique developed for array multipliers. Applying this sign extension technique to both parallel adder and multiplier partial product structures reduces the hardware required. The speed of the resulting structures is also improved.

Energy-Aware Georouting with Guaranteed Delivery in Wireless Sensor Networks with Obstacles

We propose, end-to-end (EtE), a novel EtE localized routing protocol for wireless sensor networks that is energy-efficient and guarantees delivery. To forward a packet, a node s in graph G computes the cost of the energy weighted shortest path (SP) between s and each of its neighbors in the forward direction towards the destination which minimizes the ratio of the cost of the SP to the progress (reduction in distance towards the destination). It then sends the message to the first node on the SP from s to x: say node x′. Node x′ restarts the same greedy routing process until the destination is reached or an obstacle is encountered and the routing fails. To recover from the latter scenario, local minima trap, our algorithm invokes an energy-aware Face routing that guarantees delivery. Our work is the first to optimize energy consumption of Face routing. It works as follows. First, it builds a connected dominating set from graph G, second it computes its Gabriel graph to obtain the planar graph G′. Face routing is invoked and applied to G′ only to determine which edges to follow in the recovery process. On each edge, greedy routing is applied. This two-phase (greedy–Face) EtE routing process reiterates until the final destination is reached. Simulation results show that EtE outperforms several existing geographical routing on energy consumption metric and delivery rate. Moreover, we prove that the computed path length and the total energy of the path are constant factors of the optimal for dense networks.

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Coding Schemes for Crisscross Error Patterns

This paper addresses two coding schemes which can handle emerging errors with crisscross patterns. First, a code with maximum rank distance, so-called Rank-Codes, is described and a modified Berlekamp–Massey algorithm is provided. Secondly, a Permutation Code based coding scheme for crisscross error patterns is presented. The influence of different types of noise are also discussed.

A New Cost Function for Air Quality Modeling

In this paper a new Back-Propagation (BP) algorithm cost function is appropriately studied for the modeling of air pollution time series. The underlying idea is that of modifying the error definition in order to improve the capabilities of this kind of models to forecast episodes of poor air quality. The proposed error definition can be regarded as a generalization of the traditional squared error cost function thanks to the presence of a parameter α which allows to obtain the ordinary BP as a special case when α = 1. A criterion for choosing this parameter is stated based on setting a-priori a maximum level of allowable false alarms. The goodness of the proposed approach is assessed by means of case studies both on synthetic and measured air quality data.

Performance of MIMO System Through Nakagami Fading Channel with Arbitrary Fading Parameters

In this paper, the analytical and simulation results of the bit error rate (BER) performance for a multiple-input multiple-output (MIMO) system with an arbitrary number of transmit and receive antennas are developed for the uplink transmission. The fading channel is assumed to follow Nakagami-m distribution with correlation among branches. The BER is expressed in terms of Lauricella’s multivariate hypergeometric function for both independent and correlated antenna branches for BPSK system.

Robust Recursive <Emphasis Type="Italic">H</Emphasis><Subscript>∞</Subscript> DOA Estimation Using Spatial Forward Linear Predictor

This letter deals with robust direction of arrival (DOA) estimation based on the recursive H _∞ algorithm for the forward linear predictor. This recursive H _∞ criterion is different from traditional H ₂ estimation criterions which minimize the squared prediction error. The forward linear predictor with recursive H _∞ algorithm is a worst case optimization approach, which minimizes the total effect of the worst disturbances on the prediction error. Some computer simulation examples are provided for illustrating the effectiveness of the proposed method.

Applying Data Mapping Techniques to Vector DSPs

Vector digital signal processors (DSPs) offer a good performance to power consumption ratio. Therefore, they are suitable for mobile devices in software defined radio applications. These vector DSPs require input algorithms with vector operations. The performance of vectorized algorithms to a great extent depends on the distribution of data on vector elements. Traditional algorithms for vectorization focus on the extraction of parallelism from a program; we propose an analysis tool that focuses on the selection of an efficient dynamic data mapping for vector DSPs. We transferred Garcia’s communication parallelism graph (Garcia et al., IEEE Trans Parallel Distrib Syst 12: 416–431, 2001) for distributed memory multiprocessor systems to vector DSPs. By alternating the representation of two-dimensional data distributions and the cost models, we are able to determine a dynamic mapping of data on vector elements on the Embedded Vector Processor (EVP) (van Berkel et al., Proceedings of the 2004 software-defined radio technical conference SDR’04, 2004). Additionally, we propose a new efficient algorithm for processing the graph representation that operates in two steps. We demonstrate the capabilities of our tool by describing the vectorization of some MIMO OFDM algorithms.