Submicron NbN/MgO/NbN Josephson tunnel junctions and theirapplication to the logic circuit

An improved fabrication process for submicron NbN/MgO/NbN Josephson tunnel junctions has been developed. By introducing a contact layer between the junction and the wiring layer, the critical current of the wiring above the junction was considerably enhanced. A logic circuit composed of four-junction logic gates was fabricated using 0.9-μm-square junctions. Logic delay measurement was successfully achieved with a minimum logic delay of 3.6 ps/gate and a wide operating margin of ±17% within 50 gates     

Josephson dual rail two-bit adder circuit utilizing magnetically coupled OR-AND gates

A novel Josephson logic gate called the asymmetrical interferometer device (AID) is presented. It is composed of a pair of asymmetrical interferometers whose outputs are injected into a single junction. The interferometers are individually operated as two input OR and the single junction is worked as AND.(A + B) (C + D)operation is accomplished by only one AID gate. They have a serial fan-in capability due to their magnetic coupling scheme. The gate size is reduced by half, compared with the previous current injection logic (CIL) gate. With these AID gates, a high-speed two-bit dual rail adder circuit is configured, which provides the logic circuits performing with both true and complement inputs and without any timing circuits. The AID gate fabricated by standard 5-µm Pb-alloy technology showed a wide margin over ±20 percent that was in good agreement with statically designed characteristics. Experimental adder operation was also successfully performed.     

A DC-powered Josephson logic family that uses hybrid unlatchingflip-flop logic elements (Huffles)

This paper describes the development of a dc-powered Josephson logic family that uses hybrid unlatching flip-flop logic elements (Huffles). The Huffle circuit used in this study is modified by adding a parallel resistor to the original Hebard-type Huffle circuit. Analysis of the circuit's operation shows that the undesirable hung-up phenomena are prevented by this modification. Based on the result of the analysis, the circuit's parameters are derived and a typical operating margin of ±26% is obtained. Besides AND/OR operations using a threshold logic operation, two-input exclusive OR (XOR), two-input multiplexor (MUX), and three-input majority (MAJ) operations are realized using a Huffle gate in which 2-Josephson-interferometers (2JI) in the standard Huffle gate are replaced by stacked-2JI's. Thus, a Huffle logic family, formed from NOT, AND, OR, XOR, MUX, MAJ, and flip-flop (FF), are constructed. By using this Huffle logic family, a 6-b arithmetic logic operating unit (ALU), a 6-b analog-to-digital converter (ADC), and a 6-b gray-to-binary converter (GBC) have been successfully operated. During high-speed testing, a 1-b comparator was operated up to an input bandwidth of 6 GHz     

Josephson-logic devices and circuits

A review of the recent advances in Josephson logic devices and circuits is presented. The Josephson junction is almost an ideal digital switch exhibiting very abrupt threshold, ultra-high switching speeds (∼10 ps), and very low power dissipation (∼1 µW). Logic devices based on the Josephson junctions combine Josephson junctions with other circuit elements to provide isolation to the input signals as well as to provide higher gain than a single junction. These devices can be classified into two groups, the first group uses magnetically coupled SQUID's (Superconducting QUantum Interference Devices) to provide isolation, whereas the second group of circuits utilizes the high-resistance state of a Josephson junction in series with the signal input to provide isolation. Logic circuits based on these two isolation Schemes are compared. In both schemes, higher gains are achieved by the use of either multiple Josephson junctions in parallel or a buffer stage. The buffer stage is a Current-Injection Device (CID) which provides gain and the AND function between the two signal currents injected into it. Some of the unique features of Josephson logic circuits such as terminated superconducting transmission lines, ac power supply, Timed Inverter, and Latch circuits are also examined. The dynamic behavior of the Josephson junctions is modeled by very simple equivalent circuits. The computer simulations based on these models are compared with experiments and found to be in excellent agreement. A family of experimental logic circuits has been designed and experimentally tested using 2.5-µm minimum feature size. These circuits have fully loaded logic delays of about 40 ps/gate and power dissipation of about 4 µW/gate. The gate delays and power-delay products are compared with leading semiconductor technologies.     

Feasibility of an ultra-high-speed Josephson multiplier

The authors discuss the design, fabrication, and evaluation of a Josephson multiplier model featuring all-niobium junctions. They designed a 16-bit /spl times/ 16-bit parallel multiplier and fabricated its critical path model consisting of 828 gates. The circuit was designed using modified variable threshold logic (MVTL) OR-gates and single-junction AND gates. These gates consisted of Nb/AlO/SUB x//Nb Josephson junctions, Nb wiring, Mo resistors, and SiO/SUB 2/ insulators. Both the minimum linewidth and junction diameter were 2.5 /spl mu/m. The observed multiplication time using the critical path model was 1.1 ns. The propagation delay due to the interconnecting wiring was estimated to be 0.20 ns, and the longest path of the circuit consisted of 103 gates. Thus the average gate delay in the circuit was estimated to be 8.7 ps/gate. These results point to the possibility of an ultra high-speed multiplier, about five times faster than any semiconductor device.     

Complementary Josephson-junction circuit: a fast flip-flop and logic gate

A logic circuit with Josephson junctions has been developed that operates as logic gate or as a flip-flop. Despite the latching-type characteristic of the Josephson tunnel junction, the complementary logic circuit is nonlatching. The test circuit has a power dissipation of 16.4 ?W and a signal risetime of approximately 60 ps has been measured.     

Niobium-based integrated circuit technologies

Metallurgical and electrical properties of Nb and NbN films for use as Josephson junction electrodes and wiring layers are investigated. The crystallographic and superconducting properties necessary for Nb-based integrated circuit processes are clarified. Tunnel barrier structures of NbN-Nb oxide-NbN (Pb alloy) and Nb-Al oxide-Nb Josephson junctions have been analyzed and correlated with junction characteristics and critical current uniformity. It was found that the surface structure of a base electrode should be smooth to ensure that Josephson junctions have low leakage current and uniform critical current distribution. New types of Josephson junctions with artificial tunnel barriers such as amorphous Si or Mg oxide are reviewed. A variety of Josephson junction structures or processes have been developed for Nb-based Josephson integrated circuits in order to improve circuit performance. These include junction miniaturization, planarization, and stacked junction structures. These structures are mainly intended for Nb-Al oxide-Nb Josephson circuits. The Nb-Al oxide-Nb Josephson junction technology is by far the most advanced and has been used in logic and memory circuits, for example a 4-bit×4-bit parallel multiplier, a Josephson logic gate array, a 16-bit arithmetic logic unit, a 4-bit microprocessor, and 1-kb and 4-kb memory circuits     

Ultrahigh-speed logic gate family with Nb/Al-AlOx/Nb Josephson junctions

The modified variable threshold logic (MVTL) OR gate has a wide operating margin and occupies a small area, so that a gate family using this OR gate is suitable for LSI logic circuits. This paper describes the design, fabrication process, and evaluation of the MVTL gate family. The gate family is composed of OR, AND, and 2/3 MAJORITY gates. The gates were made with all refractory material including Nb/ Al-AlOx/Nb junctions and Mo resistors, and they were patterned by using a reactive ion etching (RIE) technique. The logic delay of the gate was measured with a Josephson sampler. The minimum delays for OR, AND, and 2/3 MAJORITY gates were 5.6, 16, and 21 ps/gate, respectively.     

A Josephson adder employing high-gain direct-coupled logic gate

A wide-margin adder with a simple configuration employing high-gain direct-coupled logic gates (HDCL's) was studied. A wide-margin half-adder circuit, consisting of a single junction and three HDCL buffer gates, is proposed. In order to obtain a wide-margin circuit, gates were designed to be protective against a noise signal. The experimental circuit fabricated by a conventional Pb alloy Josephson technology with 5-µm minimum line width has shown wide-margin (more than a ± 30-percent bias signal margin) characteristics, as predicted by a computer simulation. This paper also demonstrates that the adder can be simply modified into a wide-margin full adder with a simple configuration by connecting an additional single junction and a buffer gate for a carry signal.     

An experimental multiplier circuit based on superconducting Josephson devices

This paper describes the design, testing, and operation of a 4-bit multiplier circuit based on Josephson tunneling logic (JTL) gates. The algorithm adopted was that of a simple serial 4-bit multiplier consisting of a 4-bit adder with ripple carry, together with a four phase, 8-bit accumulator shift register. The circuit, fabricated using a 25-/spl mu/m minimum linewidth technology, operated with a minimum cycle time of 6.67 ns (a limit imposed by the external test equipment) giving a 4-bit multiplication time of 27 ns with an average power dissipation of 35 /spl mu/W per logic gate. With better external pulse generators, or internal Josephson junction generators, the present circuit has been simulated to operate with a 3.0-ns cycle giving a 4-bit multiplication time of 12 ns.     

A self-aligned gate III-V heterostructure FET process forultrahigh-speed digital and mixed analog/digital LSI/VLSI circuits

A planar ion-implanted self-aligned gate process for the fabrication of high-speed digital and mixed analog/digital LSI/VLSI integrated circuits is reported. A 4-b analog-to-digital converter, a 2500-gate 8×8 multiplier/accumulator, and a 4500-gate 16×16 complex multiplier have been demonstrated using enhancement-mode n⁺ -(Al,Ga)As/MODFETs, superlattice MODFETs, and doped channel heterostructure field-effect transistors (FETs) whose epitaxial layers were grown by molecular-beam epitaxy. With nominal 1-μm gate-length devices, direct-coupled FET logic ring oscillators with realistic circuit structures have propagation delays of 30 ps/stage at a power dissipation of 1.2 mW/stage. In LSI circuit operation, these gates have delays of 89 ps/gate at a power dissipation of 1.38 mW/gate when loaded with an average fan-out of 2.5 gates and about 1000 μm of high-density interconnects. High-performance voltage comparator circuits operated at sampling rates greater than 2.5 GHz at Nyquist analog input rates and with static hysteresis of less than 1 mV at room temperature. Fully functional 4-b analog-to-digital circuits operating at frequencies up to 2 GHz were obtained     

Optical input/output interface system for Josephson junctionintegrated circuits

An optical input/output interface system for a Josephson junction integrated circuit is fabricated and tested. The system consists of a superconducting optical detector, a dc powered Josephson circuit, a dc powered Josephson high voltage circuit, a liquid-He-cooled semiconductor amplifier, and a liquid-He-cooled semiconductor laser. Features of the system are use of an ultrathin NbN film for the optical detector and adoption of the dc powered Josephson circuits for logic operation circuits. Correct optical output signal is detected by a liquid-He-cooled semiconductor photodiode. The optical input/output interface has the advantage of low heat penetration and low crosstalk compared to the interface using conventional coaxial lines. Moreover, dc powered Josephson circuits have an advantage of low crosstalk from power supply lines compared to conventional Josephson circuits, which are driven by ac supply current     

3.0 ps switching operation in all-Nb Josephson logic gates

A high-speed logic delay of 3.0 ps/gate in a resistor-coupled Josephson logic (RCL) gate chain is attained using a new Nb Josephson integrated circuit technology. Lift-off, Nb stress control and planarisation techniques are used for fabricating high-quality Nb/AlOx/Nb trilayer junctions and reliable Nb wiring. Pd, which is stable during etching, is used as a resistor material.     

High-temperature operation of oxide SFQ-circuit-elements

Single flux quantum (SFQ) circuit components such as an SFQ-dc converter and a confluence buffer have been fabricated by using an YBa/sub 2/Cu/sub 3/O/sub 7-/spl delta// ramp-edge junction technology and their logic operations at temperatures up to near 60 K were investigated. The SFQ-dc converter was correctly operated in a wide temperature range from 4.2 K to 56 K and found to be useful for detecting output signals from other SFQ circuit components at any operating temperatures. The basic function that a signal from either of two input Josephson transmission lines (JTLs) was transmitted to an output JTL was confirmed for the confluence buffer and finite operating margins were obtained at temperatures from 42 K to 61 K. The narrowest margin of dc supply current obtained at temperatures from 55 K to 60 K was /spl plusmn/20% and was consistent with the simulation. Margin reduction due to thermal noise was also evaluated. According to the analytical calculation, the operating margin to keep the bit-error rate less than 10/sup -5/ was as large as /spl plusmn/20% even at 50 K when the value of junction critical-current I/sub c/ was kept near 0.4 mA.     

High-speed testing of Josephson logic circuits by an on-chip signal-pattern generator

We have developed an on-chip signal-pattern generator (SPG) for high-speed testing of latching-type Josephson logic circuits. The basis of the SPG is using a feedback shift register, in which the complement output of the last-stage LATCH gate (a D flip-flop) is fed back to the first-stage LATCH gate. Since the SPG consists of only LATCH gates and requires no external input signal, the design and high-speed operation are greatly simplified. We performed a high-speed measurement of the 1-bit SPG and found that the SPG has the potential to operate at a speed of more than 4.6 GHz. We also demonstrated a high-speed testing of a 2-bit logic circuit with the 2-bit SPG up to a clock frequency of 1 GHz.     

A high-speed four-bit full adder with a resistor coupled Josephson logic

A four-bit full adder circuit implemented in resistor coupled Josephson logic (RCJL) has been designed and successfully tested with 173-ps critical path delay. The full adder circuit uses dual rail logic with emphasis on high-speed operation. An experimental four-bit adder circuit was fabricated using lead-alloy Josephson IC technology with a 5-µm minimum feature size and a 7-µm minimum junction diameter. The circuit consists of 80 devices with 264 junctions. The minimum critical path delay for the ripple carry adder was measured to be 173 ps/4 bits. This result demonstrates the RCJL potential for high-speed digital applications.     

A 2.5-ns, 40-mW, 4/spl times/4 GaAs multiplier in two's complement mode

The design, fabrication, and testing of a very fast GaAs 4/spl times/4 parallel multiplier based on the modified Booth's algorithm are described. The multiplier includes novel transfer logic cells and is the first high-performance GaAs two's-complement multiplier. The circuit, fabricated with 1-/spl mu/m aligned process, exhibits a multiplication time of 2.5 ns (typical 2.7 ns) on the critical path, with a 40-mW power consumption. Per gate the average delay is 120 ps, at 0.2-mW dissipation.     

An experimental nanosecond Josephson 1K RAM using 5-µm Pb-alloy technology

A high-speed fully decoded Josephson 1K RAM has been designed and tested. Several bits of the 1K RAM were successfully operated with a typical read access time of 3.3 ns and associated power dissipation of 2.0 mW. The chip, containing about 10 000 Josephson junctions, was fabricated using 5-µm Pb-alloy technology, including a novel junction oxide barrier formation technique. A nondestructive readout (NDRO) Josephson ring cell operating with all current levels equal and an on-chip timing circuit for read/write operations were employed.     

A compact high-speed (31,5) parallel counter circuit based oncapacitive threshold-logic gates

A novel high-speed circuit implementation of the (31,5)-parallel counter (i.e., population counter) based on capacitive threshold logic (CTL) is presented. The circuit consists of 20 threshold logic gates arranged in two stages, i.e., the parallel counter described here has an effective logic depth of two. The charge-based CTL gates are essentially dynamic circuits which require a periodic refresh or precharge cycle, but unlike conventional dynamic CMOS gates, the circuit can be operated in synchronous as well as in asynchronous mode. The counter circuit is implemented using conventional 1.2 μm double-poly CMOS technology, and it occupies a silicon area of about 0.08 mm². Extensive post-layout simulations indicate that the circuit has a typical input-to-output propagation delay of less than 3 ns, and the test circuit is shown to operate reliably when consecutive 31-b input vectors are applied at a rate of up to 16 Mvectors/s. With its demonstrated data processing capability of about 500 Mb/s, the CTL-based (31,5) parallel counter offers a number of application possibilities, e.g., in high-speed parallel multiplier arrays and data encoding circuits     

On the application of the Neuron MOS transistor principle formodern VLSI design

In this paper, the speed performance, power consumption, and layout area of Neuron MOS transistor circuits are monitored considering the requirements of modern VLSI design. The Neuron MOS transistor is a recently discovered device principle which has a number of input gates that couple capacitively to a floating gate. The floating gate potential controls the current of a transistor channel. This device can be used in logic circuits. A threshold current through the Neuron MOS transistor can be defined that causes a switching of the output of the logic circuits as soon as the channel current surmounts or falls below the specified value. We designed two different multiplier cells, one based on a Neuron MOS inverter, and the other on a Neuron MOS n-MOSFET which is used as one input device of a comparator circuit. Functionality of both cells is proven for data rates up to 50 MHz which represents the first high-speed measurement of a circuit based on this new design principle. A perspective for the upper speed limit found at more than 500 MHz is given by simulation. The new design principle has a layout area reduced by more than a factor of two compared to usual multiplier cells. Moreover, it is shown, that depending on the design chosen, high speed operation leads to considerable power savings. In view of those advantages it is concluded that the principle of threshold logic qualifies for a major breakthrough for packing density improvement of CMOS-based applications