面向温度优化的片上网络任务调度方法

随着片上网络规模的扩大和研究的逐步深入,如何将芯片上众多的任务进行合理的调度成为系统温度优化的关键之一。针对片上网络任务调度问题, 提出一种基于最短曼哈顿距离的任务调度SMDS方案。该策略充分考虑核通信图中通信节点对之间最短曼哈顿路径,通过搜索算法寻找任务调度的目的节点,使用模拟退火算法确定任务调度对。实验结果显示,与传统的分布式任务调度 DTM策略相比,针对6*6、8*8和10*10的拓扑结构,SMDS实验方案在迁移次数方面的平均优化率分别为2208%、21.74%和23.02%。在平均跳数方面的平均优化率分别为24.04%、29.18%和23.04%,实现了系统温度优化。     

基于Flink的任务调度策略

针对大数据流式计算平台拓扑中因各关键节点上任务间不同类型的通信方式导致的通信开销较大问题,提出一种Flink环境下的任务调度策略。通过各任务间数据流大小确定拓扑边权重,将有向无环图转化为拓扑关键路径模型,在保证关键路径上节点负载差异较小的同时,最小化关键任务的节点间通信开销。实验结果表明,该算法与Flink平台现有的任务调度策略相比,在WordCount和TwitterSentiment作业执行过程中计算平均时延降低了13.09%,有效提升了系统性能。     

基于多核系统NOC架构的静态列表调度算法*

在单芯片多核系统中,NoC已成为主流片上通信架构,有效的任务调度是挖掘计算并行性的重要方面。本文在经典静态列表调度基础上,针对HEFT算法中节点排序会得出较多的优先级相同节点的问题,提出一种节点二次排序的调度方法,在边的调度上应用了ALAP原则,改进算法有效提高了调度效果。实验表明：新方法对bl、blcomp、blio等节点优先级算法得出的任务列表均有良好的调度效果,适应性较好;对于2D MESH同构NoC平台,改进算法对三种节点优先级算法有1.15倍的平均加速比,最大可有1.27倍加速比。     

片上网络的星型簇结构通信能耗研究

相对于传统的平面结构,三维片上网络具有更好的集成度和性能。提出一种基于三维网格的星型簇结构的片上网络(3D SCBM-NoC),3D SCBM-NoC可以减少路由节点,降低处理节点间的通信代价。通过分析3DSCBM-NoC的拓扑结构,建立了针对星型簇结构的片上网络通信能耗模型,分别使用顺序方法和蚁群算法实现了片上网络映射。实验结果表明,相对于处理节点规模相同且数目为16的3D Mesh-NoC和2D Mesh-NoC,3DSCBM-NoC的通信能耗明显降低。     

混合无线三维片网中无线路由节点分布研究

传统的片上网络都是采用金属链路连接各个路由节点,芯片上IP核的增多一方面导致了布线复杂度的增加,另一方面也导致了片上网络传输延迟和功耗的增加。由于片上微型天线的成功研制,芯片内的无线通信得以实现。无线通信具有高带宽、低延迟、低功耗的特点,使得无线片上网络(WNoC)成为传统片上网络最理想的替代方案,可以显著提高系统的性能。针对传统大规模片上网络(NoC)远距离核间多跳通信所带来的高能耗与延时问题,提出了一种8×8×4的三维混合无线片上网络架构以及针对该架构的路由算法。此外,对在混合型无线片上网络的拓扑设计中所遇到的无线节点和无线链路放置等问题进行了讨论。仿真结果表明,将无线节点放在第0层和第3层所得到的性能最好,且该拓扑结构与传统片上网络结构相比,在网络平均延迟以及网络总功耗方面取得了很大的提升。     

延迟优化的片上网络低功耗映射*

片上网络（NoC）是解决传统基于总线的片上系统（SoC）所面临的功耗、延迟、同步和信号完整性等挑战的有效解决方案。功耗和延迟是NoC设计中的重要约束和性能指标,在设计的各个阶段都存在着优化空间。基于蚁群优化算法,通过通信链路上并发通信事件的均匀分布来降低NoC映射阶段的功耗和延迟。仿真实验表明,与链路通信量负载均衡的方法相比,该方案能进一步在拓扑映射阶段优化功耗和延迟。     

基于3D Mesh结构的一种静态路由算法

3D NoC在同构多核系统中相比2D NoC具有更为优越的性能.本文在研究3D Mesh结构的基础上,对拓扑结构中的平均延时和理想吞吐量进行了理论上的评估,并提出了一种基于3D Mesh的新的静态路由算法,最后运用NS2网络仿真软件对其进行仿真和比较.实验结果显示,新的路由算法可以有效地提高吞吐量,并在大规模数据传输时...     

一种改进的二维Mesh结构片上网络拓扑

随着多核技术的发展,片上网络(Network on Chip,NoC)越来越受到人们的关注.为了研究出更适用于片上网络的拓扑结构,在研究二维mesh结构的基础上,将二维mesh结构中每个3×3的小mesh里的对角线上的点用长边连接,形成改进后的拓扑,提出了在改进后的拓扑上的16节点的路由算法,并将改进后的拓扑与二维mesh结构做了性能分析.在OPNET下仿真结果表明,在同等网络规模下,改进后的拓扑较原来的二维mesh结构有更小的传输延迟和更大的吞吐量.     

一种用于片上网络的拥塞感知哈密尔顿最短路径路由算法

类脑处理器能够支持多种脉冲神经网络SNN的部署来完成多种任务。片上网络NoC能够用较少的资源和功耗解决片上复杂的互连通信问题。现有的类脑处理器多采用片上网络来连接多个神经元核,以支持神经元之间的通信。SNN在时间步内瞬时突发的通信会在短时间内产生大量的脉冲报文。在这种通信行为下,片上网络会在短时间内达到饱和,造成网络拥塞。片上网络中非拥塞感知路由算法会进一步加剧网络拥塞状态,如何在每一个时间步内有效处理这些数据包,从而降低网络延迟,提高吞吐率,成为了目前需要解决的问题。首先对SNN的瞬时猝发通信特性进行了分析;然后提出一种拥塞感知的哈密尔顿路径路由算法,以降低NoC平均延迟和提高吞吐率;最后,使用Verilog HDL实现该路由算法,并通过模拟仿真进行性能评估。在网络规模为16×16的2D Mesh结构的片上网络中,相对于没有拥塞感知的路由算法,在数量猝发模式和概率猝发模式下,所提出的拥塞感知路由算法的NoC平均延迟分别降低了13.9%和15.9%;吞吐率分别提高了21.6%和16.8%。     

支持双拓扑结构的片上网络评估高层仿真平台

为实现高效的NoC（片上网络）性能评估, 缩短系统芯片的开发周期, 针对时钟精确级的NoC仿真方法进行研究, 提出了一种新型的高层次、高效率仿真平台, 与仅支持网格拓扑结构的传统仿真器相比, 其创新地支持了网格和环型双拓扑结构的性能评估, 同时支持虚通道扩展的路由器结构设计, 能快速得到网络的延迟、吞吐率、功耗等性能结果。实验结果表明, 该仿真平台能准确模拟NoC功能行为, 快速获得其仿真性能, 为NoC设计验证提供了高效的方法。     

An optimised 3D topology for on-chip communications

Increasing system complexity, energy and device reliability, requirement of modular approach, structured layout, effective spatial reuse of resources, scalability and re-programmability have made network-on-chip (NoC) an obvious interconnection design alternative to the ubiquitous bus based on chip communication architecture in system-on-chip. Designing of a topology and its routing scheme plays a vital role in determining performance of any NoC architecture. In recent years, 3D stacked NoC architecture attracts added interest in NoC design as it offers improved performance and shorter global interconnect. In this paper, we have developed a partially, vertically interconnected 3D topology, namely 3D Recursive Network Topology (3D RNT) and prove that the topology has a Hamiltonian connectedness. We have developed deadlock-free routing algorithm for the 3D RNT topology. Also, we compare the performance of the 3D RNT with partially and fully connected 3D mesh topologies (3D PMT and 3D FMT) by conducting suitable experiments. The experiment results show that there is not much deviation in respect of the performance of the 3D RNT on comparing with 3D PMT and 3D FMT even though a number of vertical links are trimmed down to 75%, which is an encouraging outcome as far as design space is concerned.     

A task migration mechanism for distributed many-core operating systems

Spatial locality of task execution is becoming important in future hardware platforms since the number of cores is steadily increasing. The large amount of cores requires an intelligent power manager and the high chip and core density requires increased thermal awareness to avoid thermal hotspots on the chip. This paper presents a lightweight task migration mechanism explicitly for distributed operating systems running on many-core platforms. As the distributed OS runs one scheduler on each core, the tasks are migrated between OS kernels within the same shared memory platform. The benefits, such as performance and energy efficiency, of task migration are achieved by re-locating running tasks on the most appropriate cores and keeping the overhead of executing such a migration sufficiently low. We investigate the overhead of migrating tasks on a distributed OS running both on a bus-based platform and a many-core NoC—with these means of measures, we can predict the task migration overhead and pinpoint the emerging bottlenecks. With the presented task migration mechanism, we intend to improve the dynamism of power and performance characteristics in distributed many-core operating systems.     

无虚拟通道的3D NoC ZoneDefense容错路由算法*

3D片上网络能有效解决片上系统的通信问题。本文针对3D Mesh NoC中的节点故障,提出了一种无虚拟通道容错路由算法,称为3D ZoneDefense容错路由算法(3D-ZDFT)。该算法建立在3D防御区域基础之上,3D防御区域能够提供故障体的位置信息。根据防御区域提供的故障体位置信息,3D-ZDFT可提前发现故障位置并改变转发端口,实现容错的同时避免引入死锁。实验结果表明,与HamFA相比,3D-ZDFT有较低的网络延迟和更高的可靠性。面积开销分析显示,3D-ZDFT比HamFA的面积开销高约3.1%。     

可靠电压频率岛感知的异步片上网络能耗优化

针对采用2D-Torus拓扑结构且支持电压频率岛（VFI）的异步片上网络能耗优化问题,提出了具有可靠性的、基于电压频率岛的划分和分配及片上网络任务映射的能耗优化方法．该方法采用递进优化的方式,根据IP核的动态处理能耗,不同电压频率岛之间的转换能耗和可靠性带来的能耗开销定义了IP核在电压频率岛之间移动的阈值函数,并通过对阈值函数进行判断完成电压频率岛的划分和分配,应用基于三元相关性量子粒子群优化算法完成处理单元到资源节点的映射,在映射中考虑保证系统可靠性的通信开销,对异步片上网络系统的可靠性进行优化．实验结果表明,该算法可以在不过多消耗能耗的情况下显著的改善片上网络系统的可靠性,且可有效降低NOC系统的能耗.     

三维片上网络研究综述

三维片上网络以其更短的全局互连、更高的封装密度、更小的体积等诸多优势,已引起国内外学术界和产业界的高度重视.对三维片上网络的研究,将直接影响一个国家未来三维集成电路和三维芯片产业的发展,也关系到国家安全.近年来,三维片上网络逐渐成为片上网络研究领域的一个重要方向,已取得了许多研究进展,但仍然存在许多挑战性的课题.对三维片上网络的基本问题作了简介;分析了三维片上网络在国内外的研究现状;讨论了三维片上网络研究中的关键问题,归纳出网络拓扑结构、路由机制、性能评估、通信容错、功耗、映射、测试、交换技术、服务质量、流量控制、资源网络接口等12类研究课题;分类综述了关键问题的研究进展;分析了三维片上网络存在的问题;指出,在三维片上网络拓扑结构方面:个性化拓扑结构设计、仿真平台研究开发、基于新型拓扑结构的三维芯片样片试制以及无线技术的引入等,在路由算法方面:适合3D Torus的路由算法、结合无关路由与自适应路由算法优点的新路由算法、适合各种新型拓扑结构的高效路由算法等,在性能评估方面:永久故障的容错、改进仿真程序增加对物理链路的建模、充分考虑通信的局部性等,在功耗方面:对拓扑结构/映射算法/路由算法和布局进行综合优化、动态和静态控制相结合、更为精确的3D NoC功耗模型等,在映射方面:发热均匀性、动态路由策略下映射评估模型的优化、低功耗映射算法、基于优化算法的组合映射等,都将是三维片上网络未来的重要研究课题.     

Application-Specific Network-on-Chip synthesis with flexible router Placement

Network-on-Chip (NoC) has been proposed as a possible solution to the communication problem in nanoscale System-on-Chip (SoC) design. NoC architectures with optimized application-specific topologies have been found to be superior to the regular architectures in designing Multi-Processor System-on-Chip (MPSoC) solutions. The application specific NoC design problem takes as input the chip floorplan, library of NoC components, and communication requirements between the tasks of the application. It outputs the positions of the routers in the floorplan, such that, all communication requirements of the application are satisfied. This paper presents an Integer Linear Programming formulation of the problem, followed by a heuristic technique based on Particle Swarm Optimization (PSO) for finding the router positions from the set of available positions within the chip floorplan. The goal is to minimize the communication cost between cores, satisfying both the link length and router port constraints. The results have been shown on realistic benchmarks. Comparisons have been carried out with regular mesh and custom architectures having routers positioned at (i) the corners of the cores, (ii) the centers of the cores, and (iii) the intersections of the cores. Significant reductions in communication cost have been observed over all the cases. For smaller benchmarks, the optimum results obtained via ILP matches exactly with those reported by the PSO. Many of the existing router placement policies fail even for these small benchmarks, when restrictions are imposed on permissible link length. This establishes the merit of the PSO formulation. Link and router energy consumption of the synthesized NoC have been compared with regular mesh based architectures. The results show significant reduction in communication cost, area overhead, link energy and router energy in the synthesized NoC over regular mesh topology as well.     

基于不规则Mesh的NoC无死锁路由

网络拓扑的选择是NoC设计中的一个重要问题,目前典型的特定应用NoC系统通常集成多个不同功能、不同尺寸、不同通讯需求的组件,而规则的网络拓扑结构并不适于在这种类型的NoC中应用,因此不规则Mesh网络被提出并被应用于不规则结构的NoC系统.为解决规则 Mesh路由算法在不规则Mesh中无法保证路由连通性的问题,本文提出一种不规则Mesh无死锁路由算法,无论NoC系统集成组件的版图如何变化,这一算法始终是连通的,即算法与不规则Mesh的规模和结构是无关的,同时算法仅使用较低的虚拟通道.     

A novel 3D NoC architecture based on De Bruijn graph

Networks on Chip (NoC) and 3-Dimensional Integrated Circuits (3D IC) have been proposed as the solutions to the ever-growing communication problem in System on Chip (SoC). Most of contemporary 3D architectures are based on Mesh topology, which fails to achieve small latency and power consumption due to its inherent large network diameter. Moreover, the conventional XY routing lacks the ability of fault tolerance. In this paper, we propose a new 3D NoC architecture, which adopts De Bruijn graph as the topology in physical horizontal planes by leveraging its advantage of small latency, simple routing, low power, and great scalability. We employ an enhanced pillar structure for vertical interconnection. We design two shifting based routing algorithms to meet separate performance requirements in latency and computing complexity. Also, we use fault tolerant routing to guarantee reliable data transmission. Our simulation results show that the proposed 3D NoC architecture achieves better network performance and power efficiency than 3D Mesh and XNoTs topologies.