铁电负电容场效应晶体管器件的研究

铁电负电容场效应晶体管作为一种新型半导体器件,利用铁电材料的负电容效应可使晶体管的亚阈值摆幅突破理论极限值60 mV/dec,是未来低功耗晶体管领域最具有前途的器件之一。该文研究并建立了铁电负电容场效应晶体管的器件模型,采用Matlab软件对负电容场效应晶体管的器件特性进行了研究分析,获得了亚阈值摆幅为33.917 6 mV/dec的负电容场效应晶体管的器件结构,探究了铁电层厚度、等效栅氧化层厚度及不同铁电材料对负电容场效应晶体管亚阈值摆幅的影响。     

绝缘体上硅FinFET亚阈值摆幅研究

在新型多栅器件栅电容模型的研究中,量子电容随着沟道长度及栅氧化层厚度的不断减小而变得越发不可忽略。推导了基于绝缘体上硅(SOI)工艺技术的鳍式场效应晶体管(FinFET)的量子电容,并通过构建囊括量子电容的内部电容网络模型推导了亚阈值摆幅。采用Matlab软件,仿真验证了量子电容对亚阈值摆幅的影响。提出了亚阈值摆幅的优化方法,为如何选取合适的器件尺寸来优化某个特定设计目标的性能提供了指导。     

NC-FinFET器件的仿真研究

通过结合BSIMCMG模型与负电容(NC)模型,构建了NC-FinFET模型。基于所建立的NC-FinFET模型,推导分析了其等效电容模型。利用Hspice对NC-FinFET的器件特性进行了系统仿真与分析。结果表明,与FinFET相比,NC-FinFET在电学特性上有更加明显的优势,亚阈值摆幅更低。此外,分析了铁电材料的厚度对亚阈值摆幅及栅压放大倍数的影响,以及衬偏电压对NC-FinFET性能的影响,为在NC-FinFET中降低功耗和抑制寄生效应提供了理论依据和解决思路。     

铁电负电容可测试性的仿真研究

铁电材料具有负电容特性,可应用于新一代超低亚阈值摆幅晶体管中。由于铁电负电容具有准静态特性,在实际测试中,难以直接观测到单独铁电电容的负电容现象。基于“Ginzburg-Landau”模型,采用TCAD软件,构建了紧凑的HfO₂铁电电容结构,并通过仿真获得了匹配的RC电路参数,验证了负电容特性。同时,仿真研究了外加电压幅值与串联电阻阻值对铁电电容负电容效应可测试性的影响。     

Si/Ge异质结双栅隧穿场效应晶体管TCAD仿真研究

Si/Ge异质结双栅隧穿场效应晶体管(DGTFET)较传统硅基DGTFET有更好的电学性能。文章基于Sentaurus TCAD仿真软件,构建了有/无Pocket两种结构的Si/Ge异质结DGTFET器件,定量研究了Pocket结构及Pocket区厚度、掺杂浓度等参数对器件开态电流、关态电流、亚阈值摆幅、截止频率和增益带宽积的影响。通过仿真实验和计算分析发现,Si/Ge异质结DGTFET的开态/关态电流、亚阈值摆幅、截止频率和增益带宽积随Pocket区掺杂浓度增大而增大,而Pocket区厚度对器件性能没有明显影响。研究结果为TFET器件的直流、频率特性优化提供了指导。     

一种带有斜向扩展源的双栅隧穿场效应晶体管

设计并研究了一种带有轻掺杂漏(LDD)和斜向扩展源(OES)的双栅隧穿场效应晶体管(DG-TFET),并利用Sentaurus TCAD仿真工具对栅长及扩展源长度等关键参数进行了仿真分析。对比了该器件与传统TFET的亚阈值摆幅、关态电流和开关电流比,并从器件的带带隧穿概率分析其优势。仿真结果表明,该器件的最佳数值开关电流比及亚阈值摆幅分别可达3.56×10¹²和24.5 mV/dec。另外,该DG-TFET在双极性电流和接触电阻方面性能良好,且具有较快的转换速率和较低的功耗。     

质子辐照对AlGaN/GaN HEMT亚阈值摆幅特性的影响

研究了具有不同栅漏间距的AlGaN/GaN高电子迁移率晶体管(HEMT)的亚阈值摆幅特性在0.4 MeV质子辐照(质子总注量为2.16×10¹² cm^-2)后的变化规律。质子辐照前，各器件的亚阈值摆幅基本一致；质子辐照后，器件的亚阈值摆幅随着栅漏间距的减小而逐渐降低。基于辐照前后器件的电容-电压曲线和输出特性得到低场载流子输运特性，并据此分析了亚阈值摆幅的变化原因。发现与器件尺寸相关的极化散射效应是不同尺寸器件在辐照后亚阈值摆幅发生不同变化的主要原因。为AlGaN/GaN HEMT的性能优化提供了全新的视角与维度。     

隧穿晶体管研究进展

随着晶体管尺寸不断缩小,CMOS电路的功耗问题变得日益严重。隧穿晶体管是一种基于载流子的隧道效应工作的器件,可以在室温下实现小于60 mV/dec的亚阈值摆幅,具有很好的低功耗应用前景。但常规的隧穿晶体管导通电流比较小,而且具有双极特性。首先介绍了隧穿晶体管的结构和工作原理。其次,针对常规隧穿晶体管问题,综述了国内外研究进展,包括Ge材料隧穿晶体管、纳米线隧穿晶体管等。最后介绍了一种基于隧穿介质层的新型隧穿晶体管,器件仿真结果表明这种新型器件可以有效抑制双极特性。     

基于铁电薄膜的Al/PVDF/SiO2/n-Si结构的负电容效应研究

采用旋涂法制备了基于铁电聚合物薄膜的Al/PVDF/SiO_2/n-Si(MFIS)结构。通过测量MFIS结构的电容-频率特性和电容-电压特性,观察到负电容效应。测量频率越低,正向偏压越大,负电容效应越显著。在时域中,施加脉冲电压,出现瞬态电流随时间增大的电感现象。研究结果表明,MFIS结构中的负电容效应是一种电感现象。构建能带图分析MFIS结构中负电容效应的产生原因,是由于大量电子注入到界面中被捕获使得电流的相位落后于电压导致。基于铁电薄膜的负电容MFIS结构有望应用于低功耗器件中。     

基于FET结构的MoS2器件的研究进展

对带隙可调的二维层状半导体二硫化钼(MoS2)的材料特性以及基于MoS2薄膜的器件性能和应用进行了简单阐述,重点分析了多种MoS2场效应晶体管(FET)的结构特点,并对MoS2 FET的制备工艺、电学性能(载流子迁移率、电流开关比、亚阈值摆幅等)以及栅极介质层材料对器件性能的影响等进行了综述.在此基础上进一步总结了近年...     

Partially Depleted Silicon-on-Ferroelectric Insulator Field Effect Transistor- Parametrization & Design Optimization for Minimum Subthreshold Swing

This paper presents the concept of a new field effect transistor based on ferroelectric insulator. The proposed design is named Partially Depleted Silicon-on-Ferroelectric Insulator Field Effect Transistor (PD-SOFFET). The design combines the concepts of negative capacitance in ferroelectric material and silicon-on-insulator (SOI) device. The structure varies from the conventional SOI technology by substituting the buried SiO₂ with a layer of ferroelectric insulator. This new material stack can extract an effective negative capacitance (NC) in the body of the device. The NC effect can provide internal signal boosting. It is demonstrated that the subthreshold swing and the threshold voltage of the proposed device can be lowered by carefully selecting the doping density, the types of the gate oxide and the thicknesses of the ferroelectric film, the silicon layer above the buried insulator and the gate oxide. Lower subthreshold swing is a prime requirement for ultra-low-power design. This paper focuses on studying several parameters to tune the subthreshold swing of the SOFFET device. We have recently introduced the concept of the new transistor, SOFFET, with ferroelectric insulator embedded inside the silicon substrate to lower the subthreshold swing. This paper investigates the impacts of different oxide materials, ferroelectric thicknesses and doping profiles on the negative capacitance inside the body of the proposed PD-SOFFET. It is observed that some emerging gate oxide materials can improve subthreshold flexibility, lower leakage and provide better control over the channel in the proposed device.     

Silicon-on-Ferroelectric Insulator field effect transistor (SOFFET): Partially depleted structure for sub-60 mV/decade applications

This paper presents the concept of a new field effect transistor (FET) named a Partially Depleted Silicon-on-Ferroelectric Insulator Field Effect Transistor (PD-SOFFET). Our design proposes to utilize the negative capacitance (NC) of ferroelectric material in a partially depleted silicon-on-insulator (PD-SOI) device structure. We suggest to substitute the buried insulator oxide (SiO₂) inside the SOI substrate with a ferroelectric material, which converts it to the Silicon-on-Ferroelectric Insulator (SOF) substrate. The proposed integration of a ferroelectric material into the body of the MOSFET device will provide the required NC effect to overcome the fundamental thermionic barrier of the current and emerging FETs. This new SOFFET device would provide enhanced device gain, speed and channel conduction. A theoretical model is developed to validate the concept of the new device, which can lower the subthreshold swing (S) below the theoretical minimum S=60 mV/decade that is imposed by the thermodynamic limit (kT/q) of the FET devices. Analytical models have been derived to show that the subthreshold swing and the threshold voltage of the proposed device depend on the thicknesses of ferroelectric insulator and gate oxide, and the doping profile of the silicon body. It has been demonstrated that by carefully optimizing different geometric and electrical parameters the proposed PD-SOFFET can provide S value significantly below 60 mV/decade.     

A new high-power voltage-controlled differential negative resistance device—The lambda bipolar power transistor

A new high power voltage-controlled differential negative resistance device using the LAMBDA bipolar transistor structure, called the LAMBDA bipolar power transistor, is proposed and studied. The basic structure of this new device consists of the simultaneous integration of an interdigitated bipolar junction transistor and a merged metal-oxide-semiconductor field effect transistor. Two basic interconnection configurations of the integrated devices are also discussed. Several interesting applications based on the fabricated devices are also demonstrated. It is shown that the proposed device can be used as power signal generator and amplitude modulator using very simple circuits.     

Transient Performance Estimation of Charge Plasma Based Negative Capacitance Junctionless Tunnel FET

We investigate the transient behavior of an n-type double gate negative capacitance junctionless tunnel field effect transistor (NC-JLTFET). The structure is realized by using the work-function engineering of metal electrodes over a heavily doped n⁺ silicon channel and a ferroelectric gate stack to get negative capacitance behavior. The positive feedback in the electric dipoles of ferroelectric materials results in applied gate bias boosting. Various device transient parameters viz. transconductance, output resistance, output conductance, intrinsic gain, intrinsic gate delay, transconductance generation factor and unity gain frequency are analyzed using ac analysis of the device. To study the impact of the work-function variation of control and source gate on device performance, sensitivity analysis of the device has been carried out by varying these parameters. Simulation study reveals that it preserves inherent advantages of charge-plasma junctionless structure and exhibits improved transient behavior as well.     

n/sup +/-InAs-InAlAs recess gate technology for InAs-channel millimeter-wave HFETs

We report a submicrometer, self-aligned recess gate technology for millimeter-wave InAs-channel heterostructure field effect transistors. The recess gate structure is obtained in an n/sup +/-InAs-InAlAs double cap layer structure with a citric-acid-based etchant. From molecular-beam epitaxy-grown material functional devices with 1000-, 500-, and 200-nm gate length were fabricated. From all three device geometries we obtain drive currents of at least 500 mA/mm, gate leakage currents below 2 mA/mm, and RF-transconductance of 1 S/mm. For the 200-nm gate length device f/sub /spl tau// and f/sub max/ are 162 and 137 GHz, respectively. For the 500-nm gate length device f/sub /spl tau// and f/sub max/ are 89 and 140 GHz, respectively. We observe scaling limitations at 200-nm gate length, in particular a negative threshold voltage shift from -550 to -810 mV, increased kink-effect, and a high gate-to-drain capacitance of 0.5 pF/mm. The present limitations to device scaling are discussed.     

Low-voltage high-gain differential OTA for SC circuits

A new differential operational transconductance amplifier (OTA) for SC circuits that operates with a supply voltage of less than two transistor threshold voltages is presented. Its simplicity relies on the use of a low-voltage regulated cascode circuit, which achieves very high output impedance under low-voltage restrictions. The OTA has been designed to operate with a supply voltage of V/sub DD/=1.5 V, using a 0.6 /spl mu/m CMOS technology with transistor threshold voltages of V/sub TN/=0.75 V and V/sub TP/=-0.85 V. Post-layout simulation results for a load capacitance (C/sub L/) of 2 pF show a 75 MHz gain-bandwidth product and 100 dB DC gain with a quiescent power consumption of 750 /spl mu/W.     

基于FDSOI的TFET和MOSFET总剂量效应仿真

对基于全耗尽绝缘体上硅(FDSOI)的隧穿场效应晶体管(TFET)器件和金属氧化物半导体场效应晶体管(MOSFET)器件进行了总剂量(TID)效应仿真,基于两种器件不同的工作原理,研究了总剂量效应对两种器件造成的电学影响,分析了辐照前后TFET和MOSFET的能带结构、载流子密度等关键因素的变化。仿真结果表明:两种器件在受到较大辐射剂量时(1 Mrad (Si)),TFET受辐射引起的固定电荷影响较小,仍能保持较好的开关特性、稳定的阈值电压;而MOSFET则受固定电荷的影响较大,出现了背部导电沟道,其关态电流增加了几个数量级,开关特性发生了严重退化,阈值电压也严重地向负电压偏移。此外,TFET的开态电流会随着辐照剂量的增加而减小,这与MOSFET的表现恰好相反。因此TFET比MOSFET有更好的抗总剂量效应能力。