Analysis of the operation of GaAlAs/GaAs HBTs

Drift-diffusion modeling in two dimensions has been used to characterize and analyze storage, transport and recombination effects in GaAlAs/GaAs heterostructure bipolar transistors. Both intrinsic and parasitic effects have been studied, and their relationship to the design of the device is discussed. For conventional dopings and high current densities, the heterojunction grading potential causes a barrier in the base-emitter junction, which results in a large increase in the dynamic resistance. In heterojunction collectors, a similar barrier leads to a large increase in base charge storage and to spreading of the collector current. It is shown that increased doping levels can successfully suppress these barrier effects. The capacitance and transport phenomena at the base-emitter junction are also analyzed under conditions of large forward bias, where the junction space-charge region is shorter than the alloy grading length. Recombination is analyzed in the limit of high surface recombination velocities using Shockley-Read-Hall theory in the presence of Fermi-level pinning due to surface states. The pinning results in a potential energy saddle point at the edge of the base-emitter junction, which largely determines the surface recombination behavior of the transistor when the recombination velocity is high     

Application of O+implantation in inverted InGaAs/InAlAs heterojunction bipolar transistors

Deep O+ implantation has been used to create a high-resistivity layer buried beneath the Be+ -implanted extrinsic base-emitter junction region of In0.52Al0.48As/In0.53Ga0.47As inverted (emitter-down) heterojunction bipolar transistors (HBT's). The O+ -implanted layer remains highly resistive even after a rapid thermal annealing step at 700°C to activate the Be+ implants. With the O+ implantation, the forward current of the extrinsic base-emitter diode is significantly reduced. HBT's with Be+ - and O+ -implanted extrinsic base regions exhibit current gains of ≃ 100 at a collector current density in excess of 10³A/cm². Another benefit from the deep O+ -implanted layer is a dramatic reduction in the junction capacitance of the extrinsic base-emitter diode.     

Base-emitter diffusion capacitance in GaAlAs/GaAs HBTs

The voltage dependence of the base-emitter diffusion capacitance in a single heterojunction GaAlAs/GaAs HBT is discussed. It is found that conventional transistor capacitance models are not accurate for these devices. An empirical expression is given which may be used to model this diffusion capacitance.<>     

Direct parameter extraction of SiGe HBTs for the VBIC bipolar compact model

An improved direct parameter extraction method of SiGe heterojunction bipolar transistors (HBTs) for the vertical bipolar intercompany (VBIC)-type hybrid-/spl pi/ model is developed. All the equivalent circuit elements are extracted analytically from S-parameter data only and without any numerical optimization. The proposed technique of the parameter extraction, differing from the previous ones, focuses on correcting the pad de-embedding error for an accurate and invariant extraction of intrinsic base resistance (R/sub bi/), formulating a new parasitic substrate network, and improving the extraction procedure of transconductance (g/sub m/), dynamic base-emitter resistance (r/sub /spl pi//), and base-emitter capacitance (C/sub /spl pi//) using the accurately extracted R/sub bi/. The extracted parameters are frequency-independent and reliable due to elimination of any de-embedding errors. The agreements between the measured and model-calculated data are excellent in the frequency range of 0.2-10.2 GHz over a wide range of bias points. Therefore, we believe that the proposed extraction method is a simple and reliable routine applicable to the optimization of transistor design, process control, and the improvement of VBIC compact model, especially for SiGe HBTs.     

Selective epitaxy base transistor (SEBT)

A bipolar transistor using selective epitaxy for base formation in a double-poly self-aligned structure is presented. The intrinsic base was formed by a selective-epitaxial deposition in place of ion implantation. Such epitaxial base processes are capable of achieving a narrow intrinsic base sheet resistance R_bi and base-emitter diffusion capacitance c_be compared to advanced ion-implanted processes. A selective epitaxial base can be simply introduced in advanced double-poly self-aligned processes compared to a nonselective epitaxial layer     

An analysis of small-signal and large-signal base resistances forsubmicrometer BJT's

Small-signal and large-signal base resistances for submicrometer BJT's have been analyzed in detail by using a two-dimensional device simulator. It has been clarified that the small-signal base resistance cannot be obtained from the input impedance semicircle in the complex plane accurately due to the effect of the emitter resistance at low frequencies, and also due to the reduction of the base-emitter junction resistance and the diffusion capacitance at high frequencies. A new method for extracting an accurate value of the small-signal base resistance is proposed. The extracted small-signal base resistance not only differed from the large-signal base resistance extracted from the dc characteristics of a BJT, but also agreed with the differential resistance. It has been shown that, for a 0.6 μm emitter-width BJT, the measured value of the small-signal base resistance is less than half that of the large-signal base resistance in the bias region in which actual BJT circuits operate     

SDB/SOI双极器件失效机理与可靠性评价技术研究

对硅片直接键合/绝缘体上硅(SDB/SOI)双极电路的退化机理进行了描述。在基极-发射极反向偏置的条件下,研究了应力作用时间与器件参数的退化关系。实验结果表明,电流放大倍数β与退化时间的平方根呈线性关系;不同的反向偏压下,退化的速度也不同。建立了器件的退化模型,对双极器件在使用条件下的可靠性进行了分析。     

A 160-GHz f/sub T/ and 140-GHz f/sub MAX/ submicrometer InP DHBT in MBE regrown-emitter technology

We report a 0.7/spl times/8 /spl mu/m/sup 2/ InAlAs-InGaAs-InP double heterojunction bipolar transistor, fabricated in a molecular-beam epitaxy (MBE) regrown-emitter technology, exhibiting 160 GHz f/sub T/ and 140 GHz f/sub MAX/. These initial results are the first known RF results for a nonselective regrown-emitter heterojunction bipolar transistor, and the fastest ever reported using a regrown base-emitter heterojunction. The maximum current density is J/sub E/=8/spl times/10/sup 5/ A/cm/sup 2/ and the collector breakdown voltage V/sub CEO/ is 6 V for a 1500-/spl Aring/ collector. In this technology, the dimension of base-emitter junction has been scaled to an area as low as 0.3/spl times/4 /spl mu/m/sup 2/ while a larger-area extrinsic emitter maintains lower emitter access resistance. Furthermore, the application of a refractory metal (Ti-W) base contact beneath the extrinsic emitter regrowth achieves a fully self-aligned device topology.     

A 10.7-MHz sixth-order SC ladder filter in 0.35-/spl mu/m CMOS technology

A sixth-order 10.7-MHz bandpass switched-capacitor filter based on a double terminated ladder filter is presented. The filter uses a multipath operational transconductance amplifier (OTA) that presents both better accuracy and higher slew rate than previously reported Class-A OTA topologies. Design techniques based on charge cancellation and slower clocks are used to reduce the overall capacitance from 782 down to 219 unity capacitors. The filter's center frequency and bandwidth are 10.7 MHz and 400 kHz, respectively, and a passband ripple of 1 dB in the entire passband. The quality factor of the resonators used as filter terminations is around 32. The measured (filter + buffer) third-intermodulation (IM3) distortion is less than -40 dB for a two-tone input signal of +3-dBm power level each. The signal-to-noise ratio is roughly 58 dB while the IM3 is -45 dB; the power consumption for the standalone filter is 42 mW. The chip was fabricated in a 0.35-/spl mu/m CMOS process; filter's area is 0.84 mm/sup 2/.     

1/f noise characteristics of AlGaAs/GaAs heterojunction bipolartransistor with a noise corner frequency below 1 kHz

To reduce the low-frequency noise, HBTs with a large emitter size of 120×120 μm² are fabricated on abrupt emitter-base junction materials without undoped spacer. The HBTs exhibit an internal noise corner frequency of 100 Hz, which is much lower than about 100 kHz of conventional AlGaAs/GaAs HBTs. From the very low noise HBTs, the existence of resistance fluctuation 1/f noise is clearly verified by the simple comparison of collector current noise spectra with different base terminations. It is found that, at a high emitter-base forward bias, the resistance fluctuation 1/f noise becomes dominant for shorted base-emitter termination, but the internal 1/f noise dominant for open base. Device design rules for low noise small-feature size HBT, including resistance fluctuation, are discussed     

Experimental comparison of base recombination currents in abrupt and graded AlGaAs/GaAs heterojunction bipolar transistors

The relative importance of the base bulk recombination current and the base-emitter junction space charge recombination current is examined for AlGaAs/GaAs HBTs with different grading schemes in the base-emitter junction. Experimental results demonstrate that, in abrupt HBTs, the base bulk recombination current is larger, and the base current increases with the base-emitter bias with an ideality factor of approximately 1. In contrast, in graded HBTs, the space charge recombination current dominates and the base current ideality factor is approximately 2. These experimental results agree well with a published theoretical calculation.<>     

Temporal response characteristics of a In0.53Ga0.47As/InP quantum well phototransistor

An investigation of multiple-quantum-well heterojunction phototransistors with InGaAs/InP quantum wells in the collector and InGaAsP base is discussed. The design of the structure ensures that light is absorbed only in the quantum-well region, thus providing a way to study the correlation between quantum well and phototransistor carrier dynamics. Moreover, since the operation of a n-p-n phototransistor is governed by hole injection into the base, the transient behavior of the device reflects the hole dynamics in the multiple-quantum-well region. The response of the device to picosecond optical pulses shows strong dependence on bias conditions: from device response determined by minority carrier recombination time (~2 ns) at high base-emitter bias, to current time constant dominated response (~50 ps) at low base-emitter bias. The field dependent escape times of carriers from the quantum wells under different bias conditions are obtained (10-100 ps) and are seen to affect the risetime of the transistor to pulsed photoexcitation     

A low-power inverted ladder D/a converter

Interpolating, dual resistor ladder digital-to-analog converters (DACs) typically use the fine, least significant bit (LSB) ladder floating upon the static most significant bit (MSB) ladder. The usage of the LSB ladder incurs a penalty in dynamic performance due to the added output resistance and switch matrix parasitic capacitance. Current biasing of the LSB ladder addresses this issue by employing active circuitry. We propose an inverted ladder DAC, where an MSB ladder slides upon two static LSB ladders. While using no active components this scheme achieves lower output resistance and parasitic capacitance for a given power budget. We present a 0.35-/spl mu/m, 3.3-V implementation consuming 22-/spl mu/A current with output resistance of 40 k/spl Omega/ and effective parasitic capacitance of 650 fF.     

An integratable second-order compensated bandgap reference for 1V supply

A new systematic approach is used for the design of bandgap references. A linear combination of two base-emitter voltages is taken to compensate implicitly for the temperature behavior of these base-emitter voltages. To reach optimum circuit performance with respect to accuracy and power, systematic design procedures are used. The realized bandgap reference circuit is completely integratable and operates from a supply voltage of only 1V. The output voltage is approximately 194 mV and has an average temperature dependency of 1.5ppm/°C in the range of 0°C to 100°C. The circuit has been realized in a bipolar process withf _t 5 GHz. The total amount of capacitance is approximately 150 pF and the current consumption is about 100µA.     

Performance Modeling of Low-$k$/Cu Interconnects for 32-nm-Node and Beyond

Challenges and issues with the scaling of low-$k$/Cu interconnects in ultra-large-scale integration (ULSI) devices are reviewed, and the performance of interconnects is featured by considering the effect of the resistance and capacitance per unit interconnect length or the minimum grid length. The grid-scaled resistance–capacitance (GSRC) model is proposed to compare the interconnect performance at various technology nodes. Introduction of low-$k$ films to reduce the line capacitance improves the per-grid value of the resistance–capacitance product, however, the abrupt increment of the line resistivity due to the small-size effect consumes the benefit of the capacitance beyond 32-nm-node. We also discuss power consumption in interconnects with different low- $k$ structures based on experimental works. Continuous reduction of effective $k$-value $(K_{ rm eff})$ is needed to reduce the active power consumption. The way to reduce the interconnect resistance while keeping the interconnect reliability high is a key challenge, particularly for deeply scaled-down ULSIs.      

Phototransistors, APD-FET, and PINFET optical receivers for 1-1.6-µm wavelength

The PINFET hybrid is the most sensitive receiver currently available for long-wavelength direct detection digital optical systems operating below 1 Gbit/s. State-of-the-art values for input capacitance and current gain in heterojunction phototransistors (HPT's) may yield better sensitivity at bit-rates above 1 Gbit/s. At lower bit-rates, a reduced capacitance and/or higher gain would be needed, together with a low base-collector leakage current, a low base-emitter defect current, and probably the use of a bounded disparity transmission code. Avalanche photodiodes (APD's) in principle offer scope for much improvement, but will require a low level of shot noise on the bulk leakage current and either a low excess noise factor for the photocurrent avalanche or a low level of gain-independent pre-amplifier noise. Comprehensive estimates of receiver sensitivity for APD's in systems operating at 100 Mbit/s and 1 Gbit/s indicate the relative importance of the various noise sources for the case where the excess noise factors for the photocurrent and leakage current avalanches are equal. However, the PINFET hybrid is still likely to compete with state-of-the-art APD's for bit-rates up to several hundred Mbit/s.     

Intermodulation generation by electron tunneling through aluminum-oxide films

The generation of intermodulation (IM) interference by nonlinear conduction mechanisms in normally passive hardware components can lead to severe degradation in the performance of multi-carrier communication systems in satellites, space probes, and ship-board systems. This paper describes an investigation of the generation of IM due to nonlinear conduction by electron tunneling through aluminum-oxide films. Details are presented regarding the fabrication of Al-Al2O3-Al junctions, the current-voltage and capacitance characteristics, and the measurement of IM power levels. The IM is correlated with the junction circuit parameters and with tunneling theory. Results are also presented on preliminary experiments to beneficially modify such nonlinear conduction by implantation of metallic ions in the oxide film.     

Failure mode analysis of AlGaAs/GaAs HBTs using electrostatic discharge method

The failure modes of AlGaAs/GaAs heterojunction bipolar transistors (HBTs) showing increases of base leakage current found during the bias and temperature reliability test have been examined and analysed by using an electrostatic discharge (ESD) method. In the examination for HBT having an emitter of 2 × 20 μm, increases of a base leakage current have been observed when an ESD of around 100 V is applied through a base-emitter junction. Furthermore, increases of a collector leakage current have been observed with the additional ESD of around 150 V. Since no fatal effects for the transistor amplification are found in the high current region, the degradations are concluded to be responsible to the local damages of the base layer at the edge of base-emitter junction. Applying the Wunsch-Bell model to the damaged region, the temperature is estimated to be in a range from 400 to 550°C. It is thought that thermal destruction occurs in a base layer.     

On the High-Speed Turn-Off of a Power Transistor by a Small Saturable Core

An effective method for reducing the size and weight of the switching dc-dc converter is to increase the switching frequency. To accomplish this with no deterioration in efficiency, it is necessary to suppress the switching loss per cycle by shortening the switching time. An efficient dc-dc converter operating at the megahertz region is presented. The turn-off time is shortened by using the current feedback and the core saturation. The turn-off mechanism is analyzed with the equivalent circuits. As a result, it is found that the excess carrier in the base region is discharged quickly by the large reverse base current, which flows when the energy stored in the base-emitter capacitance of the power transistor is transferred to the saturated inductance of the core with high frequency oscillation.     

Narrow-gate In0.53Ga0.47As junctionfield-effect transistors as tunable resistors for long-wavelengthintegrated optical receivers

The fabrication of In_0.53Ga_0.47As junction field-effect transistors (JFETs) for use as active feedback resistors in integrated transimpedance photoreceivers is described. Transistors using both air-bridge and non-air-bridge technologies are described. Varying the gate-to-source voltage (V_GS) allows the output resistance to be tuned continuously between 3 and 40 kΩ with a drain-to-source shunt capacitance of less than 10 fF. The temperature coefficient of the output resistance is between -5 and -20 Ω/°C (for V_GS less than the pinch-off voltage). The combination of large resistance and low shunt capacitance can result in high receiver sensitivity without sacrificing amplifier dynamic range. The feedback FETs are fabricated adjacent to 1.8-μm gate JFETs with transconductances of 110 mS/mm and gate-to-source capacitances of 1.3 pF/mm