Excess noise reduction in GaInP/GaAs heterojunction bipolartransistors

In this paper an annealing procedure which gives an excess noise reduction both of heavily C-doped resistive structures and GaInP/GaAs Heterojunction Bipolar Transistors (HBTs) of 5 dB is proposed. The investigation of the correlation between the noise generators indicate that the annealing leads to a decrease of noise voltage attributed to a strain reduction both in the intrinsic and in the extrinsic base related to a site switching effect of carbon atoms. The reduction of noise current with annealing is attributed to the surface improvement related passivation process by hydrogen atoms     

Impact of post-oxidation annealing on low-frequency noise, threshold voltage, and subthreshold swing of p-channel MOSFETs

The impact of post-oxidation annealing on the low-frequency noise, threshold voltage, and subthreshold swing of p-channel MOSFET is reported. The low-frequency noise is improved significantly with post-oxidation annealing and a modest V/sub T/ and S reduction is observed. Oxide traps are primarily extracted from measured noise. They are also extracted from threshold voltage and subthreshold slope shift. The contribution of oxide traps to threshold voltage shift and 1/f noise is analyzed through quantitative approach in the light of correlated fluctuation theory. Analysis on experimental results shed light on the well-known controversy about the origin of low-frequency noise, suggesting that experimental results are in agreement with mobility fluctuation theory whereas correlated number fluctuation theory explains the result assuming only a fraction of total oxide charge at a given energy level participates in the generation of low-frequency noise.     

The Investigation of Post-Annealing-Induced Defects Behavior on 90-nm In Halo nMOSFETs With Low-Frequency Noise and Charge-Pumping Measuring

In this letter, we investigated the effects of post-annealing on indium (In) halo-induced defects for 90-nm nMOSFETs with both low-frequency noise and charge-pumping (CP) current measuring methods. The noise in In halo devices with and without a post-annealing is lower and higher than that in Boron-halo devices, respectively. Additionally, with increase of annealing time, the noise is decreased for the measuring frequency less than 1 kHz due to the efficient elimination of oxide defects. For frequency larger than 1 kHz, the longer annealing time induces a larger quantity interface defects thus enhancing the generation of noise in high frequency. The results are nicely supported by the measurements of gate integrity and CP currents     

The correlation between the low-frequency electrical noise of high-power quantum well lasers and devices surface non-radiative current

The low-frequency electrical noise, voltage–current (V–I) and electrical derivative characteristics of 980 nm InGaAsP/InGaAs/GaAlAs high power double quantum well (DQW) lasers are measured at different conditions. The correlation between the low-frequency electrical noise and surface non-radiative current of devices is discussed. The results indicate that the low-frequency electrical noise of 980 nm high power DQW lasers is mainly 1/f noise and has good relation with the devices surface current at low injection.     

1/f noise and radiation effects in MOS devices

An extensive comparison of the 1/f noise and radiation response of MOS devices is presented. Variations in the room-temperature 1/f noise of unirradiated transistors in the linear regime of device operation correlate strongly with variations in postirradiation threshold-voltage shifts due to oxide trap charge. A simple number fluctuation model has been developed to semi-quantitatively account for this correlation. The 1/f noise of irradiated n-channel MOS transistors increases during irradiation with increasing oxide-trap charge and decreases during postirradiation positive-bias annealing with decreasing oxide-trap charge. No such correlation is found between low-frequency 1/f noise and interface-trap charge. The noise of irradiated p-channel MOS transistors also increases during irradiation, but in contrast to the n-channel response, the p-channel transistor noise magnitude increases during positive-bias annealing with decreasing oxide-trap charge. A qualitative model involving the electrostatic charging and discharging of border traps, as well as accompanying changes in trap energy, is developed to account for this difference in n- and p-channel postirradiation annealing response. The correlation between the low-frequency 1/f noise of unirradiated devices and their postirradiation oxide-trap charge suggests noise measurements can be used as a nondestructive screen of oxide trap charge related failures in discrete MOS devices and for small scale circuits in which critical transistors can be isolated. It also suggests that process techniques developed to reduce radiation-induced-hole trapping in MOS devices can be applied to reduce the low-frequency 1/f noise of MOS circuits and devices. In particular, reducing the number of oxygen vacancies and vacancy complexes in the SiO ₂ can significantly reduce the 1/f noise of MOS devices both in and outside a radiation environment     

Nanoscale CMOS spacer FinFET for the terabit era

A spacer lithography process technology, which uses a sacrificial layer and spacer layer formed by chemical vapor deposition (CVD), has been developed. It has been applied to make a sub-40-nm Si-fin structure for a double-gate FinFET with conventional dry etching for the first time. The minimum-sized features are defined not by the photolithography but by the CVD film thickness. Therefore, this spacer lithography technology yields better critical dimension uniformity than conventional optical or e-beam lithography and defines smaller features beyond the limit of current lithography technology. It also provides a doubling of feature density for a given lithography pitch, which increases current by a factor of two. To demonstrate this spacer lithography technology, Si-fin structures have been patterned for planar double-gate CMOS FinFET devices     

Effect of the surface and barrier defects on the AlGaN/GaN HEMT low-frequency noise performance

We report on the effect of Si/sub 3/N/sub 4/ passivation of the surface of AlGaN/GaN transistors on low-frequency noise performance. Low-frequency noise measurements were performed on the device before and after the passivation by a Si/sub 3/N/sub 4/ film. A lower level of the low-frequency noise was observed from the device after the passivation. The passivation layer improved high-frequency, large-signal device performance, but introduced parasitic leakage current from the gate. A lower level of flicker noise is explained by the fact that noise is mostly originated from the fluctuation of sheet charge and mobility in the ungated region of the device due to the defects on the surface and in the barrier of the unpassivated device. Passivation eliminates part of the defects and higher leakage current increases the number of electrons on the surface and in the vicinity of the barrier defects, lowering the contribution to the low-frequency noise according to Hooge's law.     

1/f noise in hot-carrier damaged MOSFET's: effects ofoxide charge and interface traps

The 1/f noise in the drain current of hot-carrier damaged MOSFETs biased in weak inversion has been studied. By the use of a biased annealing treatment to simultaneously decrease the density of oxide trapped charge (N_ot) and increase the density of interface traps (D_it), the authors have separated the contributions of these two kinds of defects. The results clearly indicate that, while the low-frequency 1/f noise is correlated with N_ot, the high-frequency 1/f noise is correlated with D_it     

Surface passivation of GaAs MESFETs

The metal semiconductor field effect transistor (MESFET) represents a more realistic test for “passivation” efficacy than conventional capacitor test structures due to its prototypical fabrication process. This paper evaluates Gallium-Arsenide (GaAs) surface passivation films utilizing the MESFET as a test vehicle. For this study, gate-to-drain leakage current, gate-to-drain breakdown voltage, complex impedance versus frequency, and low-frequency noise measurements are performed on MESFETs with various passivation films. The results indicate that a hydrogen plasma used to “pre-clean” the GaAs surface in conjunction with an in situ plasma-enhanced chemical vapor deposition (PECVD) Si₃N₄ passivation film yields the best performance. In contrast, atomic-layer-epitaxial ZnSe demonstrated inferior performance (even in comparison to PECVD Si₃N₄ passivation films that did not receive a hydrogen “pre-clean”)     

Low-frequency excess noise in metal—Silicon Schottky barrier diodes

Theoretical models for the generation-recombination noise and trapping noise in metal-semiconductor Schottky barrier diodes are developed. Low-frequency excess noise in Schottky barrier diodes is found to be dominated by the modulation of the barrier height φB caused by fluctuation in the charge state of traps or generation-recombination centers. This noise mechanism does not occur in p-n junctions. The bias and the temperature dependence of the generation-recombination noise is critically compared with the experimental data for forward diode current ranges from 3 to 300 µA and operating temperatures from -25° to 100°C. Trapping noise in Schottky barrier diodes is observed at low temperatures in diodes not intentionally doped with deep level impurities. The experimental results on trapping noise can be described by assuming that the trap states have a constant capture cross section and are uniformly distributed in space, as well as in energy. The surface potential at the diode periphery also has an important effect on the Schottky barrier diode noise. The best low-frequency noise behavior is found when the surface is at the flat-band condition. An accumulated surface is always associated with a large amount of low-frequency excess noise.     

DC conduction and low-frequency noise characteristics ofGaAlAs/GaAs single heterojunction bipolar transistors at roomtemperature and low temperatures

The DC conduction and low-frequency noise characteristics of GaAlAs/GaAs single heterojunction bipolar transistors (HBTs) have been investigated at room temperature and at temperatures down to 5 K. The collector current dependence of the current gain was investigated at various temperatures. The low-frequency noise characteristics exhibit both 1/f and generation-recombination components. The noise characteristics are sensitive to changes in base current and insensitive to changes in collector-emitter voltage, thus suggesting that the noise source is located in the vicinity of the emitter-base heterojunction. The noise spectrum follows a simple model based on minority carrier trapping effects at the heterointerface     

A New Look at Noise in Transferred Electron Oscillators

Low-frequency current and voltage fluctuations have been measured, and it has been confirmed that noise in packaged transferred electron devices (TED's) is due to three distinct noise mechanisms: flicker, generation-recombination, antd thermal noise. For transferred electron oscillators (TEO's), this low-frequency noise is upconverted into the microwave frequency range and adds to the intrinsic RF noise. We have found that between 1 kHz and 1 MHz off the carrier, temperature-dependent generation-recombination noise is the main contributor to the total noise. A model of a noisy TEO is presented. This model permits the calculation of AM and FM noise spectra from device and circuit parameters for measured low-frequency noise or the derivation of device characteristics from noise and circuit parameter measurements.     

Low 1/f noise characteristics of AlGaAs/GaAs heterojunction bipolartransistor with electrically abrupt emitter-base junction

It is shown that the use of an electrically abrupt emitter-base junction considerably reduces the 1/f noise of self-aligned AlGaAs/GaAs heterojunction bipolar transistor (HBT). Although this device does not have depleted AlGaAs ledge passivation layer, the low-frequency noise spectra show a very low 1/f noise corner frequency of less than 10 kHz, which is much lower than previously reported value of about 100 kHz from conventional passivated or unpassivated AlGaAs/GaAs HBT's. Except for a residual generation-recombination (g-r) noise component, the noise power is comparable to that of Si BJT. It is also found that the low-frequency noise power of the AlGaAs/GaAs HBT is proportional to the extrinsic GaAs base surface recombination current square. Unlike the other HBT's reported, the noise sources associated with interface state and emitter-base (E-B) space charge region recombination are not significant for our device     

An advanced low-frequency noise model of GaInP-GaAs HBT for accurate prediction of phase noise in oscillators

We present a new low-frequency noise model of a GaInP-GaAs HBT and the associated extraction process from measurements. Specific measurements enable us to locate the two dominant low-frequency noise sources. Their spectral densities extraction as a function of the emitter bias current is then performed and a normalized scalable model is deduced. The cyclostationarity of the low-frequency noise sources is justified. The whole noise model including the shot noise source is implemented in the nonlinear HBT model used in the United Monolithic Semiconductors foundry. In order to verify the validity of the scalable noise model, several voltage-controlled oscillators with different center frequencies and tuning bandwidth have been designed and processed. Comparisons between the predicted performances and experimental results show an excellent agreement and validate the proposed low-frequency noise modeling of multifinger HBTs.     

Low-frequency intensity fluctuations of c.w. d.h. GaAlAs-diode lasers

The optical-emission fluctuations and the current noise of c.w. d.h. GaAlAs junction lasers have been investigated for the first time in the low-frequency range. In both the optical noise spectra and the current noise spectra, a l/f behaviour has been observed. It was found that a strong crosscorrelation exists between optical-emission noise and forward-current noise. Finally, an optoelectronic feedback method that practically eliminated the relative excess light noise has been demonstrated.     

A highly threshold Voltage-controllable 4T FinFET with an 8.5-nm-thick Si-fin channel

Highly threshold voltage (V/sub th/)-controllable four-terminal (4T) FinFETs with an aggressively thinned Si-fin thickness down to 8.5-nm have successfully been fabricated by using an orientation-dependent wet-etching technique, and the V/sub th/ controllability by gate biasing has systematically been confirmed. The V/sub th/ shift rate (/spl gamma/=-/spl delta/V/sub th///spl delta/V/sub g2/) dramatically increases with reducing Si-fin thickness (T/sub Si/), and the extremely high /spl gamma/=0.79 V/V is obtained at the static control gate bias mode for the 8.5-nm-thick Si-fin channel device with the 1.7-nm-thick gate oxide. By the synchronized control gate driving mode, /spl gamma/=0.46 V/V and almost ideal S-slope are achieved for the same device. These experimental results indicate that the optimum V/sub th/ tuning for the high performance and low-power consumption very large-scale integrations can be realized by a small gate bias voltage in the ultrathin Si-fin channel device and the orientation-dependent wet etching is the promising fabrication technique for the 4T FinFETs.     

Low-frequency noise properties of selectively dry etched InP HEMT's

The low-frequency noise of lattice-matched InAlAs/InGaAs/InP high electron mobility transistors (HEMT's) gate recess etched with a highly selective dry etching process and with conventional wet etching were studied at different gate and drain biases for the temperature range of 77-340 K. The measurements showed a significantly lower normalized drain current 1/f noise for the dry etched HEMT's under all bias conditions. No difference in the normalized gate current 1/f noise could be observed for the two device types. By varying the temperature, four electron traps could be identified in the drain current noise spectra for both dry and wet etched devices. No additional traps were introduced by the dry etching step. The concentration of the main trap in the Schottky layer is one order of magnitude lower for the dry etched HEMT's. No hydrogen passivation of the shallow donors was observed in these devices. We presume hydrogen passivation of the deep levels as the cause for the trap density reduction. The kink effect in the dry etched HEMT's was observed to be reduced significantly compared with wet etched devices which gives further evidence of trap passivation during dry etching. These results show that dry etched InP HEMT's have suitable characteristics for the fabrication of devices for noise sensitive applications     

SiGe HBT低频噪声PSPICE模拟分析

对SiGe HBT低频噪声的各噪声源进行了较全面的分析,据此建立了SPICE噪声等效电路模型,进一步用PSPICE软件对SiGe HBT的低频噪声特性进行了仿真模拟.研究了频率、基极电阻、工作电流和温度等因素对低频噪声的影响.模拟结果表明,相较于Si BJT和GaAs HBT,SiGe HBT具有更好的低频噪声特性;在低频范围内,可通过减小基极电阻、减小工作电流密度或减小发射极面积、降低器件的工作温度等措施来有效改善SiGe HBT的低频噪声特性.所得结果对SiGe HBT的设计和应用有重要意义.     

低偏置电流下大功率半导体激光器低频电噪声特性

测量了大功率InGaAsP/GaAs量子阱半导体激光器在五十分之一阈值电流下的电压低频噪声功率谱密度.实验结果显示,激光器的低频电噪声呈现1/f噪声,在不同的偏置电流范围内,1/f噪声幅度随电流的变化关系不同,整体上随偏置电流的增大而减小,实验中并未发现g-r噪声.结合低偏置电流时激光器动态电阻的大小,给出了1/f噪声的模型,分析了在低偏置电流下的1/f噪声主要来自有源区和漏电电阻,其幅度的大小及其随偏置电流的变化趋势与激光器的可靠性有密切的关系.